1 /* 2 * Test Special Purpose Registers 3 * 4 * Copyright 2017 Thomas Huth, Red Hat Inc. 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 * 8 * The basic idea of this test is to check whether the contents of the Special 9 * Purpose Registers (SPRs) are preserved correctly during migration. So we 10 * fill in the SPRs with a well-known value, read the values back (since not 11 * all bits might be retained in the SPRs), then wait for migration to complete 12 * (if the '-w' option has been specified) so that the user has a chance to 13 * migrate the VM. Alternatively, the test can also simply sleep a little bit 14 * with the H_CEDE hypercall, in the hope that we'll get scheduled to another 15 * host CPU and thus register contents might have changed, too (in case of 16 * bugs). Finally, we read back the values from the SPRs and compare them with 17 * the values before the migration. Mismatches are reported as test failures. 18 * Note that we do not test all SPRs since some of the registers change their 19 * content automatically, and some are only accessible with hypervisor privi- 20 * leges or have bad side effects, so we have to omit those registers. 21 */ 22 #include <libcflat.h> 23 #include <util.h> 24 #include <migrate.h> 25 #include <alloc.h> 26 #include <asm/handlers.h> 27 #include <asm/hcall.h> 28 #include <asm/processor.h> 29 #include <asm/barrier.h> 30 31 uint64_t before[1024], after[1024]; 32 33 /* Common SPRs for all PowerPC CPUs */ 34 static void set_sprs_common(uint64_t val) 35 { 36 mtspr(9, val); /* CTR */ 37 // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */ 38 mtspr(274, val); /* SPRG2 */ 39 mtspr(275, val); /* SPRG3 */ 40 } 41 42 /* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */ 43 static void set_sprs_book3s_201(uint64_t val) 44 { 45 mtspr(18, val); /* DSISR */ 46 mtspr(19, val); /* DAR */ 47 mtspr(152, val); /* CTRL */ 48 mtspr(256, val); /* VRSAVE */ 49 mtspr(786, val); /* MMCRA */ 50 mtspr(795, val); /* MMCR0 */ 51 mtspr(798, val); /* MMCR1 */ 52 } 53 54 /* SPRs from PowerISA 2.07 Book III-S */ 55 static void set_sprs_book3s_207(uint64_t val) 56 { 57 mtspr(3, val); /* DSCR */ 58 mtspr(13, val); /* AMR */ 59 mtspr(17, val); /* DSCR */ 60 mtspr(18, val); /* DSISR */ 61 mtspr(19, val); /* DAR */ 62 mtspr(29, val); /* AMR */ 63 mtspr(61, val); /* IAMR */ 64 // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */ 65 mtspr(153, val); /* FSCR */ 66 mtspr(157, val); /* UAMOR */ 67 mtspr(159, val); /* PSPB */ 68 mtspr(256, val); /* VRSAVE */ 69 // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */ 70 mtspr(769, val); /* MMCR2 */ 71 mtspr(770, val); /* MMCRA */ 72 mtspr(771, val); /* PMC1 */ 73 mtspr(772, val); /* PMC2 */ 74 mtspr(773, val); /* PMC3 */ 75 mtspr(774, val); /* PMC4 */ 76 mtspr(775, val); /* PMC5 */ 77 mtspr(776, val); /* PMC6 */ 78 mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 79 mtspr(784, val); /* SIER */ 80 mtspr(785, val); /* MMCR2 */ 81 mtspr(786, val); /* MMCRA */ 82 mtspr(787, val); /* PMC1 */ 83 mtspr(788, val); /* PMC2 */ 84 mtspr(789, val); /* PMC3 */ 85 mtspr(790, val); /* PMC4 */ 86 mtspr(791, val); /* PMC5 */ 87 mtspr(792, val); /* PMC6 */ 88 mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 89 mtspr(796, val); /* SIAR */ 90 mtspr(797, val); /* SDAR */ 91 mtspr(798, val); /* MMCR1 */ 92 mtspr(800, val); /* BESCRS */ 93 mtspr(801, val); /* BESCCRSU */ 94 mtspr(802, val); /* BESCRR */ 95 mtspr(803, val); /* BESCRRU */ 96 mtspr(804, val); /* EBBHR */ 97 mtspr(805, val); /* EBBRR */ 98 mtspr(806, val); /* BESCR */ 99 mtspr(815, val); /* TAR */ 100 } 101 102 /* SPRs from PowerISA 3.00 Book III */ 103 static void set_sprs_book3s_300(uint64_t val) 104 { 105 set_sprs_book3s_207(val); 106 mtspr(48, val); /* PIDR */ 107 mtspr(144, val); /* TIDR */ 108 mtspr(823, val); /* PSSCR */ 109 } 110 111 /* SPRs from Power ISA Version 3.1B */ 112 static void set_sprs_book3s_31(uint64_t val) 113 { 114 set_sprs_book3s_207(val); 115 mtspr(48, val); /* PIDR */ 116 /* 3.1 removes TIDR */ 117 mtspr(823, val); /* PSSCR */ 118 } 119 120 static void set_sprs(uint64_t val) 121 { 122 uint32_t pvr = mfspr(287); /* Processor Version Register */ 123 124 set_sprs_common(val); 125 126 switch (pvr >> 16) { 127 case 0x39: /* PPC970 */ 128 case 0x3C: /* PPC970FX */ 129 case 0x44: /* PPC970MP */ 130 set_sprs_book3s_201(val); 131 break; 132 case 0x4b: /* POWER8E */ 133 case 0x4c: /* POWER8NVL */ 134 case 0x4d: /* POWER8 */ 135 set_sprs_book3s_207(val); 136 break; 137 case 0x4e: /* POWER9 */ 138 set_sprs_book3s_300(val); 139 break; 140 case 0x80: /* POWER10 */ 141 set_sprs_book3s_31(val); 142 break; 143 default: 144 puts("Warning: Unknown processor version!\n"); 145 } 146 } 147 148 static void get_sprs_common(uint64_t *v) 149 { 150 v[9] = mfspr(9); /* CTR */ 151 // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */ 152 v[274] = mfspr(274); /* SPRG2 */ 153 v[275] = mfspr(275); /* SPRG3 */ 154 } 155 156 static void get_sprs_book3s_201(uint64_t *v) 157 { 158 v[18] = mfspr(18); /* DSISR */ 159 v[19] = mfspr(19); /* DAR */ 160 v[136] = mfspr(136); /* CTRL */ 161 v[256] = mfspr(256); /* VRSAVE */ 162 v[786] = mfspr(786); /* MMCRA */ 163 v[795] = mfspr(795); /* MMCR0 */ 164 v[798] = mfspr(798); /* MMCR1 */ 165 } 166 167 static void get_sprs_book3s_207(uint64_t *v) 168 { 169 v[3] = mfspr(3); /* DSCR */ 170 v[13] = mfspr(13); /* AMR */ 171 v[17] = mfspr(17); /* DSCR */ 172 v[18] = mfspr(18); /* DSISR */ 173 v[19] = mfspr(19); /* DAR */ 174 v[29] = mfspr(29); /* AMR */ 175 v[61] = mfspr(61); /* IAMR */ 176 // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */ 177 v[153] = mfspr(153); /* FSCR */ 178 v[157] = mfspr(157); /* UAMOR */ 179 v[159] = mfspr(159); /* PSPB */ 180 v[256] = mfspr(256); /* VRSAVE */ 181 v[259] = mfspr(259); /* SPRG3 (read only) */ 182 // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */ 183 v[769] = mfspr(769); /* MMCR2 */ 184 v[770] = mfspr(770); /* MMCRA */ 185 v[771] = mfspr(771); /* PMC1 */ 186 v[772] = mfspr(772); /* PMC2 */ 187 v[773] = mfspr(773); /* PMC3 */ 188 v[774] = mfspr(774); /* PMC4 */ 189 v[775] = mfspr(775); /* PMC5 */ 190 v[776] = mfspr(776); /* PMC6 */ 191 v[779] = mfspr(779); /* MMCR0 */ 192 v[780] = mfspr(780); /* SIAR (read only) */ 193 v[781] = mfspr(781); /* SDAR (read only) */ 194 v[782] = mfspr(782); /* MMCR1 (read only) */ 195 v[784] = mfspr(784); /* SIER */ 196 v[785] = mfspr(785); /* MMCR2 */ 197 v[786] = mfspr(786); /* MMCRA */ 198 v[787] = mfspr(787); /* PMC1 */ 199 v[788] = mfspr(788); /* PMC2 */ 200 v[789] = mfspr(789); /* PMC3 */ 201 v[790] = mfspr(790); /* PMC4 */ 202 v[791] = mfspr(791); /* PMC5 */ 203 v[792] = mfspr(792); /* PMC6 */ 204 v[795] = mfspr(795); /* MMCR0 */ 205 v[796] = mfspr(796); /* SIAR */ 206 v[797] = mfspr(797); /* SDAR */ 207 v[798] = mfspr(798); /* MMCR1 */ 208 v[800] = mfspr(800); /* BESCRS */ 209 v[801] = mfspr(801); /* BESCCRSU */ 210 v[802] = mfspr(802); /* BESCRR */ 211 v[803] = mfspr(803); /* BESCRRU */ 212 v[804] = mfspr(804); /* EBBHR */ 213 v[805] = mfspr(805); /* EBBRR */ 214 v[806] = mfspr(806); /* BESCR */ 215 v[815] = mfspr(815); /* TAR */ 216 } 217 218 static void get_sprs_book3s_300(uint64_t *v) 219 { 220 get_sprs_book3s_207(v); 221 v[48] = mfspr(48); /* PIDR */ 222 v[144] = mfspr(144); /* TIDR */ 223 v[823] = mfspr(823); /* PSSCR */ 224 } 225 226 static void get_sprs_book3s_31(uint64_t *v) 227 { 228 get_sprs_book3s_207(v); 229 v[48] = mfspr(48); /* PIDR */ 230 v[823] = mfspr(823); /* PSSCR */ 231 } 232 233 static void get_sprs(uint64_t *v) 234 { 235 uint32_t pvr = mfspr(287); /* Processor Version Register */ 236 237 get_sprs_common(v); 238 239 switch (pvr >> 16) { 240 case 0x39: /* PPC970 */ 241 case 0x3C: /* PPC970FX */ 242 case 0x44: /* PPC970MP */ 243 get_sprs_book3s_201(v); 244 break; 245 case 0x4b: /* POWER8E */ 246 case 0x4c: /* POWER8NVL */ 247 case 0x4d: /* POWER8 */ 248 get_sprs_book3s_207(v); 249 break; 250 case 0x4e: /* POWER9 */ 251 get_sprs_book3s_300(v); 252 break; 253 case 0x80: /* POWER10 */ 254 get_sprs_book3s_31(v); 255 break; 256 } 257 } 258 259 int main(int argc, char **argv) 260 { 261 int i; 262 bool pause = false; 263 uint64_t pat = 0xcafefacec0debabeULL; 264 const uint64_t patterns[] = { 265 0xcafefacec0debabeULL, ~0xcafefacec0debabeULL, 266 0xAAAA5555AAAA5555ULL, 0x5555AAAA5555AAAAULL, 267 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL, 268 -1ULL, 269 }; 270 271 for (i = 1; i < argc; i++) { 272 if (!strcmp(argv[i], "-w")) { 273 pause = true; 274 } else if (!strcmp(argv[i], "-p")) { 275 i += 1; 276 if (i >= argc || *argv[i] < '0' 277 || *argv[i] >= '0' + ARRAY_SIZE(patterns)) 278 report_abort("Error: bad value for -p"); 279 pat ^= patterns[*argv[i] - '0']; 280 } else if (!strcmp(argv[i], "-t")) { 281 /* Randomize with timebase register */ 282 asm volatile("mftb %0" : "=r"(i)); 283 pat ^= i; 284 asm volatile("mftb %0" : "=r"(i)); 285 pat ^= ~(uint64_t)i << 32; 286 } else { 287 report_abort("Warning: Unsupported argument: %s", 288 argv[i]); 289 } 290 } 291 292 printf("Settings SPRs to %#lx...\n", pat); 293 set_sprs(pat); 294 295 memset(before, 0, sizeof(before)); 296 memset(after, 0, sizeof(after)); 297 298 get_sprs(before); 299 300 if (pause) { 301 migrate_once(); 302 } else { 303 msleep(2000); 304 } 305 306 get_sprs(after); 307 308 puts("Checking SPRs...\n"); 309 for (i = 0; i < 1024; i++) { 310 if (before[i] != 0 || after[i] != 0) 311 report(before[i] == after[i], 312 "SPR %d:\t%#018lx <==> %#018lx", i, before[i], 313 after[i]); 314 } 315 316 return report_summary(); 317 } 318