1 /* 2 * Test Special Purpose Registers 3 * 4 * Copyright 2017 Thomas Huth, Red Hat Inc. 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 * 8 * The basic idea of this test is to check whether the contents of the Special 9 * Purpose Registers (SPRs) are preserved correctly during migration. So we 10 * fill in the SPRs with a well-known value, read the values back (since not 11 * all bits might be retained in the SPRs), then wait for migration to complete 12 * (if the '-w' option has been specified) so that the user has a chance to 13 * migrate the VM. Alternatively, the test can also simply sleep a little bit 14 * with the H_CEDE hypercall, in the hope that we'll get scheduled to another 15 * host CPU and thus register contents might have changed, too (in case of 16 * bugs). Finally, we read back the values from the SPRs and compare them with 17 * the values before the migration. Mismatches are reported as test failures. 18 * Note that we do not test all SPRs since some of the registers change their 19 * content automatically, and some are only accessible with hypervisor privi- 20 * leges or have bad side effects, so we have to omit those registers. 21 */ 22 #include <libcflat.h> 23 #include <util.h> 24 #include <alloc.h> 25 #include <asm/handlers.h> 26 #include <asm/hcall.h> 27 #include <asm/processor.h> 28 #include <asm/barrier.h> 29 30 #define mfspr(nr) ({ \ 31 uint64_t ret; \ 32 asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \ 33 ret; \ 34 }) 35 36 #define mtspr(nr, val) \ 37 asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val)) 38 39 uint64_t before[1024], after[1024]; 40 41 /* Common SPRs for all PowerPC CPUs */ 42 static void set_sprs_common(uint64_t val) 43 { 44 mtspr(9, val); /* CTR */ 45 // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */ 46 mtspr(274, val); /* SPRG2 */ 47 mtspr(275, val); /* SPRG3 */ 48 } 49 50 /* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */ 51 static void set_sprs_book3s_201(uint64_t val) 52 { 53 mtspr(18, val); /* DSISR */ 54 mtspr(19, val); /* DAR */ 55 mtspr(152, val); /* CTRL */ 56 mtspr(256, val); /* VRSAVE */ 57 mtspr(786, val); /* MMCRA */ 58 mtspr(795, val); /* MMCR0 */ 59 mtspr(798, val); /* MMCR1 */ 60 } 61 62 /* SPRs from PowerISA 2.07 Book III-S */ 63 static void set_sprs_book3s_207(uint64_t val) 64 { 65 mtspr(3, val); /* DSCR */ 66 mtspr(13, val); /* AMR */ 67 mtspr(17, val); /* DSCR */ 68 mtspr(18, val); /* DSISR */ 69 mtspr(19, val); /* DAR */ 70 mtspr(29, val); /* AMR */ 71 mtspr(61, val); /* IAMR */ 72 // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */ 73 mtspr(153, val); /* FSCR */ 74 mtspr(157, val); /* UAMOR */ 75 mtspr(159, val); /* PSPB */ 76 mtspr(256, val); /* VRSAVE */ 77 // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */ 78 mtspr(769, val); /* MMCR2 */ 79 mtspr(770, val); /* MMCRA */ 80 mtspr(771, val); /* PMC1 */ 81 mtspr(772, val); /* PMC2 */ 82 mtspr(773, val); /* PMC3 */ 83 mtspr(774, val); /* PMC4 */ 84 mtspr(775, val); /* PMC5 */ 85 mtspr(776, val); /* PMC6 */ 86 mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 87 mtspr(784, val); /* SIER */ 88 mtspr(785, val); /* MMCR2 */ 89 mtspr(786, val); /* MMCRA */ 90 mtspr(787, val); /* PMC1 */ 91 mtspr(788, val); /* PMC2 */ 92 mtspr(789, val); /* PMC3 */ 93 mtspr(790, val); /* PMC4 */ 94 mtspr(791, val); /* PMC5 */ 95 mtspr(792, val); /* PMC6 */ 96 mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 97 mtspr(796, val); /* SIAR */ 98 mtspr(797, val); /* SDAR */ 99 mtspr(798, val); /* MMCR1 */ 100 mtspr(800, val); /* BESCRS */ 101 mtspr(801, val); /* BESCCRSU */ 102 mtspr(802, val); /* BESCRR */ 103 mtspr(803, val); /* BESCRRU */ 104 mtspr(804, val); /* EBBHR */ 105 mtspr(805, val); /* EBBRR */ 106 mtspr(806, val); /* BESCR */ 107 mtspr(815, val); /* TAR */ 108 } 109 110 /* SPRs from PowerISA 3.00 Book III */ 111 static void set_sprs_book3s_300(uint64_t val) 112 { 113 set_sprs_book3s_207(val); 114 mtspr(48, val); /* PIDR */ 115 mtspr(144, val); /* TIDR */ 116 mtspr(823, val); /* PSSCR */ 117 } 118 119 static void set_sprs(uint64_t val) 120 { 121 uint32_t pvr = mfspr(287); /* Processor Version Register */ 122 123 set_sprs_common(val); 124 125 switch (pvr >> 16) { 126 case 0x39: /* PPC970 */ 127 case 0x3C: /* PPC970FX */ 128 case 0x44: /* PPC970MP */ 129 set_sprs_book3s_201(val); 130 break; 131 case 0x4b: /* POWER8E */ 132 case 0x4c: /* POWER8NVL */ 133 case 0x4d: /* POWER8 */ 134 set_sprs_book3s_207(val); 135 break; 136 case 0x4e: /* POWER9 */ 137 set_sprs_book3s_300(val); 138 break; 139 default: 140 puts("Warning: Unknown processor version!\n"); 141 } 142 } 143 144 static void get_sprs_common(uint64_t *v) 145 { 146 v[9] = mfspr(9); /* CTR */ 147 // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */ 148 v[274] = mfspr(274); /* SPRG2 */ 149 v[275] = mfspr(275); /* SPRG3 */ 150 } 151 152 static void get_sprs_book3s_201(uint64_t *v) 153 { 154 v[18] = mfspr(18); /* DSISR */ 155 v[19] = mfspr(19); /* DAR */ 156 v[136] = mfspr(136); /* CTRL */ 157 v[256] = mfspr(256); /* VRSAVE */ 158 v[786] = mfspr(786); /* MMCRA */ 159 v[795] = mfspr(795); /* MMCR0 */ 160 v[798] = mfspr(798); /* MMCR1 */ 161 } 162 163 static void get_sprs_book3s_207(uint64_t *v) 164 { 165 v[3] = mfspr(3); /* DSCR */ 166 v[13] = mfspr(13); /* AMR */ 167 v[17] = mfspr(17); /* DSCR */ 168 v[18] = mfspr(18); /* DSISR */ 169 v[19] = mfspr(19); /* DAR */ 170 v[29] = mfspr(29); /* AMR */ 171 v[61] = mfspr(61); /* IAMR */ 172 // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */ 173 v[153] = mfspr(153); /* FSCR */ 174 v[157] = mfspr(157); /* UAMOR */ 175 v[159] = mfspr(159); /* PSPB */ 176 v[256] = mfspr(256); /* VRSAVE */ 177 v[259] = mfspr(259); /* SPRG3 (read only) */ 178 // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */ 179 v[769] = mfspr(769); /* MMCR2 */ 180 v[770] = mfspr(770); /* MMCRA */ 181 v[771] = mfspr(771); /* PMC1 */ 182 v[772] = mfspr(772); /* PMC2 */ 183 v[773] = mfspr(773); /* PMC3 */ 184 v[774] = mfspr(774); /* PMC4 */ 185 v[775] = mfspr(775); /* PMC5 */ 186 v[776] = mfspr(776); /* PMC6 */ 187 v[779] = mfspr(779); /* MMCR0 */ 188 v[780] = mfspr(780); /* SIAR (read only) */ 189 v[781] = mfspr(781); /* SDAR (read only) */ 190 v[782] = mfspr(782); /* MMCR1 (read only) */ 191 v[784] = mfspr(784); /* SIER */ 192 v[785] = mfspr(785); /* MMCR2 */ 193 v[786] = mfspr(786); /* MMCRA */ 194 v[787] = mfspr(787); /* PMC1 */ 195 v[788] = mfspr(788); /* PMC2 */ 196 v[789] = mfspr(789); /* PMC3 */ 197 v[790] = mfspr(790); /* PMC4 */ 198 v[791] = mfspr(791); /* PMC5 */ 199 v[792] = mfspr(792); /* PMC6 */ 200 v[795] = mfspr(795); /* MMCR0 */ 201 v[796] = mfspr(796); /* SIAR */ 202 v[797] = mfspr(797); /* SDAR */ 203 v[798] = mfspr(798); /* MMCR1 */ 204 v[800] = mfspr(800); /* BESCRS */ 205 v[801] = mfspr(801); /* BESCCRSU */ 206 v[802] = mfspr(802); /* BESCRR */ 207 v[803] = mfspr(803); /* BESCRRU */ 208 v[804] = mfspr(804); /* EBBHR */ 209 v[805] = mfspr(805); /* EBBRR */ 210 v[806] = mfspr(806); /* BESCR */ 211 v[815] = mfspr(815); /* TAR */ 212 } 213 214 static void get_sprs_book3s_300(uint64_t *v) 215 { 216 get_sprs_book3s_207(v); 217 v[48] = mfspr(48); /* PIDR */ 218 v[144] = mfspr(144); /* TIDR */ 219 v[823] = mfspr(823); /* PSSCR */ 220 } 221 222 static void get_sprs(uint64_t *v) 223 { 224 uint32_t pvr = mfspr(287); /* Processor Version Register */ 225 226 get_sprs_common(v); 227 228 switch (pvr >> 16) { 229 case 0x39: /* PPC970 */ 230 case 0x3C: /* PPC970FX */ 231 case 0x44: /* PPC970MP */ 232 get_sprs_book3s_201(v); 233 break; 234 case 0x4b: /* POWER8E */ 235 case 0x4c: /* POWER8NVL */ 236 case 0x4d: /* POWER8 */ 237 get_sprs_book3s_207(v); 238 break; 239 case 0x4e: /* POWER9 */ 240 get_sprs_book3s_300(v); 241 break; 242 } 243 } 244 245 int main(int argc, char **argv) 246 { 247 int i; 248 bool pause = false; 249 uint64_t pat = 0xcafefacec0debabeULL; 250 const uint64_t patterns[] = { 251 0xcafefacec0debabeULL, ~0xcafefacec0debabeULL, 252 0xAAAA5555AAAA5555ULL, 0x5555AAAA5555AAAAULL, 253 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL, 254 -1ULL, 255 }; 256 257 for (i = 1; i < argc; i++) { 258 if (!strcmp(argv[i], "-w")) { 259 pause = true; 260 } else if (!strcmp(argv[i], "-p")) { 261 i += 1; 262 if (i >= argc || *argv[i] < '0' 263 || *argv[i] >= '0' + ARRAY_SIZE(patterns)) 264 report_abort("Error: bad value for -p"); 265 pat ^= patterns[*argv[i] - '0']; 266 } else if (!strcmp(argv[i], "-t")) { 267 /* Randomize with timebase register */ 268 asm volatile("mftb %0" : "=r"(i)); 269 pat ^= i; 270 asm volatile("mftb %0" : "=r"(i)); 271 pat ^= ~(uint64_t)i << 32; 272 } else { 273 report_abort("Warning: Unsupported argument: %s", 274 argv[i]); 275 } 276 } 277 278 printf("Settings SPRs to %#lx...\n", pat); 279 set_sprs(pat); 280 281 memset(before, 0, sizeof(before)); 282 memset(after, 0, sizeof(after)); 283 284 get_sprs(before); 285 286 if (pause) { 287 puts("Now migrate the VM, then press a key to continue...\n"); 288 (void) getchar(); 289 } else { 290 puts("Sleeping...\n"); 291 handle_exception(0x900, &dec_except_handler, NULL); 292 asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF)); 293 hcall(H_CEDE); 294 } 295 296 get_sprs(after); 297 298 puts("Checking SPRs...\n"); 299 for (i = 0; i < 1024; i++) { 300 if (before[i] != 0 || after[i] != 0) 301 report("SPR %d:\t%#018lx <==> %#018lx", 302 before[i] == after[i], i, before[i], after[i]); 303 } 304 305 return report_summary(); 306 } 307