xref: /kvm-unit-tests/powerpc/sprs.c (revision 3ff90d5f4eb7d3064bd34e887a4abdfa89565bbd)
1ee30cf14SThomas Huth /*
2ee30cf14SThomas Huth  * Test Special Purpose Registers
3ee30cf14SThomas Huth  *
4ee30cf14SThomas Huth  * Copyright 2017  Thomas Huth, Red Hat Inc.
5ee30cf14SThomas Huth  *
6ee30cf14SThomas Huth  * This work is licensed under the terms of the GNU LGPL, version 2.
7ee30cf14SThomas Huth  *
8ee30cf14SThomas Huth  * The basic idea of this test is to check whether the contents of the Special
9ee30cf14SThomas Huth  * Purpose Registers (SPRs) are preserved correctly during migration. So we
10ee30cf14SThomas Huth  * fill in the SPRs with a well-known value, read the values back (since not
11ffd9da55SAndrew Jones  * all bits might be retained in the SPRs), then wait for migration to complete
12ffd9da55SAndrew Jones  * (if the '-w' option has been specified) so that the user has a chance to
13ffd9da55SAndrew Jones  * migrate the VM. Alternatively, the test can also simply sleep a little bit
14ffd9da55SAndrew Jones  * with the H_CEDE hypercall, in the hope that we'll get scheduled to another
15ffd9da55SAndrew Jones  * host CPU and thus register contents might have changed, too (in case of
16ffd9da55SAndrew Jones  * bugs). Finally, we read back the values from the SPRs and compare them with
17ffd9da55SAndrew Jones  * the values before the migration. Mismatches are reported as test failures.
18ee30cf14SThomas Huth  * Note that we do not test all SPRs since some of the registers change their
19ee30cf14SThomas Huth  * content automatically, and some are only accessible with hypervisor privi-
20ee30cf14SThomas Huth  * leges or have bad side effects, so we have to omit those registers.
21ee30cf14SThomas Huth  */
22ee30cf14SThomas Huth #include <libcflat.h>
23ee30cf14SThomas Huth #include <util.h>
24ee30cf14SThomas Huth #include <alloc.h>
25ee30cf14SThomas Huth #include <asm/handlers.h>
26ee30cf14SThomas Huth #include <asm/hcall.h>
27ee30cf14SThomas Huth #include <asm/processor.h>
28ee30cf14SThomas Huth #include <asm/barrier.h>
29ee30cf14SThomas Huth 
30ee30cf14SThomas Huth #define mfspr(nr) ({ \
31ee30cf14SThomas Huth 	uint64_t ret; \
32ee30cf14SThomas Huth 	asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \
33ee30cf14SThomas Huth 	ret; \
34ee30cf14SThomas Huth })
35ee30cf14SThomas Huth 
36ee30cf14SThomas Huth #define mtspr(nr, val) \
37ee30cf14SThomas Huth 	asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val))
38ee30cf14SThomas Huth 
39ee30cf14SThomas Huth uint64_t before[1024], after[1024];
40ee30cf14SThomas Huth 
41ee30cf14SThomas Huth /* Common SPRs for all PowerPC CPUs */
42ee30cf14SThomas Huth static void set_sprs_common(uint64_t val)
43ee30cf14SThomas Huth {
44ee30cf14SThomas Huth 	mtspr(9, val);		/* CTR */
45ee30cf14SThomas Huth 	// mtspr(273, val);	/* SPRG1 */  /* Used by our exception handler */
46ee30cf14SThomas Huth 	mtspr(274, val);	/* SPRG2 */
47ee30cf14SThomas Huth 	mtspr(275, val);	/* SPRG3 */
48ee30cf14SThomas Huth }
49ee30cf14SThomas Huth 
50ee30cf14SThomas Huth /* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */
51ee30cf14SThomas Huth static void set_sprs_book3s_201(uint64_t val)
52ee30cf14SThomas Huth {
53ee30cf14SThomas Huth 	mtspr(18, val);		/* DSISR */
54ee30cf14SThomas Huth 	mtspr(19, val);		/* DAR */
55ee30cf14SThomas Huth 	mtspr(152, val);	/* CTRL */
56ee30cf14SThomas Huth 	mtspr(256, val);	/* VRSAVE */
57ee30cf14SThomas Huth 	mtspr(786, val);	/* MMCRA */
58ee30cf14SThomas Huth 	mtspr(795, val);	/* MMCR0 */
59ee30cf14SThomas Huth 	mtspr(798, val);	/* MMCR1 */
60ee30cf14SThomas Huth }
61ee30cf14SThomas Huth 
62ee30cf14SThomas Huth /* SPRs from PowerISA 2.07 Book III-S */
63ee30cf14SThomas Huth static void set_sprs_book3s_207(uint64_t val)
64ee30cf14SThomas Huth {
65ee30cf14SThomas Huth 	mtspr(3, val);		/* DSCR */
66ee30cf14SThomas Huth 	mtspr(13, val);		/* AMR */
67ee30cf14SThomas Huth 	mtspr(17, val);		/* DSCR */
68ee30cf14SThomas Huth 	mtspr(18, val);		/* DSISR */
69ee30cf14SThomas Huth 	mtspr(19, val);		/* DAR */
70ee30cf14SThomas Huth 	mtspr(29, val);		/* AMR */
71ee30cf14SThomas Huth 	mtspr(61, val);		/* IAMR */
72ee30cf14SThomas Huth 	// mtspr(152, val);	/* CTRL */  /* TODO: Needs a fix in KVM */
73ee30cf14SThomas Huth 	mtspr(153, val);	/* FSCR */
74ee30cf14SThomas Huth 	mtspr(157, val);	/* UAMOR */
75ee30cf14SThomas Huth 	mtspr(159, val);	/* PSPB */
76ee30cf14SThomas Huth 	mtspr(256, val);	/* VRSAVE */
77ee30cf14SThomas Huth 	// mtspr(272, val);	/* SPRG0 */ /* Used by our exception handler */
78ee30cf14SThomas Huth 	mtspr(769, val);	/* MMCR2 */
79ee30cf14SThomas Huth 	mtspr(770, val);	/* MMCRA */
80ee30cf14SThomas Huth 	mtspr(771, val);	/* PMC1 */
81ee30cf14SThomas Huth 	mtspr(772, val);	/* PMC2 */
82ee30cf14SThomas Huth 	mtspr(773, val);	/* PMC3 */
83ee30cf14SThomas Huth 	mtspr(774, val);	/* PMC4 */
84ee30cf14SThomas Huth 	mtspr(775, val);	/* PMC5 */
85ee30cf14SThomas Huth 	mtspr(776, val);	/* PMC6 */
86ee30cf14SThomas Huth 	mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070);	/* MMCR0 */
87ee30cf14SThomas Huth 	mtspr(784, val);	/* SIER */
88ee30cf14SThomas Huth 	mtspr(785, val);	/* MMCR2 */
89ee30cf14SThomas Huth 	mtspr(786, val);	/* MMCRA */
90ee30cf14SThomas Huth 	mtspr(787, val);	/* PMC1 */
91ee30cf14SThomas Huth 	mtspr(788, val);	/* PMC2 */
92ee30cf14SThomas Huth 	mtspr(789, val);	/* PMC3 */
93ee30cf14SThomas Huth 	mtspr(790, val);	/* PMC4 */
94ee30cf14SThomas Huth 	mtspr(791, val);	/* PMC5 */
95ee30cf14SThomas Huth 	mtspr(792, val);	/* PMC6 */
96ee30cf14SThomas Huth 	mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070);	/* MMCR0 */
97ee30cf14SThomas Huth 	mtspr(796, val);	/* SIAR */
98ee30cf14SThomas Huth 	mtspr(797, val);	/* SDAR */
99ee30cf14SThomas Huth 	mtspr(798, val);	/* MMCR1 */
100ee30cf14SThomas Huth 	mtspr(800, val);	/* BESCRS */
101ee30cf14SThomas Huth 	mtspr(801, val);	/* BESCCRSU */
102ee30cf14SThomas Huth 	mtspr(802, val);	/* BESCRR */
103ee30cf14SThomas Huth 	mtspr(803, val);	/* BESCRRU */
104ee30cf14SThomas Huth 	mtspr(804, val);	/* EBBHR */
105ee30cf14SThomas Huth 	mtspr(805, val);	/* EBBRR */
106ee30cf14SThomas Huth 	mtspr(806, val);	/* BESCR */
107ee30cf14SThomas Huth 	mtspr(815, val);	/* TAR */
108ee30cf14SThomas Huth }
109ee30cf14SThomas Huth 
11025a302cbSThomas Huth /* SPRs from PowerISA 3.00 Book III */
11125a302cbSThomas Huth static void set_sprs_book3s_300(uint64_t val)
11225a302cbSThomas Huth {
11325a302cbSThomas Huth 	set_sprs_book3s_207(val);
11425a302cbSThomas Huth 	mtspr(48, val);		/* PIDR */
11525a302cbSThomas Huth 	mtspr(144, val);	/* TIDR */
11625a302cbSThomas Huth 	mtspr(823, val);	/* PSSCR */
11725a302cbSThomas Huth }
11825a302cbSThomas Huth 
119ee30cf14SThomas Huth static void set_sprs(uint64_t val)
120ee30cf14SThomas Huth {
121ee30cf14SThomas Huth 	uint32_t pvr = mfspr(287);	/* Processor Version Register */
122ee30cf14SThomas Huth 
123ee30cf14SThomas Huth 	set_sprs_common(val);
124ee30cf14SThomas Huth 
125ee30cf14SThomas Huth 	switch (pvr >> 16) {
126ee30cf14SThomas Huth 	case 0x39:			/* PPC970 */
127ee30cf14SThomas Huth 	case 0x3C:			/* PPC970FX */
128ee30cf14SThomas Huth 	case 0x44:			/* PPC970MP */
129ee30cf14SThomas Huth 		set_sprs_book3s_201(val);
130ee30cf14SThomas Huth 		break;
131ee30cf14SThomas Huth 	case 0x4b:			/* POWER8E */
132ee30cf14SThomas Huth 	case 0x4c:			/* POWER8NVL */
133ee30cf14SThomas Huth 	case 0x4d:			/* POWER8 */
134ee30cf14SThomas Huth 		set_sprs_book3s_207(val);
135ee30cf14SThomas Huth 		break;
13625a302cbSThomas Huth 	case 0x4e:			/* POWER9 */
13725a302cbSThomas Huth 		set_sprs_book3s_300(val);
13825a302cbSThomas Huth 		break;
139ee30cf14SThomas Huth 	default:
140ee30cf14SThomas Huth 		puts("Warning: Unknown processor version!\n");
141ee30cf14SThomas Huth 	}
142ee30cf14SThomas Huth }
143ee30cf14SThomas Huth 
144ee30cf14SThomas Huth static void get_sprs_common(uint64_t *v)
145ee30cf14SThomas Huth {
146ee30cf14SThomas Huth 	v[9] = mfspr(9);	/* CTR */
147ee30cf14SThomas Huth 	// v[273] = mfspr(273);	/* SPRG1 */ /* Used by our exception handler */
148ee30cf14SThomas Huth 	v[274] = mfspr(274);	/* SPRG2 */
149ee30cf14SThomas Huth 	v[275] = mfspr(275);	/* SPRG3 */
150ee30cf14SThomas Huth }
151ee30cf14SThomas Huth 
152ee30cf14SThomas Huth static void get_sprs_book3s_201(uint64_t *v)
153ee30cf14SThomas Huth {
154ee30cf14SThomas Huth 	v[18] = mfspr(18);	/* DSISR */
155ee30cf14SThomas Huth 	v[19] = mfspr(19);	/* DAR */
156ee30cf14SThomas Huth 	v[136] = mfspr(136);	/* CTRL */
157ee30cf14SThomas Huth 	v[256] = mfspr(256);	/* VRSAVE */
158ee30cf14SThomas Huth 	v[786] = mfspr(786);	/* MMCRA */
159ee30cf14SThomas Huth 	v[795] = mfspr(795);	/* MMCR0 */
160ee30cf14SThomas Huth 	v[798] = mfspr(798);	/* MMCR1 */
161ee30cf14SThomas Huth }
162ee30cf14SThomas Huth 
163ee30cf14SThomas Huth static void get_sprs_book3s_207(uint64_t *v)
164ee30cf14SThomas Huth {
165ee30cf14SThomas Huth 	v[3] = mfspr(3);	/* DSCR */
166ee30cf14SThomas Huth 	v[13] = mfspr(13);	/* AMR */
167ee30cf14SThomas Huth 	v[17] = mfspr(17);	/* DSCR */
168ee30cf14SThomas Huth 	v[18] = mfspr(18);	/* DSISR */
169ee30cf14SThomas Huth 	v[19] = mfspr(19);	/* DAR */
170ee30cf14SThomas Huth 	v[29] = mfspr(29);	/* AMR */
171ee30cf14SThomas Huth 	v[61] = mfspr(61);	/* IAMR */
172ee30cf14SThomas Huth 	// v[136] = mfspr(136);	/* CTRL */  /* TODO: Needs a fix in KVM */
173ee30cf14SThomas Huth 	v[153] = mfspr(153);	/* FSCR */
174ee30cf14SThomas Huth 	v[157] = mfspr(157);	/* UAMOR */
175ee30cf14SThomas Huth 	v[159] = mfspr(159);	/* PSPB */
176ee30cf14SThomas Huth 	v[256] = mfspr(256);	/* VRSAVE */
177ee30cf14SThomas Huth 	v[259] = mfspr(259);	/* SPRG3 (read only) */
178ee30cf14SThomas Huth 	// v[272] = mfspr(272);	/* SPRG0 */  /* Used by our exception handler */
179ee30cf14SThomas Huth 	v[769] = mfspr(769);	/* MMCR2 */
180ee30cf14SThomas Huth 	v[770] = mfspr(770);	/* MMCRA */
181ee30cf14SThomas Huth 	v[771] = mfspr(771);	/* PMC1 */
182ee30cf14SThomas Huth 	v[772] = mfspr(772);	/* PMC2 */
183ee30cf14SThomas Huth 	v[773] = mfspr(773);	/* PMC3 */
184ee30cf14SThomas Huth 	v[774] = mfspr(774);	/* PMC4 */
185ee30cf14SThomas Huth 	v[775] = mfspr(775);	/* PMC5 */
186ee30cf14SThomas Huth 	v[776] = mfspr(776);	/* PMC6 */
187ee30cf14SThomas Huth 	v[779] = mfspr(779);	/* MMCR0 */
188ee30cf14SThomas Huth 	v[780] = mfspr(780);	/* SIAR (read only) */
189ee30cf14SThomas Huth 	v[781] = mfspr(781);	/* SDAR (read only) */
190ee30cf14SThomas Huth 	v[782] = mfspr(782);	/* MMCR1 (read only) */
191ee30cf14SThomas Huth 	v[784] = mfspr(784);	/* SIER */
192ee30cf14SThomas Huth 	v[785] = mfspr(785);	/* MMCR2 */
193ee30cf14SThomas Huth 	v[786] = mfspr(786);	/* MMCRA */
194ee30cf14SThomas Huth 	v[787] = mfspr(787);	/* PMC1 */
195ee30cf14SThomas Huth 	v[788] = mfspr(788);	/* PMC2 */
196ee30cf14SThomas Huth 	v[789] = mfspr(789);	/* PMC3 */
197ee30cf14SThomas Huth 	v[790] = mfspr(790);	/* PMC4 */
198ee30cf14SThomas Huth 	v[791] = mfspr(791);	/* PMC5 */
199ee30cf14SThomas Huth 	v[792] = mfspr(792);	/* PMC6 */
200ee30cf14SThomas Huth 	v[795] = mfspr(795);	/* MMCR0 */
201ee30cf14SThomas Huth 	v[796] = mfspr(796);	/* SIAR */
202ee30cf14SThomas Huth 	v[797] = mfspr(797);	/* SDAR */
203ee30cf14SThomas Huth 	v[798] = mfspr(798);	/* MMCR1 */
204ee30cf14SThomas Huth 	v[800] = mfspr(800);	/* BESCRS */
205ee30cf14SThomas Huth 	v[801] = mfspr(801);	/* BESCCRSU */
206ee30cf14SThomas Huth 	v[802] = mfspr(802);	/* BESCRR */
207ee30cf14SThomas Huth 	v[803] = mfspr(803);	/* BESCRRU */
208ee30cf14SThomas Huth 	v[804] = mfspr(804);	/* EBBHR */
209ee30cf14SThomas Huth 	v[805] = mfspr(805);	/* EBBRR */
210ee30cf14SThomas Huth 	v[806] = mfspr(806);	/* BESCR */
211ee30cf14SThomas Huth 	v[815] = mfspr(815);	/* TAR */
212ee30cf14SThomas Huth }
213ee30cf14SThomas Huth 
21425a302cbSThomas Huth static void get_sprs_book3s_300(uint64_t *v)
21525a302cbSThomas Huth {
21625a302cbSThomas Huth 	get_sprs_book3s_207(v);
21725a302cbSThomas Huth 	v[48] = mfspr(48);	/* PIDR */
21825a302cbSThomas Huth 	v[144] = mfspr(144);	/* TIDR */
21925a302cbSThomas Huth 	v[823] = mfspr(823);	/* PSSCR */
22025a302cbSThomas Huth }
22125a302cbSThomas Huth 
222ee30cf14SThomas Huth static void get_sprs(uint64_t *v)
223ee30cf14SThomas Huth {
224ee30cf14SThomas Huth 	uint32_t pvr = mfspr(287);	/* Processor Version Register */
225ee30cf14SThomas Huth 
226ee30cf14SThomas Huth 	get_sprs_common(v);
227ee30cf14SThomas Huth 
228ee30cf14SThomas Huth 	switch (pvr >> 16) {
229ee30cf14SThomas Huth 	case 0x39:			/* PPC970 */
230ee30cf14SThomas Huth 	case 0x3C:			/* PPC970FX */
231ee30cf14SThomas Huth 	case 0x44:			/* PPC970MP */
232ee30cf14SThomas Huth 		get_sprs_book3s_201(v);
233ee30cf14SThomas Huth 		break;
234ee30cf14SThomas Huth 	case 0x4b:			/* POWER8E */
235ee30cf14SThomas Huth 	case 0x4c:			/* POWER8NVL */
236ee30cf14SThomas Huth 	case 0x4d:			/* POWER8 */
237ee30cf14SThomas Huth 		get_sprs_book3s_207(v);
238ee30cf14SThomas Huth 		break;
23925a302cbSThomas Huth 	case 0x4e:			/* POWER9 */
24025a302cbSThomas Huth 		get_sprs_book3s_300(v);
24125a302cbSThomas Huth 		break;
242ee30cf14SThomas Huth 	}
243ee30cf14SThomas Huth }
244ee30cf14SThomas Huth 
245ee30cf14SThomas Huth int main(int argc, char **argv)
246ee30cf14SThomas Huth {
247ee30cf14SThomas Huth 	int i;
248ee30cf14SThomas Huth 	bool pause = false;
249ee30cf14SThomas Huth 	uint64_t pat = 0xcafefacec0debabeULL;
250ee30cf14SThomas Huth 	const uint64_t patterns[] = {
251ee30cf14SThomas Huth 		0xcafefacec0debabeULL, ~0xcafefacec0debabeULL,
252ee30cf14SThomas Huth 		0xAAAA5555AAAA5555ULL, 0x5555AAAA5555AAAAULL,
253ee30cf14SThomas Huth 		0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL,
254ee30cf14SThomas Huth 		-1ULL,
255ee30cf14SThomas Huth 	};
256*3ff90d5fSSuraj Jitindar Singh 	static uint64_t decr = 0x7FFFFFFF; /* Max value */
257ee30cf14SThomas Huth 
258ee30cf14SThomas Huth 	for (i = 1; i < argc; i++) {
259ee30cf14SThomas Huth 		if (!strcmp(argv[i], "-w")) {
260ee30cf14SThomas Huth 			pause = true;
261ee30cf14SThomas Huth 		} else if (!strcmp(argv[i], "-p")) {
262ee30cf14SThomas Huth 			i += 1;
263ee30cf14SThomas Huth 			if (i >= argc || *argv[i] < '0'
264ee30cf14SThomas Huth 			    || *argv[i] >= '0' + ARRAY_SIZE(patterns))
265ee30cf14SThomas Huth 				report_abort("Error: bad value for -p");
266ee30cf14SThomas Huth 			pat ^= patterns[*argv[i] - '0'];
267ee30cf14SThomas Huth 		} else if (!strcmp(argv[i], "-t")) {
268ee30cf14SThomas Huth 			/* Randomize with timebase register */
269ee30cf14SThomas Huth 			asm volatile("mftb %0" : "=r"(i));
270ee30cf14SThomas Huth 			pat ^= i;
271ee30cf14SThomas Huth 			asm volatile("mftb %0" : "=r"(i));
272ee30cf14SThomas Huth 			pat ^= ~(uint64_t)i << 32;
273ee30cf14SThomas Huth 		} else {
274ee30cf14SThomas Huth 			report_abort("Warning: Unsupported argument: %s",
275ee30cf14SThomas Huth 			             argv[i]);
276ee30cf14SThomas Huth 		}
277ee30cf14SThomas Huth 	}
278ee30cf14SThomas Huth 
279fd6aada0SRadim Krčmář 	printf("Settings SPRs to %#lx...\n", pat);
280ee30cf14SThomas Huth 	set_sprs(pat);
281ee30cf14SThomas Huth 
282ee30cf14SThomas Huth 	memset(before, 0, sizeof(before));
283ee30cf14SThomas Huth 	memset(after, 0, sizeof(after));
284ee30cf14SThomas Huth 
285ee30cf14SThomas Huth 	get_sprs(before);
286ee30cf14SThomas Huth 
287ee30cf14SThomas Huth 	if (pause) {
288ffd9da55SAndrew Jones 		puts("Now migrate the VM, then press a key to continue...\n");
2891aee4297SAndrew Jones 		(void) getchar();
290ee30cf14SThomas Huth 	} else {
291ee30cf14SThomas Huth 		puts("Sleeping...\n");
292*3ff90d5fSSuraj Jitindar Singh 		handle_exception(0x900, &dec_except_handler, &decr);
293ee30cf14SThomas Huth 		asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF));
294ee30cf14SThomas Huth 		hcall(H_CEDE);
295ee30cf14SThomas Huth 	}
296ee30cf14SThomas Huth 
297ee30cf14SThomas Huth 	get_sprs(after);
298ee30cf14SThomas Huth 
299ee30cf14SThomas Huth 	puts("Checking SPRs...\n");
300ee30cf14SThomas Huth 	for (i = 0; i < 1024; i++) {
301ee30cf14SThomas Huth 		if (before[i] != 0 || after[i] != 0)
302fd6aada0SRadim Krčmář 			report("SPR %d:\t%#018lx <==> %#018lx",
303ee30cf14SThomas Huth 				before[i] == after[i], i, before[i], after[i]);
304ee30cf14SThomas Huth 	}
305ee30cf14SThomas Huth 
306ee30cf14SThomas Huth 	return report_summary();
307ee30cf14SThomas Huth }
308