1 #ifndef LIBCFLAT_PROCESSOR_H 2 #define LIBCFLAT_PROCESSOR_H 3 4 #include "libcflat.h" 5 #include "msr.h" 6 #include <stdint.h> 7 8 #ifdef __x86_64__ 9 # define R "r" 10 # define W "q" 11 # define S "8" 12 #else 13 # define R "e" 14 # define W "l" 15 # define S "4" 16 #endif 17 18 #define DB_VECTOR 1 19 #define BP_VECTOR 3 20 #define UD_VECTOR 6 21 #define DF_VECTOR 8 22 #define TS_VECTOR 10 23 #define NP_VECTOR 11 24 #define SS_VECTOR 12 25 #define GP_VECTOR 13 26 #define PF_VECTOR 14 27 #define AC_VECTOR 17 28 29 #define X86_CR0_PE 0x00000001 30 #define X86_CR0_MP 0x00000002 31 #define X86_CR0_EM 0x00000004 32 #define X86_CR0_TS 0x00000008 33 #define X86_CR0_WP 0x00010000 34 #define X86_CR0_AM 0x00040000 35 #define X86_CR0_NW 0x20000000 36 #define X86_CR0_CD 0x40000000 37 #define X86_CR0_PG 0x80000000 38 #define X86_CR3_PCID_MASK 0x00000fff 39 #define X86_CR4_TSD 0x00000004 40 #define X86_CR4_DE 0x00000008 41 #define X86_CR4_PSE 0x00000010 42 #define X86_CR4_PAE 0x00000020 43 #define X86_CR4_MCE 0x00000040 44 #define X86_CR4_PGE 0x00000080 45 #define X86_CR4_PCE 0x00000100 46 #define X86_CR4_UMIP 0x00000800 47 #define X86_CR4_LA57 0x00001000 48 #define X86_CR4_VMXE 0x00002000 49 #define X86_CR4_PCIDE 0x00020000 50 #define X86_CR4_OSXSAVE 0x00040000 51 #define X86_CR4_SMEP 0x00100000 52 #define X86_CR4_SMAP 0x00200000 53 #define X86_CR4_PKE 0x00400000 54 #define X86_CR4_CET 0x00800000 55 #define X86_CR4_PKS 0x01000000 56 57 #define X86_EFLAGS_CF 0x00000001 58 #define X86_EFLAGS_FIXED 0x00000002 59 #define X86_EFLAGS_PF 0x00000004 60 #define X86_EFLAGS_AF 0x00000010 61 #define X86_EFLAGS_ZF 0x00000040 62 #define X86_EFLAGS_SF 0x00000080 63 #define X86_EFLAGS_TF 0x00000100 64 #define X86_EFLAGS_IF 0x00000200 65 #define X86_EFLAGS_DF 0x00000400 66 #define X86_EFLAGS_OF 0x00000800 67 #define X86_EFLAGS_IOPL 0x00003000 68 #define X86_EFLAGS_NT 0x00004000 69 #define X86_EFLAGS_VM 0x00020000 70 #define X86_EFLAGS_AC 0x00040000 71 72 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 73 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 74 75 76 /* 77 * CPU features 78 */ 79 80 enum cpuid_output_regs { 81 EAX, 82 EBX, 83 ECX, 84 EDX 85 }; 86 87 struct cpuid { u32 a, b, c, d; }; 88 89 static inline struct cpuid raw_cpuid(u32 function, u32 index) 90 { 91 struct cpuid r; 92 asm volatile ("cpuid" 93 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 94 : "0"(function), "2"(index)); 95 return r; 96 } 97 98 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 99 { 100 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 101 if (level < function) 102 return (struct cpuid) { 0, 0, 0, 0 }; 103 return raw_cpuid(function, index); 104 } 105 106 static inline struct cpuid cpuid(u32 function) 107 { 108 return cpuid_indexed(function, 0); 109 } 110 111 static inline u8 cpuid_maxphyaddr(void) 112 { 113 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 114 return 36; 115 return raw_cpuid(0x80000008, 0).a & 0xff; 116 } 117 118 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 119 (c << 8) | d) 120 121 /* 122 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 123 * CPUID meta-data: 124 * 125 * [63:32] : input value for EAX 126 * [31:16] : input value for ECX 127 * [15:8] : output register 128 * [7:0] : bit position in output register 129 */ 130 131 /* 132 * Intel CPUID features 133 */ 134 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 135 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 136 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 137 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 138 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 139 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 140 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 141 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 142 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 143 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 144 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 145 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 146 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 147 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 148 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 149 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 150 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 151 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 152 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 153 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 154 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 155 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 156 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 157 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 158 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 159 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 160 #define X86_FEATURE_SHSTK (CPUID(0x7, 0, ECX, 7)) 161 #define X86_FEATURE_IBT (CPUID(0x7, 0, EDX, 20)) 162 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 163 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 164 #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) 165 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 166 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 167 168 /* 169 * AMD CPUID features 170 */ 171 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 172 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 173 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 174 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 175 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 176 177 178 static inline bool this_cpu_has(u64 feature) 179 { 180 u32 input_eax = feature >> 32; 181 u32 input_ecx = (feature >> 16) & 0xffff; 182 u32 output_reg = (feature >> 8) & 0xff; 183 u8 bit = feature & 0xff; 184 struct cpuid c; 185 u32 *tmp; 186 187 c = cpuid_indexed(input_eax, input_ecx); 188 tmp = (u32 *)&c; 189 190 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 191 } 192 193 struct far_pointer32 { 194 u32 offset; 195 u16 selector; 196 } __attribute__((packed)); 197 198 struct descriptor_table_ptr { 199 u16 limit; 200 ulong base; 201 } __attribute__((packed)); 202 203 static inline void barrier(void) 204 { 205 asm volatile ("" : : : "memory"); 206 } 207 208 static inline void clac(void) 209 { 210 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 211 } 212 213 static inline void stac(void) 214 { 215 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 216 } 217 218 static inline u16 read_cs(void) 219 { 220 unsigned val; 221 222 asm volatile ("mov %%cs, %0" : "=mr"(val)); 223 return val; 224 } 225 226 static inline u16 read_ds(void) 227 { 228 unsigned val; 229 230 asm volatile ("mov %%ds, %0" : "=mr"(val)); 231 return val; 232 } 233 234 static inline u16 read_es(void) 235 { 236 unsigned val; 237 238 asm volatile ("mov %%es, %0" : "=mr"(val)); 239 return val; 240 } 241 242 static inline u16 read_ss(void) 243 { 244 unsigned val; 245 246 asm volatile ("mov %%ss, %0" : "=mr"(val)); 247 return val; 248 } 249 250 static inline u16 read_fs(void) 251 { 252 unsigned val; 253 254 asm volatile ("mov %%fs, %0" : "=mr"(val)); 255 return val; 256 } 257 258 static inline u16 read_gs(void) 259 { 260 unsigned val; 261 262 asm volatile ("mov %%gs, %0" : "=mr"(val)); 263 return val; 264 } 265 266 static inline unsigned long read_rflags(void) 267 { 268 unsigned long f; 269 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 270 return f; 271 } 272 273 static inline void write_ds(unsigned val) 274 { 275 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 276 } 277 278 static inline void write_es(unsigned val) 279 { 280 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 281 } 282 283 static inline void write_ss(unsigned val) 284 { 285 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 286 } 287 288 static inline void write_fs(unsigned val) 289 { 290 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 291 } 292 293 static inline void write_gs(unsigned val) 294 { 295 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 296 } 297 298 static inline void write_rflags(unsigned long f) 299 { 300 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 301 } 302 303 static inline void set_iopl(int iopl) 304 { 305 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 306 flags |= iopl * (X86_EFLAGS_IOPL / 3); 307 write_rflags(flags); 308 } 309 310 static inline u64 rdmsr(u32 index) 311 { 312 u32 a, d; 313 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 314 return a | ((u64)d << 32); 315 } 316 317 static inline void wrmsr(u32 index, u64 val) 318 { 319 u32 a = val, d = val >> 32; 320 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 321 } 322 323 static inline uint64_t rdpmc(uint32_t index) 324 { 325 uint32_t a, d; 326 asm volatile ("rdpmc" : "=a"(a), "=d"(d) : "c"(index)); 327 return a | ((uint64_t)d << 32); 328 } 329 330 static inline void write_cr0(ulong val) 331 { 332 asm volatile ("mov %0, %%cr0" : : "r"(val) : "memory"); 333 } 334 335 static inline ulong read_cr0(void) 336 { 337 ulong val; 338 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 339 return val; 340 } 341 342 static inline void write_cr2(ulong val) 343 { 344 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 345 } 346 347 static inline ulong read_cr2(void) 348 { 349 ulong val; 350 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 351 return val; 352 } 353 354 static inline void write_cr3(ulong val) 355 { 356 asm volatile ("mov %0, %%cr3" : : "r"(val) : "memory"); 357 } 358 359 static inline ulong read_cr3(void) 360 { 361 ulong val; 362 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 363 return val; 364 } 365 366 static inline void update_cr3(void *cr3) 367 { 368 write_cr3((ulong)cr3); 369 } 370 371 static inline void write_cr4(ulong val) 372 { 373 asm volatile ("mov %0, %%cr4" : : "r"(val) : "memory"); 374 } 375 376 static inline ulong read_cr4(void) 377 { 378 ulong val; 379 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 380 return val; 381 } 382 383 static inline void write_cr8(ulong val) 384 { 385 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 386 } 387 388 static inline ulong read_cr8(void) 389 { 390 ulong val; 391 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 392 return val; 393 } 394 395 static inline void lgdt(const struct descriptor_table_ptr *ptr) 396 { 397 asm volatile ("lgdt %0" : : "m"(*ptr)); 398 } 399 400 static inline void sgdt(struct descriptor_table_ptr *ptr) 401 { 402 asm volatile ("sgdt %0" : "=m"(*ptr)); 403 } 404 405 static inline void lidt(const struct descriptor_table_ptr *ptr) 406 { 407 asm volatile ("lidt %0" : : "m"(*ptr)); 408 } 409 410 static inline void sidt(struct descriptor_table_ptr *ptr) 411 { 412 asm volatile ("sidt %0" : "=m"(*ptr)); 413 } 414 415 static inline void lldt(unsigned val) 416 { 417 asm volatile ("lldt %0" : : "rm"(val)); 418 } 419 420 static inline u16 sldt(void) 421 { 422 u16 val; 423 asm volatile ("sldt %0" : "=rm"(val)); 424 return val; 425 } 426 427 static inline void ltr(u16 val) 428 { 429 asm volatile ("ltr %0" : : "rm"(val)); 430 } 431 432 static inline u16 str(void) 433 { 434 u16 val; 435 asm volatile ("str %0" : "=rm"(val)); 436 return val; 437 } 438 439 static inline void write_dr6(ulong val) 440 { 441 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 442 } 443 444 static inline ulong read_dr6(void) 445 { 446 ulong val; 447 asm volatile ("mov %%dr6, %0" : "=r"(val)); 448 return val; 449 } 450 451 static inline void write_dr7(ulong val) 452 { 453 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 454 } 455 456 static inline ulong read_dr7(void) 457 { 458 ulong val; 459 asm volatile ("mov %%dr7, %0" : "=r"(val)); 460 return val; 461 } 462 463 static inline void pause(void) 464 { 465 asm volatile ("pause"); 466 } 467 468 static inline void cli(void) 469 { 470 asm volatile ("cli"); 471 } 472 473 static inline void sti(void) 474 { 475 asm volatile ("sti"); 476 } 477 478 static inline unsigned long long rdtsc(void) 479 { 480 long long r; 481 482 #ifdef __x86_64__ 483 unsigned a, d; 484 485 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 486 r = a | ((long long)d << 32); 487 #else 488 asm volatile ("rdtsc" : "=A"(r)); 489 #endif 490 return r; 491 } 492 493 /* 494 * Per the advice in the SDM, volume 2, the sequence "mfence; lfence" 495 * executed immediately before rdtsc ensures that rdtsc will be 496 * executed only after all previous instructions have executed and all 497 * previous loads and stores are globally visible. In addition, the 498 * lfence immediately after rdtsc ensures that rdtsc will be executed 499 * prior to the execution of any subsequent instruction. 500 */ 501 static inline unsigned long long fenced_rdtsc(void) 502 { 503 unsigned long long tsc; 504 505 #ifdef __x86_64__ 506 unsigned int eax, edx; 507 508 asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 509 tsc = eax | ((unsigned long long)edx << 32); 510 #else 511 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); 512 #endif 513 return tsc; 514 } 515 516 static inline unsigned long long rdtscp(u32 *aux) 517 { 518 long long r; 519 520 #ifdef __x86_64__ 521 unsigned a, d; 522 523 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 524 r = a | ((long long)d << 32); 525 #else 526 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 527 #endif 528 return r; 529 } 530 531 static inline void wrtsc(u64 tsc) 532 { 533 unsigned a = tsc, d = tsc >> 32; 534 535 asm volatile("wrmsr" : : "a"(a), "d"(d), "c"(0x10)); 536 } 537 538 static inline void irq_disable(void) 539 { 540 asm volatile("cli"); 541 } 542 543 /* Note that irq_enable() does not ensure an interrupt shadow due 544 * to the vagaries of compiler optimizations. If you need the 545 * shadow, use a single asm with "sti" and the instruction after it. 546 */ 547 static inline void irq_enable(void) 548 { 549 asm volatile("sti"); 550 } 551 552 static inline void invlpg(volatile void *va) 553 { 554 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 555 } 556 557 static inline void safe_halt(void) 558 { 559 asm volatile("sti; hlt"); 560 } 561 562 static inline u32 read_pkru(void) 563 { 564 unsigned int eax, edx; 565 unsigned int ecx = 0; 566 unsigned int pkru; 567 568 asm volatile(".byte 0x0f,0x01,0xee\n\t" 569 : "=a" (eax), "=d" (edx) 570 : "c" (ecx)); 571 pkru = eax; 572 return pkru; 573 } 574 575 static inline void write_pkru(u32 pkru) 576 { 577 unsigned int eax = pkru; 578 unsigned int ecx = 0; 579 unsigned int edx = 0; 580 581 asm volatile(".byte 0x0f,0x01,0xef\n\t" 582 : : "a" (eax), "c" (ecx), "d" (edx)); 583 } 584 585 static inline bool is_canonical(u64 addr) 586 { 587 return (s64)(addr << 16) >> 16 == addr; 588 } 589 590 static inline void clear_bit(int bit, u8 *addr) 591 { 592 __asm__ __volatile__("btr %1, %0" 593 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 594 } 595 596 static inline void set_bit(int bit, u8 *addr) 597 { 598 __asm__ __volatile__("bts %1, %0" 599 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 600 } 601 602 static inline void flush_tlb(void) 603 { 604 ulong cr4; 605 606 cr4 = read_cr4(); 607 write_cr4(cr4 ^ X86_CR4_PGE); 608 write_cr4(cr4); 609 } 610 611 static inline int has_spec_ctrl(void) 612 { 613 return !!(this_cpu_has(X86_FEATURE_SPEC_CTRL)); 614 } 615 616 static inline int cpu_has_efer_nx(void) 617 { 618 return !!(this_cpu_has(X86_FEATURE_NX)); 619 } 620 621 static inline bool cpuid_osxsave(void) 622 { 623 return cpuid(1).c & (1 << (X86_FEATURE_OSXSAVE % 32)); 624 } 625 626 #endif 627