1 #ifndef _X86_PROCESSOR_H_ 2 #define _X86_PROCESSOR_H_ 3 4 #include "libcflat.h" 5 #include "desc.h" 6 #include "msr.h" 7 #include <bitops.h> 8 #include <stdint.h> 9 10 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 11 12 #ifdef __x86_64__ 13 # define R "r" 14 # define W "q" 15 # define S "8" 16 #else 17 # define R "e" 18 # define W "l" 19 # define S "4" 20 #endif 21 22 #define DB_VECTOR 1 23 #define BP_VECTOR 3 24 #define UD_VECTOR 6 25 #define DF_VECTOR 8 26 #define TS_VECTOR 10 27 #define NP_VECTOR 11 28 #define SS_VECTOR 12 29 #define GP_VECTOR 13 30 #define PF_VECTOR 14 31 #define AC_VECTOR 17 32 #define CP_VECTOR 21 33 34 #define X86_CR0_PE_BIT (0) 35 #define X86_CR0_PE BIT(X86_CR0_PE_BIT) 36 #define X86_CR0_MP_BIT (1) 37 #define X86_CR0_MP BIT(X86_CR0_MP_BIT) 38 #define X86_CR0_EM_BIT (2) 39 #define X86_CR0_EM BIT(X86_CR0_EM_BIT) 40 #define X86_CR0_TS_BIT (3) 41 #define X86_CR0_TS BIT(X86_CR0_TS_BIT) 42 #define X86_CR0_ET_BIT (4) 43 #define X86_CR0_ET BIT(X86_CR0_ET_BIT) 44 #define X86_CR0_NE_BIT (5) 45 #define X86_CR0_NE BIT(X86_CR0_NE_BIT) 46 #define X86_CR0_WP_BIT (16) 47 #define X86_CR0_WP BIT(X86_CR0_WP_BIT) 48 #define X86_CR0_AM_BIT (18) 49 #define X86_CR0_AM BIT(X86_CR0_AM_BIT) 50 #define X86_CR0_NW_BIT (29) 51 #define X86_CR0_NW BIT(X86_CR0_NW_BIT) 52 #define X86_CR0_CD_BIT (30) 53 #define X86_CR0_CD BIT(X86_CR0_CD_BIT) 54 #define X86_CR0_PG_BIT (31) 55 #define X86_CR0_PG BIT(X86_CR0_PG_BIT) 56 57 #define X86_CR3_PCID_MASK GENMASK(11, 0) 58 59 #define X86_CR4_VME_BIT (0) 60 #define X86_CR4_VME BIT(X86_CR4_VME_BIT) 61 #define X86_CR4_PVI_BIT (1) 62 #define X86_CR4_PVI BIT(X86_CR4_PVI_BIT) 63 #define X86_CR4_TSD_BIT (2) 64 #define X86_CR4_TSD BIT(X86_CR4_TSD_BIT) 65 #define X86_CR4_DE_BIT (3) 66 #define X86_CR4_DE BIT(X86_CR4_DE_BIT) 67 #define X86_CR4_PSE_BIT (4) 68 #define X86_CR4_PSE BIT(X86_CR4_PSE_BIT) 69 #define X86_CR4_PAE_BIT (5) 70 #define X86_CR4_PAE BIT(X86_CR4_PAE_BIT) 71 #define X86_CR4_MCE_BIT (6) 72 #define X86_CR4_MCE BIT(X86_CR4_MCE_BIT) 73 #define X86_CR4_PGE_BIT (7) 74 #define X86_CR4_PGE BIT(X86_CR4_PGE_BIT) 75 #define X86_CR4_PCE_BIT (8) 76 #define X86_CR4_PCE BIT(X86_CR4_PCE_BIT) 77 #define X86_CR4_OSFXSR_BIT (9) 78 #define X86_CR4_OSFXSR BIT(X86_CR4_OSFXSR_BIT) 79 #define X86_CR4_OSXMMEXCPT_BIT (10) 80 #define X86_CR4_OSXMMEXCPT BIT(X86_CR4_OSXMMEXCPT_BIT) 81 #define X86_CR4_UMIP_BIT (11) 82 #define X86_CR4_UMIP BIT(X86_CR4_UMIP_BIT) 83 #define X86_CR4_LA57_BIT (12) 84 #define X86_CR4_LA57 BIT(X86_CR4_LA57_BIT) 85 #define X86_CR4_VMXE_BIT (13) 86 #define X86_CR4_VMXE BIT(X86_CR4_VMXE_BIT) 87 #define X86_CR4_SMXE_BIT (14) 88 #define X86_CR4_SMXE BIT(X86_CR4_SMXE_BIT) 89 /* UNUSED (15) */ 90 #define X86_CR4_FSGSBASE_BIT (16) 91 #define X86_CR4_FSGSBASE BIT(X86_CR4_FSGSBASE_BIT) 92 #define X86_CR4_PCIDE_BIT (17) 93 #define X86_CR4_PCIDE BIT(X86_CR4_PCIDE_BIT) 94 #define X86_CR4_OSXSAVE_BIT (18) 95 #define X86_CR4_OSXSAVE BIT(X86_CR4_OSXSAVE_BIT) 96 #define X86_CR4_KL_BIT (19) 97 #define X86_CR4_KL BIT(X86_CR4_KL_BIT) 98 #define X86_CR4_SMEP_BIT (20) 99 #define X86_CR4_SMEP BIT(X86_CR4_SMEP_BIT) 100 #define X86_CR4_SMAP_BIT (21) 101 #define X86_CR4_SMAP BIT(X86_CR4_SMAP_BIT) 102 #define X86_CR4_PKE_BIT (22) 103 #define X86_CR4_PKE BIT(X86_CR4_PKE_BIT) 104 #define X86_CR4_CET_BIT (23) 105 #define X86_CR4_CET BIT(X86_CR4_CET_BIT) 106 #define X86_CR4_PKS_BIT (24) 107 #define X86_CR4_PKS BIT(X86_CR4_PKS_BIT) 108 109 #define X86_EFLAGS_CF_BIT (0) 110 #define X86_EFLAGS_CF BIT(X86_EFLAGS_CF_BIT) 111 #define X86_EFLAGS_FIXED_BIT (1) 112 #define X86_EFLAGS_FIXED BIT(X86_EFLAGS_FIXED_BIT) 113 #define X86_EFLAGS_PF_BIT (2) 114 #define X86_EFLAGS_PF BIT(X86_EFLAGS_PF_BIT) 115 /* RESERVED 0 (3) */ 116 #define X86_EFLAGS_AF_BIT (4) 117 #define X86_EFLAGS_AF BIT(X86_EFLAGS_AF_BIT) 118 /* RESERVED 0 (5) */ 119 #define X86_EFLAGS_ZF_BIT (6) 120 #define X86_EFLAGS_ZF BIT(X86_EFLAGS_ZF_BIT) 121 #define X86_EFLAGS_SF_BIT (7) 122 #define X86_EFLAGS_SF BIT(X86_EFLAGS_SF_BIT) 123 #define X86_EFLAGS_TF_BIT (8) 124 #define X86_EFLAGS_TF BIT(X86_EFLAGS_TF_BIT) 125 #define X86_EFLAGS_IF_BIT (9) 126 #define X86_EFLAGS_IF BIT(X86_EFLAGS_IF_BIT) 127 #define X86_EFLAGS_DF_BIT (10) 128 #define X86_EFLAGS_DF BIT(X86_EFLAGS_DF_BIT) 129 #define X86_EFLAGS_OF_BIT (11) 130 #define X86_EFLAGS_OF BIT(X86_EFLAGS_OF_BIT) 131 #define X86_EFLAGS_IOPL GENMASK(13, 12) 132 #define X86_EFLAGS_NT_BIT (14) 133 #define X86_EFLAGS_NT BIT(X86_EFLAGS_NT_BIT) 134 /* RESERVED 0 (15) */ 135 #define X86_EFLAGS_RF_BIT (16) 136 #define X86_EFLAGS_RF BIT(X86_EFLAGS_RF_BIT) 137 #define X86_EFLAGS_VM_BIT (17) 138 #define X86_EFLAGS_VM BIT(X86_EFLAGS_VM_BIT) 139 #define X86_EFLAGS_AC_BIT (18) 140 #define X86_EFLAGS_AC BIT(X86_EFLAGS_AC_BIT) 141 #define X86_EFLAGS_VIF_BIT (19) 142 #define X86_EFLAGS_VIF BIT(X86_EFLAGS_VIF_BIT) 143 #define X86_EFLAGS_VIP_BIT (20) 144 #define X86_EFLAGS_VIP BIT(X86_EFLAGS_VIP_BIT) 145 #define X86_EFLAGS_ID_BIT (21) 146 #define X86_EFLAGS_ID BIT(X86_EFLAGS_ID_BIT) 147 148 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 149 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 150 151 152 /* 153 * CPU features 154 */ 155 156 enum cpuid_output_regs { 157 EAX, 158 EBX, 159 ECX, 160 EDX 161 }; 162 163 struct cpuid { u32 a, b, c, d; }; 164 165 static inline struct cpuid raw_cpuid(u32 function, u32 index) 166 { 167 struct cpuid r; 168 asm volatile ("cpuid" 169 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 170 : "0"(function), "2"(index)); 171 return r; 172 } 173 174 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 175 { 176 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 177 if (level < function) 178 return (struct cpuid) { 0, 0, 0, 0 }; 179 return raw_cpuid(function, index); 180 } 181 182 static inline struct cpuid cpuid(u32 function) 183 { 184 return cpuid_indexed(function, 0); 185 } 186 187 static inline u8 cpuid_maxphyaddr(void) 188 { 189 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 190 return 36; 191 return raw_cpuid(0x80000008, 0).a & 0xff; 192 } 193 194 static inline bool is_intel(void) 195 { 196 struct cpuid c = cpuid(0); 197 u32 name[4] = {c.b, c.d, c.c }; 198 199 return strcmp((char *)name, "GenuineIntel") == 0; 200 } 201 202 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 203 (c << 8) | d) 204 205 /* 206 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 207 * CPUID meta-data: 208 * 209 * [63:32] : input value for EAX 210 * [31:16] : input value for ECX 211 * [15:8] : output register 212 * [7:0] : bit position in output register 213 */ 214 215 /* 216 * Basic Leafs, a.k.a. Intel defined 217 */ 218 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 219 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 220 #define X86_FEATURE_PDCM (CPUID(0x1, 0, ECX, 15)) 221 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 222 #define X86_FEATURE_X2APIC (CPUID(0x1, 0, ECX, 21)) 223 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 224 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 225 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 226 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 227 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 228 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 229 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 230 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 231 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 232 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 233 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 234 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 235 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 236 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 237 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 238 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 239 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 240 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 241 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 242 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 243 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 244 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 245 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 246 #define X86_FEATURE_SHSTK (CPUID(0x7, 0, ECX, 7)) 247 #define X86_FEATURE_IBT (CPUID(0x7, 0, EDX, 20)) 248 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 249 #define X86_FEATURE_FLUSH_L1D (CPUID(0x7, 0, EDX, 28)) 250 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 251 #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) 252 253 /* 254 * Extended Leafs, a.k.a. AMD defined 255 */ 256 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 257 #define X86_FEATURE_PERFCTR_CORE (CPUID(0x80000001, 0, ECX, 23)) 258 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 259 #define X86_FEATURE_GBPAGES (CPUID(0x80000001, 0, EDX, 26)) 260 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 261 #define X86_FEATURE_LM (CPUID(0x80000001, 0, EDX, 29)) 262 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 263 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 264 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 265 #define X86_FEATURE_LBRV (CPUID(0x8000000A, 0, EDX, 1)) 266 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 267 #define X86_FEATURE_TSCRATEMSR (CPUID(0x8000000A, 0, EDX, 4)) 268 #define X86_FEATURE_PAUSEFILTER (CPUID(0x8000000A, 0, EDX, 10)) 269 #define X86_FEATURE_PFTHRESHOLD (CPUID(0x8000000A, 0, EDX, 12)) 270 #define X86_FEATURE_VGIF (CPUID(0x8000000A, 0, EDX, 16)) 271 #define X86_FEATURE_AMD_PMU_V2 (CPUID(0x80000022, 0, EAX, 0)) 272 273 static inline bool this_cpu_has(u64 feature) 274 { 275 u32 input_eax = feature >> 32; 276 u32 input_ecx = (feature >> 16) & 0xffff; 277 u32 output_reg = (feature >> 8) & 0xff; 278 u8 bit = feature & 0xff; 279 struct cpuid c; 280 u32 *tmp; 281 282 c = cpuid_indexed(input_eax, input_ecx); 283 tmp = (u32 *)&c; 284 285 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 286 } 287 288 struct far_pointer32 { 289 u32 offset; 290 u16 selector; 291 } __attribute__((packed)); 292 293 struct descriptor_table_ptr { 294 u16 limit; 295 ulong base; 296 } __attribute__((packed)); 297 298 static inline void clac(void) 299 { 300 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 301 } 302 303 static inline void stac(void) 304 { 305 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 306 } 307 308 static inline u16 read_cs(void) 309 { 310 unsigned val; 311 312 asm volatile ("mov %%cs, %0" : "=mr"(val)); 313 return val; 314 } 315 316 static inline u16 read_ds(void) 317 { 318 unsigned val; 319 320 asm volatile ("mov %%ds, %0" : "=mr"(val)); 321 return val; 322 } 323 324 static inline u16 read_es(void) 325 { 326 unsigned val; 327 328 asm volatile ("mov %%es, %0" : "=mr"(val)); 329 return val; 330 } 331 332 static inline u16 read_ss(void) 333 { 334 unsigned val; 335 336 asm volatile ("mov %%ss, %0" : "=mr"(val)); 337 return val; 338 } 339 340 static inline u16 read_fs(void) 341 { 342 unsigned val; 343 344 asm volatile ("mov %%fs, %0" : "=mr"(val)); 345 return val; 346 } 347 348 static inline u16 read_gs(void) 349 { 350 unsigned val; 351 352 asm volatile ("mov %%gs, %0" : "=mr"(val)); 353 return val; 354 } 355 356 static inline unsigned long read_rflags(void) 357 { 358 unsigned long f; 359 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 360 return f; 361 } 362 363 static inline void write_ds(unsigned val) 364 { 365 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 366 } 367 368 static inline void write_es(unsigned val) 369 { 370 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 371 } 372 373 static inline void write_ss(unsigned val) 374 { 375 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 376 } 377 378 static inline void write_fs(unsigned val) 379 { 380 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 381 } 382 383 static inline void write_gs(unsigned val) 384 { 385 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 386 } 387 388 static inline void write_rflags(unsigned long f) 389 { 390 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 391 } 392 393 static inline void set_iopl(int iopl) 394 { 395 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 396 flags |= iopl * (X86_EFLAGS_IOPL / 3); 397 write_rflags(flags); 398 } 399 400 /* 401 * Don't use the safe variants for rdmsr() or wrmsr(). The exception fixup 402 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests 403 * temporarily modify MSR_GS_BASE and will explode when trying to determine 404 * whether or not RDMSR/WRMSR faulted. 405 */ 406 static inline u64 rdmsr(u32 index) 407 { 408 u32 a, d; 409 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 410 return a | ((u64)d << 32); 411 } 412 413 static inline void wrmsr(u32 index, u64 val) 414 { 415 u32 a = val, d = val >> 32; 416 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 417 } 418 419 static inline int rdmsr_safe(u32 index, uint64_t *val) 420 { 421 uint32_t a, d; 422 423 asm volatile (ASM_TRY("1f") 424 "rdmsr\n\t" 425 "1:" 426 : "=a"(a), "=d"(d) 427 : "c"(index) : "memory"); 428 429 *val = (uint64_t)a | ((uint64_t)d << 32); 430 return exception_vector(); 431 } 432 433 static inline int wrmsr_safe(u32 index, u64 val) 434 { 435 u32 a = val, d = val >> 32; 436 437 asm volatile (ASM_TRY("1f") 438 "wrmsr\n\t" 439 "1:" 440 : : "a"(a), "d"(d), "c"(index) : "memory"); 441 return exception_vector(); 442 } 443 444 static inline int rdpmc_safe(u32 index, uint64_t *val) 445 { 446 uint32_t a, d; 447 448 asm volatile (ASM_TRY("1f") 449 "rdpmc\n\t" 450 "1:" 451 : "=a"(a), "=d"(d) : "c"(index) : "memory"); 452 *val = (uint64_t)a | ((uint64_t)d << 32); 453 return exception_vector(); 454 } 455 456 static inline uint64_t rdpmc(uint32_t index) 457 { 458 uint64_t val; 459 int vector = rdpmc_safe(index, &val); 460 461 assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")", 462 exception_mnemonic(vector), index); 463 return val; 464 } 465 466 static inline int write_cr0_safe(ulong val) 467 { 468 asm volatile(ASM_TRY("1f") 469 "mov %0,%%cr0\n\t" 470 "1:": : "r" (val)); 471 return exception_vector(); 472 } 473 474 static inline void write_cr0(ulong val) 475 { 476 int vector = write_cr0_safe(val); 477 478 assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx", 479 vector, val); 480 } 481 482 static inline ulong read_cr0(void) 483 { 484 ulong val; 485 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 486 return val; 487 } 488 489 static inline void write_cr2(ulong val) 490 { 491 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 492 } 493 494 static inline ulong read_cr2(void) 495 { 496 ulong val; 497 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 498 return val; 499 } 500 501 static inline int write_cr3_safe(ulong val) 502 { 503 asm volatile(ASM_TRY("1f") 504 "mov %0,%%cr3\n\t" 505 "1:": : "r" (val)); 506 return exception_vector(); 507 } 508 509 static inline void write_cr3(ulong val) 510 { 511 int vector = write_cr3_safe(val); 512 513 assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx", 514 vector, val); 515 } 516 517 static inline ulong read_cr3(void) 518 { 519 ulong val; 520 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 521 return val; 522 } 523 524 static inline void update_cr3(void *cr3) 525 { 526 write_cr3((ulong)cr3); 527 } 528 529 static inline int write_cr4_safe(ulong val) 530 { 531 asm volatile(ASM_TRY("1f") 532 "mov %0,%%cr4\n\t" 533 "1:": : "r" (val)); 534 return exception_vector(); 535 } 536 537 static inline void write_cr4(ulong val) 538 { 539 int vector = write_cr4_safe(val); 540 541 assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx", 542 vector, val); 543 } 544 545 static inline ulong read_cr4(void) 546 { 547 ulong val; 548 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 549 return val; 550 } 551 552 static inline void write_cr8(ulong val) 553 { 554 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 555 } 556 557 static inline ulong read_cr8(void) 558 { 559 ulong val; 560 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 561 return val; 562 } 563 564 static inline void lgdt(const struct descriptor_table_ptr *ptr) 565 { 566 asm volatile ("lgdt %0" : : "m"(*ptr)); 567 } 568 569 static inline void sgdt(struct descriptor_table_ptr *ptr) 570 { 571 asm volatile ("sgdt %0" : "=m"(*ptr)); 572 } 573 574 static inline void lidt(const struct descriptor_table_ptr *ptr) 575 { 576 asm volatile ("lidt %0" : : "m"(*ptr)); 577 } 578 579 static inline void sidt(struct descriptor_table_ptr *ptr) 580 { 581 asm volatile ("sidt %0" : "=m"(*ptr)); 582 } 583 584 static inline void lldt(u16 val) 585 { 586 asm volatile ("lldt %0" : : "rm"(val)); 587 } 588 589 static inline u16 sldt(void) 590 { 591 u16 val; 592 asm volatile ("sldt %0" : "=rm"(val)); 593 return val; 594 } 595 596 static inline void ltr(u16 val) 597 { 598 asm volatile ("ltr %0" : : "rm"(val)); 599 } 600 601 static inline u16 str(void) 602 { 603 u16 val; 604 asm volatile ("str %0" : "=rm"(val)); 605 return val; 606 } 607 608 static inline void write_dr0(void *val) 609 { 610 asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory"); 611 } 612 613 static inline void write_dr1(void *val) 614 { 615 asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory"); 616 } 617 618 static inline void write_dr2(void *val) 619 { 620 asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory"); 621 } 622 623 static inline void write_dr3(void *val) 624 { 625 asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory"); 626 } 627 628 static inline void write_dr6(ulong val) 629 { 630 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 631 } 632 633 static inline ulong read_dr6(void) 634 { 635 ulong val; 636 asm volatile ("mov %%dr6, %0" : "=r"(val)); 637 return val; 638 } 639 640 static inline void write_dr7(ulong val) 641 { 642 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 643 } 644 645 static inline ulong read_dr7(void) 646 { 647 ulong val; 648 asm volatile ("mov %%dr7, %0" : "=r"(val)); 649 return val; 650 } 651 652 static inline void pause(void) 653 { 654 asm volatile ("pause"); 655 } 656 657 static inline void cli(void) 658 { 659 asm volatile ("cli"); 660 } 661 662 static inline void sti(void) 663 { 664 asm volatile ("sti"); 665 } 666 667 static inline unsigned long long rdrand(void) 668 { 669 long long r; 670 671 asm volatile("rdrand %0\n\t" 672 "jc 1f\n\t" 673 "mov $0, %0\n\t" 674 "1:\n\t" : "=r" (r)); 675 return r; 676 } 677 678 static inline unsigned long long rdtsc(void) 679 { 680 long long r; 681 682 #ifdef __x86_64__ 683 unsigned a, d; 684 685 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 686 r = a | ((long long)d << 32); 687 #else 688 asm volatile ("rdtsc" : "=A"(r)); 689 #endif 690 return r; 691 } 692 693 /* 694 * Per the advice in the SDM, volume 2, the sequence "mfence; lfence" 695 * executed immediately before rdtsc ensures that rdtsc will be 696 * executed only after all previous instructions have executed and all 697 * previous loads and stores are globally visible. In addition, the 698 * lfence immediately after rdtsc ensures that rdtsc will be executed 699 * prior to the execution of any subsequent instruction. 700 */ 701 static inline unsigned long long fenced_rdtsc(void) 702 { 703 unsigned long long tsc; 704 705 #ifdef __x86_64__ 706 unsigned int eax, edx; 707 708 asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 709 tsc = eax | ((unsigned long long)edx << 32); 710 #else 711 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); 712 #endif 713 return tsc; 714 } 715 716 static inline unsigned long long rdtscp(u32 *aux) 717 { 718 long long r; 719 720 #ifdef __x86_64__ 721 unsigned a, d; 722 723 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 724 r = a | ((long long)d << 32); 725 #else 726 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 727 #endif 728 return r; 729 } 730 731 static inline void wrtsc(u64 tsc) 732 { 733 wrmsr(MSR_IA32_TSC, tsc); 734 } 735 736 static inline void irq_disable(void) 737 { 738 asm volatile("cli"); 739 } 740 741 /* Note that irq_enable() does not ensure an interrupt shadow due 742 * to the vagaries of compiler optimizations. If you need the 743 * shadow, use a single asm with "sti" and the instruction after it. 744 */ 745 static inline void irq_enable(void) 746 { 747 asm volatile("sti"); 748 } 749 750 static inline void invlpg(volatile void *va) 751 { 752 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 753 } 754 755 static inline void safe_halt(void) 756 { 757 asm volatile("sti; hlt"); 758 } 759 760 static inline u32 read_pkru(void) 761 { 762 unsigned int eax, edx; 763 unsigned int ecx = 0; 764 unsigned int pkru; 765 766 asm volatile(".byte 0x0f,0x01,0xee\n\t" 767 : "=a" (eax), "=d" (edx) 768 : "c" (ecx)); 769 pkru = eax; 770 return pkru; 771 } 772 773 static inline void write_pkru(u32 pkru) 774 { 775 unsigned int eax = pkru; 776 unsigned int ecx = 0; 777 unsigned int edx = 0; 778 779 asm volatile(".byte 0x0f,0x01,0xef\n\t" 780 : : "a" (eax), "c" (ecx), "d" (edx)); 781 } 782 783 static inline bool is_canonical(u64 addr) 784 { 785 int va_width = (raw_cpuid(0x80000008, 0).a & 0xff00) >> 8; 786 int shift_amt = 64 - va_width; 787 788 return (s64)(addr << shift_amt) >> shift_amt == addr; 789 } 790 791 static inline void clear_bit(int bit, u8 *addr) 792 { 793 __asm__ __volatile__("btr %1, %0" 794 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 795 } 796 797 static inline void set_bit(int bit, u8 *addr) 798 { 799 __asm__ __volatile__("bts %1, %0" 800 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 801 } 802 803 static inline void flush_tlb(void) 804 { 805 ulong cr4; 806 807 cr4 = read_cr4(); 808 write_cr4(cr4 ^ X86_CR4_PGE); 809 write_cr4(cr4); 810 } 811 812 static inline void generate_non_canonical_gp(void) 813 { 814 *(volatile u64 *)NONCANONICAL = 0; 815 } 816 817 static inline void generate_ud(void) 818 { 819 asm volatile ("ud2"); 820 } 821 822 static inline void generate_de(void) 823 { 824 asm volatile ( 825 "xor %%eax, %%eax\n\t" 826 "xor %%ebx, %%ebx\n\t" 827 "xor %%edx, %%edx\n\t" 828 "idiv %%ebx\n\t" 829 ::: "eax", "ebx", "edx"); 830 } 831 832 static inline void generate_bp(void) 833 { 834 asm volatile ("int3"); 835 } 836 837 static inline void generate_single_step_db(void) 838 { 839 write_rflags(read_rflags() | X86_EFLAGS_TF); 840 asm volatile("nop"); 841 } 842 843 static inline uint64_t generate_usermode_ac(void) 844 { 845 /* 846 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 847 * Disclaimer: It is assumed that the stack pointer is aligned 848 * on a 16-byte boundary as x86_64 stacks should be. 849 */ 850 asm volatile("movq $0, -0x4(%rsp)"); 851 852 return 0; 853 } 854 855 /* 856 * Switch from 64-bit to 32-bit mode and generate #OF via INTO. Note, if RIP 857 * or RSP holds a 64-bit value, this helper will NOT generate #OF. 858 */ 859 static inline void generate_of(void) 860 { 861 struct far_pointer32 fp = { 862 .offset = (uintptr_t)&&into, 863 .selector = KERNEL_CS32, 864 }; 865 uintptr_t rsp; 866 867 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 868 869 if (fp.offset != (uintptr_t)&&into) { 870 printf("Code address too high.\n"); 871 return; 872 } 873 if ((u32)rsp != rsp) { 874 printf("Stack address too high.\n"); 875 return; 876 } 877 878 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 879 return; 880 into: 881 asm volatile (".code32;" 882 "movl $0x7fffffff, %eax;" 883 "addl %eax, %eax;" 884 "into;" 885 "lret;" 886 ".code64"); 887 __builtin_unreachable(); 888 } 889 890 static inline void fnop(void) 891 { 892 asm volatile("fnop"); 893 } 894 895 /* If CR0.TS is set in L2, #NM is generated. */ 896 static inline void generate_cr0_ts_nm(void) 897 { 898 write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS); 899 fnop(); 900 } 901 902 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */ 903 static inline void generate_cr0_em_nm(void) 904 { 905 write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM); 906 fnop(); 907 } 908 909 #endif 910