xref: /kvm-unit-tests/lib/x86/processor.h (revision b643ae6207dafcad8ad99f0d8a2ca8245c2ce993)
1 #ifndef _X86_PROCESSOR_H_
2 #define _X86_PROCESSOR_H_
3 
4 #include "libcflat.h"
5 #include "desc.h"
6 #include "msr.h"
7 #include <bitops.h>
8 #include <stdint.h>
9 #include <util.h>
10 
11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull
12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull
13 #define NONCANONICAL	 0xaaaaaaaaaaaaaaaaull
14 
15 #define LAM57_MASK	GENMASK_ULL(62, 57)
16 #define LAM48_MASK	GENMASK_ULL(62, 48)
17 
18 /*
19  * Get a linear address by combining @addr with a non-canonical pattern in the
20  * @mask bits.
21  */
22 static inline u64 get_non_canonical(u64 addr, u64 mask)
23 {
24 	return (addr & ~mask) | (NONCANONICAL & mask);
25 }
26 
27 #ifdef __x86_64__
28 #  define R "r"
29 #  define W "q"
30 #  define S "8"
31 #else
32 #  define R "e"
33 #  define W "l"
34 #  define S "4"
35 #endif
36 
37 #define DE_VECTOR 0
38 #define DB_VECTOR 1
39 #define NMI_VECTOR 2
40 #define BP_VECTOR 3
41 #define OF_VECTOR 4
42 #define BR_VECTOR 5
43 #define UD_VECTOR 6
44 #define NM_VECTOR 7
45 #define DF_VECTOR 8
46 #define TS_VECTOR 10
47 #define NP_VECTOR 11
48 #define SS_VECTOR 12
49 #define GP_VECTOR 13
50 #define PF_VECTOR 14
51 #define MF_VECTOR 16
52 #define AC_VECTOR 17
53 #define MC_VECTOR 18
54 #define XM_VECTOR 19
55 #define XF_VECTOR XM_VECTOR /* AMD */
56 #define VE_VECTOR 20 /* Intel only */
57 #define CP_VECTOR 21
58 #define HV_VECTOR 28 /* AMD only */
59 #define VC_VECTOR 29 /* AMD only */
60 #define SX_VECTOR 30 /* AMD only */
61 
62 #define X86_CR0_PE_BIT		(0)
63 #define X86_CR0_PE		BIT(X86_CR0_PE_BIT)
64 #define X86_CR0_MP_BIT		(1)
65 #define X86_CR0_MP		BIT(X86_CR0_MP_BIT)
66 #define X86_CR0_EM_BIT		(2)
67 #define X86_CR0_EM		BIT(X86_CR0_EM_BIT)
68 #define X86_CR0_TS_BIT		(3)
69 #define X86_CR0_TS		BIT(X86_CR0_TS_BIT)
70 #define X86_CR0_ET_BIT		(4)
71 #define X86_CR0_ET		BIT(X86_CR0_ET_BIT)
72 #define X86_CR0_NE_BIT		(5)
73 #define X86_CR0_NE		BIT(X86_CR0_NE_BIT)
74 #define X86_CR0_WP_BIT		(16)
75 #define X86_CR0_WP		BIT(X86_CR0_WP_BIT)
76 #define X86_CR0_AM_BIT		(18)
77 #define X86_CR0_AM		BIT(X86_CR0_AM_BIT)
78 #define X86_CR0_NW_BIT		(29)
79 #define X86_CR0_NW		BIT(X86_CR0_NW_BIT)
80 #define X86_CR0_CD_BIT		(30)
81 #define X86_CR0_CD		BIT(X86_CR0_CD_BIT)
82 #define X86_CR0_PG_BIT		(31)
83 #define X86_CR0_PG		BIT(X86_CR0_PG_BIT)
84 
85 #define X86_CR3_PCID_MASK	GENMASK(11, 0)
86 #define X86_CR3_LAM_U57_BIT	(61)
87 #define X86_CR3_LAM_U57		BIT_ULL(X86_CR3_LAM_U57_BIT)
88 #define X86_CR3_LAM_U48_BIT	(62)
89 #define X86_CR3_LAM_U48		BIT_ULL(X86_CR3_LAM_U48_BIT)
90 
91 #define X86_CR4_VME_BIT		(0)
92 #define X86_CR4_VME		BIT(X86_CR4_VME_BIT)
93 #define X86_CR4_PVI_BIT		(1)
94 #define X86_CR4_PVI		BIT(X86_CR4_PVI_BIT)
95 #define X86_CR4_TSD_BIT		(2)
96 #define X86_CR4_TSD		BIT(X86_CR4_TSD_BIT)
97 #define X86_CR4_DE_BIT		(3)
98 #define X86_CR4_DE		BIT(X86_CR4_DE_BIT)
99 #define X86_CR4_PSE_BIT		(4)
100 #define X86_CR4_PSE		BIT(X86_CR4_PSE_BIT)
101 #define X86_CR4_PAE_BIT		(5)
102 #define X86_CR4_PAE		BIT(X86_CR4_PAE_BIT)
103 #define X86_CR4_MCE_BIT		(6)
104 #define X86_CR4_MCE		BIT(X86_CR4_MCE_BIT)
105 #define X86_CR4_PGE_BIT		(7)
106 #define X86_CR4_PGE		BIT(X86_CR4_PGE_BIT)
107 #define X86_CR4_PCE_BIT		(8)
108 #define X86_CR4_PCE		BIT(X86_CR4_PCE_BIT)
109 #define X86_CR4_OSFXSR_BIT	(9)
110 #define X86_CR4_OSFXSR		BIT(X86_CR4_OSFXSR_BIT)
111 #define X86_CR4_OSXMMEXCPT_BIT	(10)
112 #define X86_CR4_OSXMMEXCPT	BIT(X86_CR4_OSXMMEXCPT_BIT)
113 #define X86_CR4_UMIP_BIT	(11)
114 #define X86_CR4_UMIP		BIT(X86_CR4_UMIP_BIT)
115 #define X86_CR4_LA57_BIT	(12)
116 #define X86_CR4_LA57		BIT(X86_CR4_LA57_BIT)
117 #define X86_CR4_VMXE_BIT	(13)
118 #define X86_CR4_VMXE		BIT(X86_CR4_VMXE_BIT)
119 #define X86_CR4_SMXE_BIT	(14)
120 #define X86_CR4_SMXE		BIT(X86_CR4_SMXE_BIT)
121 /* UNUSED			(15) */
122 #define X86_CR4_FSGSBASE_BIT	(16)
123 #define X86_CR4_FSGSBASE	BIT(X86_CR4_FSGSBASE_BIT)
124 #define X86_CR4_PCIDE_BIT	(17)
125 #define X86_CR4_PCIDE		BIT(X86_CR4_PCIDE_BIT)
126 #define X86_CR4_OSXSAVE_BIT	(18)
127 #define X86_CR4_OSXSAVE		BIT(X86_CR4_OSXSAVE_BIT)
128 #define X86_CR4_KL_BIT		(19)
129 #define X86_CR4_KL		BIT(X86_CR4_KL_BIT)
130 #define X86_CR4_SMEP_BIT	(20)
131 #define X86_CR4_SMEP		BIT(X86_CR4_SMEP_BIT)
132 #define X86_CR4_SMAP_BIT	(21)
133 #define X86_CR4_SMAP		BIT(X86_CR4_SMAP_BIT)
134 #define X86_CR4_PKE_BIT		(22)
135 #define X86_CR4_PKE		BIT(X86_CR4_PKE_BIT)
136 #define X86_CR4_CET_BIT		(23)
137 #define X86_CR4_CET		BIT(X86_CR4_CET_BIT)
138 #define X86_CR4_PKS_BIT		(24)
139 #define X86_CR4_PKS		BIT(X86_CR4_PKS_BIT)
140 #define X86_CR4_LAM_SUP_BIT	(28)
141 #define X86_CR4_LAM_SUP		BIT(X86_CR4_LAM_SUP_BIT)
142 
143 #define X86_EFLAGS_CF_BIT	(0)
144 #define X86_EFLAGS_CF		BIT(X86_EFLAGS_CF_BIT)
145 #define X86_EFLAGS_FIXED_BIT	(1)
146 #define X86_EFLAGS_FIXED	BIT(X86_EFLAGS_FIXED_BIT)
147 #define X86_EFLAGS_PF_BIT	(2)
148 #define X86_EFLAGS_PF		BIT(X86_EFLAGS_PF_BIT)
149 /* RESERVED 0			(3) */
150 #define X86_EFLAGS_AF_BIT	(4)
151 #define X86_EFLAGS_AF		BIT(X86_EFLAGS_AF_BIT)
152 /* RESERVED 0			(5) */
153 #define X86_EFLAGS_ZF_BIT	(6)
154 #define X86_EFLAGS_ZF		BIT(X86_EFLAGS_ZF_BIT)
155 #define X86_EFLAGS_SF_BIT	(7)
156 #define X86_EFLAGS_SF		BIT(X86_EFLAGS_SF_BIT)
157 #define X86_EFLAGS_TF_BIT	(8)
158 #define X86_EFLAGS_TF		BIT(X86_EFLAGS_TF_BIT)
159 #define X86_EFLAGS_IF_BIT	(9)
160 #define X86_EFLAGS_IF		BIT(X86_EFLAGS_IF_BIT)
161 #define X86_EFLAGS_DF_BIT	(10)
162 #define X86_EFLAGS_DF		BIT(X86_EFLAGS_DF_BIT)
163 #define X86_EFLAGS_OF_BIT	(11)
164 #define X86_EFLAGS_OF		BIT(X86_EFLAGS_OF_BIT)
165 #define X86_EFLAGS_IOPL		GENMASK(13, 12)
166 #define X86_EFLAGS_NT_BIT	(14)
167 #define X86_EFLAGS_NT		BIT(X86_EFLAGS_NT_BIT)
168 /* RESERVED 0			(15) */
169 #define X86_EFLAGS_RF_BIT	(16)
170 #define X86_EFLAGS_RF		BIT(X86_EFLAGS_RF_BIT)
171 #define X86_EFLAGS_VM_BIT	(17)
172 #define X86_EFLAGS_VM		BIT(X86_EFLAGS_VM_BIT)
173 #define X86_EFLAGS_AC_BIT	(18)
174 #define X86_EFLAGS_AC		BIT(X86_EFLAGS_AC_BIT)
175 #define X86_EFLAGS_VIF_BIT	(19)
176 #define X86_EFLAGS_VIF		BIT(X86_EFLAGS_VIF_BIT)
177 #define X86_EFLAGS_VIP_BIT	(20)
178 #define X86_EFLAGS_VIP		BIT(X86_EFLAGS_VIP_BIT)
179 #define X86_EFLAGS_ID_BIT	(21)
180 #define X86_EFLAGS_ID		BIT(X86_EFLAGS_ID_BIT)
181 
182 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \
183 			X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)
184 
185 
186 /*
187  * CPU features
188  */
189 
190 enum cpuid_output_regs {
191 	EAX,
192 	EBX,
193 	ECX,
194 	EDX
195 };
196 
197 struct cpuid { u32 a, b, c, d; };
198 
199 static inline struct cpuid raw_cpuid(u32 function, u32 index)
200 {
201 	struct cpuid r;
202 	asm volatile ("cpuid"
203 		      : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d)
204 		      : "0"(function), "2"(index));
205 	return r;
206 }
207 
208 static inline struct cpuid cpuid_indexed(u32 function, u32 index)
209 {
210 	u32 level = raw_cpuid(function & 0xf0000000, 0).a;
211 	if (level < function)
212 	return (struct cpuid) { 0, 0, 0, 0 };
213 	return raw_cpuid(function, index);
214 }
215 
216 static inline struct cpuid cpuid(u32 function)
217 {
218 	return cpuid_indexed(function, 0);
219 }
220 
221 static inline bool is_intel(void)
222 {
223 	struct cpuid c = cpuid(0);
224 	u32 name[4] = {c.b, c.d, c.c };
225 
226 	return strcmp((char *)name, "GenuineIntel") == 0;
227 }
228 
229 /*
230  * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
231  * passed by value with no overhead.
232  */
233 struct x86_cpu_feature {
234 	u32	function;
235 	u16	index;
236 	u8	reg;
237 	u8	bit;
238 };
239 
240 #define X86_CPU_FEATURE(fn, idx, gpr, __bit)					\
241 ({										\
242 	struct x86_cpu_feature feature = {					\
243 		.function = fn,							\
244 		.index = idx,							\
245 		.reg = gpr,							\
246 		.bit = __bit,							\
247 	};									\
248 										\
249 	static_assert((fn & 0xc0000000) == 0 ||					\
250 		      (fn & 0xc0000000) == 0x40000000 ||			\
251 		      (fn & 0xc0000000) == 0x80000000 ||			\
252 		      (fn & 0xc0000000) == 0xc0000000);				\
253 	static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE));	\
254 	feature;								\
255 })
256 
257 /*
258  * Basic Leafs, a.k.a. Intel defined
259  */
260 #define X86_FEATURE_MWAIT		X86_CPU_FEATURE(0x1, 0, ECX, 3)
261 #define X86_FEATURE_VMX			X86_CPU_FEATURE(0x1, 0, ECX, 5)
262 #define X86_FEATURE_PDCM		X86_CPU_FEATURE(0x1, 0, ECX, 15)
263 #define X86_FEATURE_PCID		X86_CPU_FEATURE(0x1, 0, ECX, 17)
264 #define X86_FEATURE_X2APIC		X86_CPU_FEATURE(0x1, 0, ECX, 21)
265 #define X86_FEATURE_MOVBE		X86_CPU_FEATURE(0x1, 0, ECX, 22)
266 #define X86_FEATURE_TSC_DEADLINE_TIMER	X86_CPU_FEATURE(0x1, 0, ECX, 24)
267 #define X86_FEATURE_XSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 26)
268 #define X86_FEATURE_OSXSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 27)
269 #define X86_FEATURE_RDRAND		X86_CPU_FEATURE(0x1, 0, ECX, 30)
270 #define X86_FEATURE_MCE			X86_CPU_FEATURE(0x1, 0, EDX, 7)
271 #define X86_FEATURE_APIC		X86_CPU_FEATURE(0x1, 0, EDX, 9)
272 #define X86_FEATURE_CLFLUSH		X86_CPU_FEATURE(0x1, 0, EDX, 19)
273 #define X86_FEATURE_DS			X86_CPU_FEATURE(0x1, 0, EDX, 21)
274 #define X86_FEATURE_XMM			X86_CPU_FEATURE(0x1, 0, EDX, 25)
275 #define X86_FEATURE_XMM2		X86_CPU_FEATURE(0x1, 0, EDX, 26)
276 #define X86_FEATURE_TSC_ADJUST		X86_CPU_FEATURE(0x7, 0, EBX, 1)
277 #define X86_FEATURE_HLE			X86_CPU_FEATURE(0x7, 0, EBX, 4)
278 #define X86_FEATURE_SMEP		X86_CPU_FEATURE(0x7, 0, EBX, 7)
279 #define X86_FEATURE_INVPCID		X86_CPU_FEATURE(0x7, 0, EBX, 10)
280 #define X86_FEATURE_RTM			X86_CPU_FEATURE(0x7, 0, EBX, 11)
281 #define X86_FEATURE_SMAP		X86_CPU_FEATURE(0x7, 0, EBX, 20)
282 #define X86_FEATURE_PCOMMIT		X86_CPU_FEATURE(0x7, 0, EBX, 22)
283 #define X86_FEATURE_CLFLUSHOPT		X86_CPU_FEATURE(0x7, 0, EBX, 23)
284 #define X86_FEATURE_CLWB		X86_CPU_FEATURE(0x7, 0, EBX, 24)
285 #define X86_FEATURE_INTEL_PT		X86_CPU_FEATURE(0x7, 0, EBX, 25)
286 #define X86_FEATURE_UMIP		X86_CPU_FEATURE(0x7, 0, ECX, 2)
287 #define X86_FEATURE_PKU			X86_CPU_FEATURE(0x7, 0, ECX, 3)
288 #define X86_FEATURE_LA57		X86_CPU_FEATURE(0x7, 0, ECX, 16)
289 #define X86_FEATURE_RDPID		X86_CPU_FEATURE(0x7, 0, ECX, 22)
290 #define X86_FEATURE_SHSTK		X86_CPU_FEATURE(0x7, 0, ECX, 7)
291 #define X86_FEATURE_IBT			X86_CPU_FEATURE(0x7, 0, EDX, 20)
292 #define X86_FEATURE_SPEC_CTRL		X86_CPU_FEATURE(0x7, 0, EDX, 26)
293 #define X86_FEATURE_FLUSH_L1D		X86_CPU_FEATURE(0x7, 0, EDX, 28)
294 #define X86_FEATURE_ARCH_CAPABILITIES	X86_CPU_FEATURE(0x7, 0, EDX, 29)
295 #define X86_FEATURE_PKS			X86_CPU_FEATURE(0x7, 0, ECX, 31)
296 #define X86_FEATURE_LAM			X86_CPU_FEATURE(0x7, 1, EAX, 26)
297 
298 /*
299  * KVM defined leafs
300  */
301 #define KVM_FEATURE_ASYNC_PF		X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
302 #define KVM_FEATURE_ASYNC_PF_INT	X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
303 
304 /*
305  * Extended Leafs, a.k.a. AMD defined
306  */
307 #define X86_FEATURE_SVM			X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
308 #define X86_FEATURE_PERFCTR_CORE	X86_CPU_FEATURE(0x80000001, 0, ECX, 23)
309 #define X86_FEATURE_NX			X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
310 #define X86_FEATURE_GBPAGES		X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
311 #define X86_FEATURE_RDTSCP		X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
312 #define X86_FEATURE_LM			X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
313 #define X86_FEATURE_RDPRU		X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
314 #define X86_FEATURE_AMD_IBPB		X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
315 #define X86_FEATURE_NPT			X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
316 #define X86_FEATURE_LBRV		X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
317 #define X86_FEATURE_NRIPS		X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
318 #define X86_FEATURE_TSCRATEMSR		X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
319 #define X86_FEATURE_PAUSEFILTER		X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
320 #define X86_FEATURE_PFTHRESHOLD		X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
321 #define X86_FEATURE_VGIF		X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
322 #define X86_FEATURE_VNMI		X86_CPU_FEATURE(0x8000000A, 0, EDX, 25)
323 #define X86_FEATURE_SME			X86_CPU_FEATURE(0x8000001F, 0, EAX,  0)
324 #define X86_FEATURE_SEV			X86_CPU_FEATURE(0x8000001F, 0, EAX,  1)
325 #define X86_FEATURE_VM_PAGE_FLUSH	X86_CPU_FEATURE(0x8000001F, 0, EAX,  2)
326 #define X86_FEATURE_SEV_ES		X86_CPU_FEATURE(0x8000001F, 0, EAX,  3)
327 #define X86_FEATURE_SEV_SNP		X86_CPU_FEATURE(0x8000001F, 0, EAX,  4)
328 #define X86_FEATURE_V_TSC_AUX		X86_CPU_FEATURE(0x8000001F, 0, EAX,  9)
329 #define X86_FEATURE_SME_COHERENT	X86_CPU_FEATURE(0x8000001F, 0, EAX, 10)
330 #define X86_FEATURE_DEBUG_SWAP		X86_CPU_FEATURE(0x8000001F, 0, EAX, 14)
331 #define X86_FEATURE_SVSM		X86_CPU_FEATURE(0x8000001F, 0, EAX, 28)
332 #define X86_FEATURE_AMD_PMU_V2		X86_CPU_FEATURE(0x80000022, 0, EAX, 0)
333 
334 /*
335  * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit
336  * value/property as opposed to a single-bit feature.  Again, pack the info
337  * into a 64-bit value to pass by value with no overhead on 64-bit builds.
338  */
339 struct x86_cpu_property {
340 	u32	function;
341 	u8	index;
342 	u8	reg;
343 	u8	lo_bit;
344 	u8	hi_bit;
345 };
346 #define X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit)			\
347 ({										\
348 	struct x86_cpu_property property = {					\
349 		.function = fn,							\
350 		.index = idx,							\
351 		.reg = gpr,							\
352 		.lo_bit = low_bit,						\
353 		.hi_bit = high_bit,						\
354 	};									\
355 										\
356 	static_assert(low_bit < high_bit);					\
357 	static_assert((fn & 0xc0000000) == 0 ||					\
358 		      (fn & 0xc0000000) == 0x40000000 ||			\
359 		      (fn & 0xc0000000) == 0x80000000 ||			\
360 		      (fn & 0xc0000000) == 0xc0000000);				\
361 	static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE));	\
362 	property;								\
363 })
364 
365 #define X86_PROPERTY_MAX_BASIC_LEAF		X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
366 #define X86_PROPERTY_PMU_VERSION		X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
367 #define X86_PROPERTY_PMU_NR_GP_COUNTERS		X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15)
368 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH	X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23)
369 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH	X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31)
370 #define X86_PROPERTY_PMU_EVENTS_MASK		X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7)
371 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK	X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31)
372 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS	X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4)
373 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH	X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12)
374 
375 #define X86_PROPERTY_SUPPORTED_XCR0_LO		X86_CPU_PROPERTY(0xd,  0, EAX,  0, 31)
376 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0	X86_CPU_PROPERTY(0xd,  0, EBX,  0, 31)
377 #define X86_PROPERTY_XSTATE_MAX_SIZE		X86_CPU_PROPERTY(0xd,  0, ECX,  0, 31)
378 #define X86_PROPERTY_SUPPORTED_XCR0_HI		X86_CPU_PROPERTY(0xd,  0, EDX,  0, 31)
379 
380 #define X86_PROPERTY_XSTATE_TILE_SIZE		X86_CPU_PROPERTY(0xd, 18, EAX,  0, 31)
381 #define X86_PROPERTY_XSTATE_TILE_OFFSET		X86_CPU_PROPERTY(0xd, 18, EBX,  0, 31)
382 
383 #define X86_PROPERTY_INTEL_PT_NR_RANGES		X86_CPU_PROPERTY(0x14, 1, EAX,  0, 2)
384 
385 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES	X86_CPU_PROPERTY(0x1d, 0, EAX,  0, 31)
386 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES	X86_CPU_PROPERTY(0x1d, 1, EAX,  0, 15)
387 #define X86_PROPERTY_AMX_BYTES_PER_TILE		X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
388 #define X86_PROPERTY_AMX_BYTES_PER_ROW		X86_CPU_PROPERTY(0x1d, 1, EBX, 0,  15)
389 #define X86_PROPERTY_AMX_NR_TILE_REGS		X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
390 #define X86_PROPERTY_AMX_MAX_ROWS		X86_CPU_PROPERTY(0x1d, 1, ECX, 0,  15)
391 
392 #define X86_PROPERTY_MAX_KVM_LEAF		X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)
393 
394 #define X86_PROPERTY_MAX_EXT_LEAF		X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31)
395 #define X86_PROPERTY_MAX_PHY_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7)
396 #define X86_PROPERTY_MAX_VIRT_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15)
397 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23)
398 #define X86_PROPERTY_SEV_C_BIT			X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5)
399 #define X86_PROPERTY_PHYS_ADDR_REDUCTION	X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
400 #define X86_PROPERTY_NR_PERFCTR_CORE		X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3)
401 #define X86_PROPERTY_NR_PERFCTR_NB		X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15)
402 
403 #define X86_PROPERTY_MAX_CENTAUR_LEAF		X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
404 
405 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi)
406 {
407 	union {
408 		struct cpuid cpuid;
409 		u32 gprs[4];
410 	} c;
411 
412 	c.cpuid = cpuid_indexed(function, index);
413 
414 	return (c.gprs[reg] & GENMASK(hi, lo)) >> lo;
415 }
416 
417 static inline bool this_cpu_has(struct x86_cpu_feature feature)
418 {
419 	return __this_cpu_has(feature.function, feature.index,
420 			      feature.reg, feature.bit, feature.bit);
421 }
422 
423 static inline uint32_t this_cpu_property(struct x86_cpu_property property)
424 {
425 	return __this_cpu_has(property.function, property.index,
426 			      property.reg, property.lo_bit, property.hi_bit);
427 }
428 
429 static __always_inline bool this_cpu_has_p(struct x86_cpu_property property)
430 {
431 	uint32_t max_leaf;
432 
433 	switch (property.function & 0xc0000000) {
434 	case 0:
435 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
436 		break;
437 	case 0x40000000:
438 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
439 		break;
440 	case 0x80000000:
441 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
442 		break;
443 	case 0xc0000000:
444 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
445 	}
446 	return max_leaf >= property.function;
447 }
448 
449 static inline u8 cpuid_maxphyaddr(void)
450 {
451 	if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR))
452 		return 36;
453 
454 	return this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR);
455 }
456 
457 static inline u64 this_cpu_supported_xcr0(void)
458 {
459 	if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO))
460 		return 0;
461 
462 	return (u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) |
463 	       ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
464 }
465 
466 struct far_pointer32 {
467 	u32 offset;
468 	u16 selector;
469 } __attribute__((packed));
470 
471 struct descriptor_table_ptr {
472 	u16 limit;
473 	ulong base;
474 } __attribute__((packed));
475 
476 static inline void clac(void)
477 {
478 	asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory");
479 }
480 
481 static inline void stac(void)
482 {
483 	asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory");
484 }
485 
486 static inline u16 read_cs(void)
487 {
488 	unsigned val;
489 
490 	asm volatile ("mov %%cs, %0" : "=mr"(val));
491 	return val;
492 }
493 
494 static inline u16 read_ds(void)
495 {
496 	unsigned val;
497 
498 	asm volatile ("mov %%ds, %0" : "=mr"(val));
499 	return val;
500 }
501 
502 static inline u16 read_es(void)
503 {
504 	unsigned val;
505 
506 	asm volatile ("mov %%es, %0" : "=mr"(val));
507 	return val;
508 }
509 
510 static inline u16 read_ss(void)
511 {
512 	unsigned val;
513 
514 	asm volatile ("mov %%ss, %0" : "=mr"(val));
515 	return val;
516 }
517 
518 static inline u16 read_fs(void)
519 {
520 	unsigned val;
521 
522 	asm volatile ("mov %%fs, %0" : "=mr"(val));
523 	return val;
524 }
525 
526 static inline u16 read_gs(void)
527 {
528 	unsigned val;
529 
530 	asm volatile ("mov %%gs, %0" : "=mr"(val));
531 	return val;
532 }
533 
534 static inline unsigned long read_rflags(void)
535 {
536 	unsigned long f;
537 	asm volatile ("pushf; pop %0\n\t" : "=rm"(f));
538 	return f;
539 }
540 
541 static inline void write_ds(unsigned val)
542 {
543 	asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory");
544 }
545 
546 static inline void write_es(unsigned val)
547 {
548 	asm volatile ("mov %0, %%es" : : "rm"(val) : "memory");
549 }
550 
551 static inline void write_ss(unsigned val)
552 {
553 	asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory");
554 }
555 
556 static inline void write_fs(unsigned val)
557 {
558 	asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory");
559 }
560 
561 static inline void write_gs(unsigned val)
562 {
563 	asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory");
564 }
565 
566 static inline void write_rflags(unsigned long f)
567 {
568 	asm volatile ("push %0; popf\n\t" : : "rm"(f));
569 }
570 
571 static inline void set_iopl(int iopl)
572 {
573 	unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL;
574 	flags |= iopl * (X86_EFLAGS_IOPL / 3);
575 	write_rflags(flags);
576 }
577 
578 /*
579  * Don't use the safe variants for rdmsr() or wrmsr().  The exception fixup
580  * infrastructure uses per-CPU data and thus consumes GS.base.  Various tests
581  * temporarily modify MSR_GS_BASE and will explode when trying to determine
582  * whether or not RDMSR/WRMSR faulted.
583  */
584 static inline u64 rdmsr(u32 index)
585 {
586 	u32 a, d;
587 	asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory");
588 	return a | ((u64)d << 32);
589 }
590 
591 static inline void wrmsr(u32 index, u64 val)
592 {
593 	u32 a = val, d = val >> 32;
594 	asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory");
595 }
596 
597 #define __rdreg64_safe(fep, insn, index, val)				\
598 ({									\
599 	uint32_t a, d;							\
600 	int vector;							\
601 									\
602 	vector = __asm_safe_out2(fep, insn, "=a"(a), "=d"(d), "c"(index));\
603 									\
604 	if (vector)							\
605 		*(val) = 0;						\
606 	else								\
607 		*(val) = (uint64_t)a | ((uint64_t)d << 32);		\
608 	vector;								\
609 })
610 
611 #define rdreg64_safe(insn, index, val)					\
612 	__rdreg64_safe("", insn, index, val)
613 
614 #define __wrreg64_safe(fep, insn, index, val)				\
615 ({									\
616 	uint32_t eax = (val), edx = (val) >> 32;			\
617 									\
618 	__asm_safe(fep, insn, "a" (eax), "d" (edx), "c" (index));	\
619 })
620 
621 #define wrreg64_safe(insn, index, val)					\
622 	__wrreg64_safe("", insn, index, val)
623 
624 static inline int rdmsr_safe(u32 index, uint64_t *val)
625 {
626 	return rdreg64_safe("rdmsr", index, val);
627 }
628 
629 static inline int rdmsr_fep_safe(u32 index, uint64_t *val)
630 {
631 	return __rdreg64_safe(KVM_FEP, "rdmsr", index, val);
632 }
633 
634 static inline int wrmsr_safe(u32 index, u64 val)
635 {
636 	return wrreg64_safe("wrmsr", index, val);
637 }
638 
639 static inline int wrmsr_fep_safe(u32 index, u64 val)
640 {
641 	return __wrreg64_safe(KVM_FEP, "wrmsr", index, val);
642 }
643 
644 static inline int rdpmc_safe(u32 index, uint64_t *val)
645 {
646 	return rdreg64_safe("rdpmc", index, val);
647 }
648 
649 static inline uint64_t rdpmc(uint32_t index)
650 {
651 	uint64_t val;
652 	int vector = rdpmc_safe(index, &val);
653 
654 	assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")",
655 		   exception_mnemonic(vector), index);
656 	return val;
657 }
658 
659 static inline int xgetbv_safe(u32 index, u64 *result)
660 {
661 	return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result);
662 }
663 
664 static inline int xsetbv_safe(u32 index, u64 value)
665 {
666 	return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value);
667 }
668 
669 static inline int write_cr0_safe(ulong val)
670 {
671 	return asm_safe("mov %0,%%cr0", "r" (val));
672 }
673 
674 static inline void write_cr0(ulong val)
675 {
676 	int vector = write_cr0_safe(val);
677 
678 	assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx",
679 		   vector, val);
680 }
681 
682 static inline ulong read_cr0(void)
683 {
684 	ulong val;
685 	asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory");
686 	return val;
687 }
688 
689 static inline void write_cr2(ulong val)
690 {
691 	asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory");
692 }
693 
694 static inline ulong read_cr2(void)
695 {
696 	ulong val;
697 	asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory");
698 	return val;
699 }
700 
701 static inline int write_cr3_safe(ulong val)
702 {
703 	return asm_safe("mov %0,%%cr3", "r" (val));
704 }
705 
706 static inline void write_cr3(ulong val)
707 {
708 	int vector = write_cr3_safe(val);
709 
710 	assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx",
711 		   vector, val);
712 }
713 
714 static inline ulong read_cr3(void)
715 {
716 	ulong val;
717 	asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory");
718 	return val;
719 }
720 
721 static inline void update_cr3(void *cr3)
722 {
723 	write_cr3((ulong)cr3);
724 }
725 
726 static inline int write_cr4_safe(ulong val)
727 {
728 	return asm_safe("mov %0,%%cr4", "r" (val));
729 }
730 
731 static inline void write_cr4(ulong val)
732 {
733 	int vector = write_cr4_safe(val);
734 
735 	assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx",
736 		   vector, val);
737 }
738 
739 static inline ulong read_cr4(void)
740 {
741 	ulong val;
742 	asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory");
743 	return val;
744 }
745 
746 static inline void write_cr8(ulong val)
747 {
748 	asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory");
749 }
750 
751 static inline ulong read_cr8(void)
752 {
753 	ulong val;
754 	asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory");
755 	return val;
756 }
757 
758 static inline void lgdt(const struct descriptor_table_ptr *ptr)
759 {
760 	asm volatile ("lgdt %0" : : "m"(*ptr));
761 }
762 
763 static inline int lgdt_safe(const struct descriptor_table_ptr *ptr)
764 {
765 	return asm_safe("lgdt %0", "m"(*ptr));
766 }
767 
768 static inline int lgdt_fep_safe(const struct descriptor_table_ptr *ptr)
769 {
770 	return asm_fep_safe("lgdt %0", "m"(*ptr));
771 }
772 
773 static inline void sgdt(struct descriptor_table_ptr *ptr)
774 {
775 	asm volatile ("sgdt %0" : "=m"(*ptr));
776 }
777 
778 static inline void lidt(const struct descriptor_table_ptr *ptr)
779 {
780 	asm volatile ("lidt %0" : : "m"(*ptr));
781 }
782 
783 static inline int lidt_safe(const struct descriptor_table_ptr *ptr)
784 {
785 	return asm_safe("lidt %0", "m"(*ptr));
786 }
787 
788 static inline int lidt_fep_safe(const struct descriptor_table_ptr *ptr)
789 {
790 	return asm_fep_safe("lidt %0", "m"(*ptr));
791 }
792 
793 static inline void sidt(struct descriptor_table_ptr *ptr)
794 {
795 	asm volatile ("sidt %0" : "=m"(*ptr));
796 }
797 
798 static inline void lldt(u16 val)
799 {
800 	asm volatile ("lldt %0" : : "rm"(val));
801 }
802 
803 static inline int lldt_safe(u16 val)
804 {
805 	return asm_safe("lldt %0", "rm"(val));
806 }
807 
808 static inline int lldt_fep_safe(u16 val)
809 {
810 	return asm_safe("lldt %0", "rm"(val));
811 }
812 
813 static inline u16 sldt(void)
814 {
815 	u16 val;
816 	asm volatile ("sldt %0" : "=rm"(val));
817 	return val;
818 }
819 
820 static inline void ltr(u16 val)
821 {
822 	asm volatile ("ltr %0" : : "rm"(val));
823 }
824 
825 static inline int ltr_safe(u16 val)
826 {
827 	return asm_safe("ltr %0", "rm"(val));
828 }
829 
830 static inline int ltr_fep_safe(u16 val)
831 {
832 	return asm_safe("ltr %0", "rm"(val));
833 }
834 
835 static inline u16 str(void)
836 {
837 	u16 val;
838 	asm volatile ("str %0" : "=rm"(val));
839 	return val;
840 }
841 
842 static inline void write_dr0(void *val)
843 {
844 	asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory");
845 }
846 
847 static inline void write_dr1(void *val)
848 {
849 	asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory");
850 }
851 
852 static inline void write_dr2(void *val)
853 {
854 	asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory");
855 }
856 
857 static inline void write_dr3(void *val)
858 {
859 	asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory");
860 }
861 
862 static inline void write_dr6(ulong val)
863 {
864 	asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory");
865 }
866 
867 static inline ulong read_dr6(void)
868 {
869 	ulong val;
870 	asm volatile ("mov %%dr6, %0" : "=r"(val));
871 	return val;
872 }
873 
874 static inline void write_dr7(ulong val)
875 {
876 	asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory");
877 }
878 
879 static inline ulong read_dr7(void)
880 {
881 	ulong val;
882 	asm volatile ("mov %%dr7, %0" : "=r"(val));
883 	return val;
884 }
885 
886 static inline void pause(void)
887 {
888 	asm volatile ("pause");
889 }
890 
891 static inline void cli(void)
892 {
893 	asm volatile ("cli");
894 }
895 
896 /*
897  * See also safe_halt().
898  */
899 static inline void sti(void)
900 {
901 	asm volatile ("sti");
902 }
903 
904 /*
905  * Enable interrupts and ensure that interrupts are evaluated upon return from
906  * this function, i.e. execute a nop to consume the STi interrupt shadow.
907  */
908 static inline void sti_nop(void)
909 {
910 	asm volatile ("sti; nop");
911 }
912 
913 /*
914  * Enable interrupts for one instruction (nop), to allow the CPU to process all
915  * interrupts that are already pending.
916  */
917 static inline void sti_nop_cli(void)
918 {
919 	asm volatile ("sti; nop; cli");
920 }
921 
922 static inline unsigned long long rdrand(void)
923 {
924 	long long r;
925 
926 	asm volatile("rdrand %0\n\t"
927 		     "jc 1f\n\t"
928 		     "mov $0, %0\n\t"
929 		     "1:\n\t" : "=r" (r));
930 	return r;
931 }
932 
933 static inline unsigned long long rdtsc(void)
934 {
935 	long long r;
936 
937 #ifdef __x86_64__
938 	unsigned a, d;
939 
940 	asm volatile ("rdtsc" : "=a"(a), "=d"(d));
941 	r = a | ((long long)d << 32);
942 #else
943 	asm volatile ("rdtsc" : "=A"(r));
944 #endif
945 	return r;
946 }
947 
948 /*
949  * Per the advice in the SDM, volume 2, the sequence "mfence; lfence"
950  * executed immediately before rdtsc ensures that rdtsc will be
951  * executed only after all previous instructions have executed and all
952  * previous loads and stores are globally visible. In addition, the
953  * lfence immediately after rdtsc ensures that rdtsc will be executed
954  * prior to the execution of any subsequent instruction.
955  */
956 static inline unsigned long long fenced_rdtsc(void)
957 {
958 	unsigned long long tsc;
959 
960 #ifdef __x86_64__
961 	unsigned int eax, edx;
962 
963 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
964 	tsc = eax | ((unsigned long long)edx << 32);
965 #else
966 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc));
967 #endif
968 	return tsc;
969 }
970 
971 static inline unsigned long long rdtscp(u32 *aux)
972 {
973 	long long r;
974 
975 #ifdef __x86_64__
976 	unsigned a, d;
977 
978 	asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux));
979 	r = a | ((long long)d << 32);
980 #else
981 	asm volatile ("rdtscp" : "=A"(r), "=c"(*aux));
982 #endif
983 	return r;
984 }
985 
986 static inline void wrtsc(u64 tsc)
987 {
988 	wrmsr(MSR_IA32_TSC, tsc);
989 }
990 
991 
992 static inline void invlpg(volatile void *va)
993 {
994 	asm volatile("invlpg (%0)" ::"r" (va) : "memory");
995 }
996 
997 struct invpcid_desc {
998 	u64 pcid : 12;
999 	u64 rsv  : 52;
1000 	u64 addr : 64;
1001 };
1002 
1003 static inline int invpcid_safe(unsigned long type, struct invpcid_desc *desc)
1004 {
1005 	/* invpcid (%rax), %rbx */
1006 	return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type));
1007 }
1008 
1009 /*
1010  * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's
1011  * intended to be a wake event arrives *after* HLT is executed.  Modern CPUs,
1012  * except for a few oddballs that KVM is unlikely to run on, block IRQs for one
1013  * instruction after STI, *if* RFLAGS.IF=0 before STI.  Note, Intel CPUs may
1014  * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too.
1015  */
1016 static inline void safe_halt(void)
1017 {
1018 	asm volatile("sti; hlt");
1019 }
1020 
1021 static inline u32 read_pkru(void)
1022 {
1023 	unsigned int eax, edx;
1024 	unsigned int ecx = 0;
1025 	unsigned int pkru;
1026 
1027 	asm volatile(".byte 0x0f,0x01,0xee\n\t"
1028 		     : "=a" (eax), "=d" (edx)
1029 		     : "c" (ecx));
1030 	pkru = eax;
1031 	return pkru;
1032 }
1033 
1034 static inline void write_pkru(u32 pkru)
1035 {
1036 	unsigned int eax = pkru;
1037 	unsigned int ecx = 0;
1038 	unsigned int edx = 0;
1039 
1040 	asm volatile(".byte 0x0f,0x01,0xef\n\t"
1041 		     : : "a" (eax), "c" (ecx), "d" (edx));
1042 }
1043 
1044 static inline bool is_canonical(u64 addr)
1045 {
1046 	int va_width, shift_amt;
1047 
1048 	if (this_cpu_has_p(X86_PROPERTY_MAX_VIRT_ADDR))
1049 		va_width = this_cpu_property(X86_PROPERTY_MAX_VIRT_ADDR);
1050 	else
1051 		va_width = 48;
1052 
1053 	shift_amt = 64 - va_width;
1054 	return (s64)(addr << shift_amt) >> shift_amt == addr;
1055 }
1056 
1057 static inline void flush_tlb(void)
1058 {
1059 	ulong cr4;
1060 
1061 	cr4 = read_cr4();
1062 	write_cr4(cr4 ^ X86_CR4_PGE);
1063 	write_cr4(cr4);
1064 }
1065 
1066 static inline void generate_non_canonical_gp(void)
1067 {
1068 	*(volatile u64 *)NONCANONICAL = 0;
1069 }
1070 
1071 static inline void generate_ud(void)
1072 {
1073 	asm volatile ("ud2");
1074 }
1075 
1076 static inline void generate_de(void)
1077 {
1078 	asm volatile (
1079 		"xor %%eax, %%eax\n\t"
1080 		"xor %%ebx, %%ebx\n\t"
1081 		"xor %%edx, %%edx\n\t"
1082 		"idiv %%ebx\n\t"
1083 		::: "eax", "ebx", "edx");
1084 }
1085 
1086 static inline void generate_bp(void)
1087 {
1088 	asm volatile ("int3");
1089 }
1090 
1091 static inline void generate_single_step_db(void)
1092 {
1093 	write_rflags(read_rflags() | X86_EFLAGS_TF);
1094 	asm volatile("nop");
1095 }
1096 
1097 static inline uint64_t generate_usermode_ac(void)
1098 {
1099 	/*
1100 	 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address.
1101 	 * Disclaimer: It is assumed that the stack pointer is aligned
1102 	 * on a 16-byte boundary as x86_64 stacks should be.
1103 	 */
1104 	asm volatile("movq $0, -0x4(%rsp)");
1105 
1106 	return 0;
1107 }
1108 
1109 /*
1110  * Switch from 64-bit to 32-bit mode and generate #OF via INTO.  Note, if RIP
1111  * or RSP holds a 64-bit value, this helper will NOT generate #OF.
1112  */
1113 static inline void generate_of(void)
1114 {
1115 	struct far_pointer32 fp = {
1116 		.offset = (uintptr_t)&&into,
1117 		.selector = KERNEL_CS32,
1118 	};
1119 	uintptr_t rsp;
1120 
1121 	asm volatile ("mov %%rsp, %0" : "=r"(rsp));
1122 
1123 	if (fp.offset != (uintptr_t)&&into) {
1124 		printf("Code address too high.\n");
1125 		return;
1126 	}
1127 	if ((u32)rsp != rsp) {
1128 		printf("Stack address too high.\n");
1129 		return;
1130 	}
1131 
1132 	asm goto ("lcall *%0" : : "m" (fp) : "rax" : into);
1133 	return;
1134 into:
1135 	asm volatile (".code32;"
1136 		      "movl $0x7fffffff, %eax;"
1137 		      "addl %eax, %eax;"
1138 		      "into;"
1139 		      "lret;"
1140 		      ".code64");
1141 	__builtin_unreachable();
1142 }
1143 
1144 static inline void fnop(void)
1145 {
1146 	asm volatile("fnop");
1147 }
1148 
1149 /* If CR0.TS is set in L2, #NM is generated. */
1150 static inline void generate_cr0_ts_nm(void)
1151 {
1152 	write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS);
1153 	fnop();
1154 }
1155 
1156 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */
1157 static inline void generate_cr0_em_nm(void)
1158 {
1159 	write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM);
1160 	fnop();
1161 }
1162 
1163 static inline bool is_la57_enabled(void)
1164 {
1165 	return !!(read_cr4() & X86_CR4_LA57);
1166 }
1167 
1168 static inline bool is_lam_sup_enabled(void)
1169 {
1170 	return !!(read_cr4() & X86_CR4_LAM_SUP);
1171 }
1172 
1173 static inline bool is_lam_u48_enabled(void)
1174 {
1175 	return (read_cr3() & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)) == X86_CR3_LAM_U48;
1176 }
1177 
1178 static inline bool is_lam_u57_enabled(void)
1179 {
1180 	return !!(read_cr3() & X86_CR3_LAM_U57);
1181 }
1182 
1183 #endif
1184