xref: /kvm-unit-tests/lib/x86/processor.h (revision 9a3266bf023e4adf39fe18f2c083c1037915da9e)
1 #ifndef _X86_PROCESSOR_H_
2 #define _X86_PROCESSOR_H_
3 
4 #include "libcflat.h"
5 #include "desc.h"
6 #include "msr.h"
7 #include <bitops.h>
8 #include <stdint.h>
9 #include <util.h>
10 
11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull
12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull
13 #define NONCANONICAL	 0xaaaaaaaaaaaaaaaaull
14 
15 #define LAM57_MASK	GENMASK_ULL(62, 57)
16 #define LAM48_MASK	GENMASK_ULL(62, 48)
17 
18 /*
19  * Get a linear address by combining @addr with a non-canonical pattern in the
20  * @mask bits.
21  */
22 static inline u64 get_non_canonical(u64 addr, u64 mask)
23 {
24 	return (addr & ~mask) | (NONCANONICAL & mask);
25 }
26 
27 #ifdef __x86_64__
28 #  define R "r"
29 #  define W "q"
30 #  define S "8"
31 #else
32 #  define R "e"
33 #  define W "l"
34 #  define S "4"
35 #endif
36 
37 #define DE_VECTOR 0
38 #define DB_VECTOR 1
39 #define NMI_VECTOR 2
40 #define BP_VECTOR 3
41 #define OF_VECTOR 4
42 #define BR_VECTOR 5
43 #define UD_VECTOR 6
44 #define NM_VECTOR 7
45 #define DF_VECTOR 8
46 #define TS_VECTOR 10
47 #define NP_VECTOR 11
48 #define SS_VECTOR 12
49 #define GP_VECTOR 13
50 #define PF_VECTOR 14
51 #define MF_VECTOR 16
52 #define AC_VECTOR 17
53 #define MC_VECTOR 18
54 #define XM_VECTOR 19
55 #define XF_VECTOR XM_VECTOR /* AMD */
56 #define VE_VECTOR 20 /* Intel only */
57 #define CP_VECTOR 21
58 #define HV_VECTOR 28 /* AMD only */
59 #define VC_VECTOR 29 /* AMD only */
60 #define SX_VECTOR 30 /* AMD only */
61 
62 #define X86_CR0_PE_BIT		(0)
63 #define X86_CR0_PE		BIT(X86_CR0_PE_BIT)
64 #define X86_CR0_MP_BIT		(1)
65 #define X86_CR0_MP		BIT(X86_CR0_MP_BIT)
66 #define X86_CR0_EM_BIT		(2)
67 #define X86_CR0_EM		BIT(X86_CR0_EM_BIT)
68 #define X86_CR0_TS_BIT		(3)
69 #define X86_CR0_TS		BIT(X86_CR0_TS_BIT)
70 #define X86_CR0_ET_BIT		(4)
71 #define X86_CR0_ET		BIT(X86_CR0_ET_BIT)
72 #define X86_CR0_NE_BIT		(5)
73 #define X86_CR0_NE		BIT(X86_CR0_NE_BIT)
74 #define X86_CR0_WP_BIT		(16)
75 #define X86_CR0_WP		BIT(X86_CR0_WP_BIT)
76 #define X86_CR0_AM_BIT		(18)
77 #define X86_CR0_AM		BIT(X86_CR0_AM_BIT)
78 #define X86_CR0_NW_BIT		(29)
79 #define X86_CR0_NW		BIT(X86_CR0_NW_BIT)
80 #define X86_CR0_CD_BIT		(30)
81 #define X86_CR0_CD		BIT(X86_CR0_CD_BIT)
82 #define X86_CR0_PG_BIT		(31)
83 #define X86_CR0_PG		BIT(X86_CR0_PG_BIT)
84 
85 #define X86_CR3_PCID_MASK	GENMASK(11, 0)
86 #define X86_CR3_LAM_U57_BIT	(61)
87 #define X86_CR3_LAM_U57		BIT_ULL(X86_CR3_LAM_U57_BIT)
88 #define X86_CR3_LAM_U48_BIT	(62)
89 #define X86_CR3_LAM_U48		BIT_ULL(X86_CR3_LAM_U48_BIT)
90 
91 #define X86_CR4_VME_BIT		(0)
92 #define X86_CR4_VME		BIT(X86_CR4_VME_BIT)
93 #define X86_CR4_PVI_BIT		(1)
94 #define X86_CR4_PVI		BIT(X86_CR4_PVI_BIT)
95 #define X86_CR4_TSD_BIT		(2)
96 #define X86_CR4_TSD		BIT(X86_CR4_TSD_BIT)
97 #define X86_CR4_DE_BIT		(3)
98 #define X86_CR4_DE		BIT(X86_CR4_DE_BIT)
99 #define X86_CR4_PSE_BIT		(4)
100 #define X86_CR4_PSE		BIT(X86_CR4_PSE_BIT)
101 #define X86_CR4_PAE_BIT		(5)
102 #define X86_CR4_PAE		BIT(X86_CR4_PAE_BIT)
103 #define X86_CR4_MCE_BIT		(6)
104 #define X86_CR4_MCE		BIT(X86_CR4_MCE_BIT)
105 #define X86_CR4_PGE_BIT		(7)
106 #define X86_CR4_PGE		BIT(X86_CR4_PGE_BIT)
107 #define X86_CR4_PCE_BIT		(8)
108 #define X86_CR4_PCE		BIT(X86_CR4_PCE_BIT)
109 #define X86_CR4_OSFXSR_BIT	(9)
110 #define X86_CR4_OSFXSR		BIT(X86_CR4_OSFXSR_BIT)
111 #define X86_CR4_OSXMMEXCPT_BIT	(10)
112 #define X86_CR4_OSXMMEXCPT	BIT(X86_CR4_OSXMMEXCPT_BIT)
113 #define X86_CR4_UMIP_BIT	(11)
114 #define X86_CR4_UMIP		BIT(X86_CR4_UMIP_BIT)
115 #define X86_CR4_LA57_BIT	(12)
116 #define X86_CR4_LA57		BIT(X86_CR4_LA57_BIT)
117 #define X86_CR4_VMXE_BIT	(13)
118 #define X86_CR4_VMXE		BIT(X86_CR4_VMXE_BIT)
119 #define X86_CR4_SMXE_BIT	(14)
120 #define X86_CR4_SMXE		BIT(X86_CR4_SMXE_BIT)
121 /* UNUSED			(15) */
122 #define X86_CR4_FSGSBASE_BIT	(16)
123 #define X86_CR4_FSGSBASE	BIT(X86_CR4_FSGSBASE_BIT)
124 #define X86_CR4_PCIDE_BIT	(17)
125 #define X86_CR4_PCIDE		BIT(X86_CR4_PCIDE_BIT)
126 #define X86_CR4_OSXSAVE_BIT	(18)
127 #define X86_CR4_OSXSAVE		BIT(X86_CR4_OSXSAVE_BIT)
128 #define X86_CR4_KL_BIT		(19)
129 #define X86_CR4_KL		BIT(X86_CR4_KL_BIT)
130 #define X86_CR4_SMEP_BIT	(20)
131 #define X86_CR4_SMEP		BIT(X86_CR4_SMEP_BIT)
132 #define X86_CR4_SMAP_BIT	(21)
133 #define X86_CR4_SMAP		BIT(X86_CR4_SMAP_BIT)
134 #define X86_CR4_PKE_BIT		(22)
135 #define X86_CR4_PKE		BIT(X86_CR4_PKE_BIT)
136 #define X86_CR4_CET_BIT		(23)
137 #define X86_CR4_CET		BIT(X86_CR4_CET_BIT)
138 #define X86_CR4_PKS_BIT		(24)
139 #define X86_CR4_PKS		BIT(X86_CR4_PKS_BIT)
140 #define X86_CR4_LAM_SUP_BIT	(28)
141 #define X86_CR4_LAM_SUP		BIT(X86_CR4_LAM_SUP_BIT)
142 
143 #define X86_EFLAGS_CF_BIT	(0)
144 #define X86_EFLAGS_CF		BIT(X86_EFLAGS_CF_BIT)
145 #define X86_EFLAGS_FIXED_BIT	(1)
146 #define X86_EFLAGS_FIXED	BIT(X86_EFLAGS_FIXED_BIT)
147 #define X86_EFLAGS_PF_BIT	(2)
148 #define X86_EFLAGS_PF		BIT(X86_EFLAGS_PF_BIT)
149 /* RESERVED 0			(3) */
150 #define X86_EFLAGS_AF_BIT	(4)
151 #define X86_EFLAGS_AF		BIT(X86_EFLAGS_AF_BIT)
152 /* RESERVED 0			(5) */
153 #define X86_EFLAGS_ZF_BIT	(6)
154 #define X86_EFLAGS_ZF		BIT(X86_EFLAGS_ZF_BIT)
155 #define X86_EFLAGS_SF_BIT	(7)
156 #define X86_EFLAGS_SF		BIT(X86_EFLAGS_SF_BIT)
157 #define X86_EFLAGS_TF_BIT	(8)
158 #define X86_EFLAGS_TF		BIT(X86_EFLAGS_TF_BIT)
159 #define X86_EFLAGS_IF_BIT	(9)
160 #define X86_EFLAGS_IF		BIT(X86_EFLAGS_IF_BIT)
161 #define X86_EFLAGS_DF_BIT	(10)
162 #define X86_EFLAGS_DF		BIT(X86_EFLAGS_DF_BIT)
163 #define X86_EFLAGS_OF_BIT	(11)
164 #define X86_EFLAGS_OF		BIT(X86_EFLAGS_OF_BIT)
165 #define X86_EFLAGS_IOPL		GENMASK(13, 12)
166 #define X86_EFLAGS_NT_BIT	(14)
167 #define X86_EFLAGS_NT		BIT(X86_EFLAGS_NT_BIT)
168 /* RESERVED 0			(15) */
169 #define X86_EFLAGS_RF_BIT	(16)
170 #define X86_EFLAGS_RF		BIT(X86_EFLAGS_RF_BIT)
171 #define X86_EFLAGS_VM_BIT	(17)
172 #define X86_EFLAGS_VM		BIT(X86_EFLAGS_VM_BIT)
173 #define X86_EFLAGS_AC_BIT	(18)
174 #define X86_EFLAGS_AC		BIT(X86_EFLAGS_AC_BIT)
175 #define X86_EFLAGS_VIF_BIT	(19)
176 #define X86_EFLAGS_VIF		BIT(X86_EFLAGS_VIF_BIT)
177 #define X86_EFLAGS_VIP_BIT	(20)
178 #define X86_EFLAGS_VIP		BIT(X86_EFLAGS_VIP_BIT)
179 #define X86_EFLAGS_ID_BIT	(21)
180 #define X86_EFLAGS_ID		BIT(X86_EFLAGS_ID_BIT)
181 
182 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \
183 			X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)
184 
185 
186 /*
187  * CPU features
188  */
189 
190 enum cpuid_output_regs {
191 	EAX,
192 	EBX,
193 	ECX,
194 	EDX
195 };
196 
197 struct cpuid { u32 a, b, c, d; };
198 
199 static inline struct cpuid raw_cpuid(u32 function, u32 index)
200 {
201 	struct cpuid r;
202 	asm volatile ("cpuid"
203 		      : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d)
204 		      : "0"(function), "2"(index));
205 	return r;
206 }
207 
208 static inline struct cpuid cpuid_indexed(u32 function, u32 index)
209 {
210 	u32 level = raw_cpuid(function & 0xf0000000, 0).a;
211 	if (level < function)
212 	return (struct cpuid) { 0, 0, 0, 0 };
213 	return raw_cpuid(function, index);
214 }
215 
216 static inline struct cpuid cpuid(u32 function)
217 {
218 	return cpuid_indexed(function, 0);
219 }
220 
221 static inline bool is_intel(void)
222 {
223 	struct cpuid c = cpuid(0);
224 	u32 name[4] = {c.b, c.d, c.c };
225 
226 	return strcmp((char *)name, "GenuineIntel") == 0;
227 }
228 
229 /*
230  * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
231  * passed by value with no overhead.
232  */
233 struct x86_cpu_feature {
234 	u32	function;
235 	u16	index;
236 	u8	reg;
237 	u8	bit;
238 };
239 
240 #define X86_CPU_FEATURE(fn, idx, gpr, __bit)					\
241 ({										\
242 	struct x86_cpu_feature feature = {					\
243 		.function = fn,							\
244 		.index = idx,							\
245 		.reg = gpr,							\
246 		.bit = __bit,							\
247 	};									\
248 										\
249 	static_assert((fn & 0xc0000000) == 0 ||					\
250 		      (fn & 0xc0000000) == 0x40000000 ||			\
251 		      (fn & 0xc0000000) == 0x80000000 ||			\
252 		      (fn & 0xc0000000) == 0xc0000000);				\
253 	static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE));	\
254 	feature;								\
255 })
256 
257 /*
258  * Basic Leafs, a.k.a. Intel defined
259  */
260 #define X86_FEATURE_MWAIT		X86_CPU_FEATURE(0x1, 0, ECX, 3)
261 #define X86_FEATURE_VMX			X86_CPU_FEATURE(0x1, 0, ECX, 5)
262 #define X86_FEATURE_PDCM		X86_CPU_FEATURE(0x1, 0, ECX, 15)
263 #define X86_FEATURE_PCID		X86_CPU_FEATURE(0x1, 0, ECX, 17)
264 #define X86_FEATURE_X2APIC		X86_CPU_FEATURE(0x1, 0, ECX, 21)
265 #define X86_FEATURE_MOVBE		X86_CPU_FEATURE(0x1, 0, ECX, 22)
266 #define X86_FEATURE_TSC_DEADLINE_TIMER	X86_CPU_FEATURE(0x1, 0, ECX, 24)
267 #define X86_FEATURE_XSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 26)
268 #define X86_FEATURE_OSXSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 27)
269 #define X86_FEATURE_RDRAND		X86_CPU_FEATURE(0x1, 0, ECX, 30)
270 #define X86_FEATURE_MCE			X86_CPU_FEATURE(0x1, 0, EDX, 7)
271 #define X86_FEATURE_APIC		X86_CPU_FEATURE(0x1, 0, EDX, 9)
272 #define X86_FEATURE_CLFLUSH		X86_CPU_FEATURE(0x1, 0, EDX, 19)
273 #define X86_FEATURE_DS			X86_CPU_FEATURE(0x1, 0, EDX, 21)
274 #define X86_FEATURE_XMM			X86_CPU_FEATURE(0x1, 0, EDX, 25)
275 #define X86_FEATURE_XMM2		X86_CPU_FEATURE(0x1, 0, EDX, 26)
276 #define X86_FEATURE_TSC_ADJUST		X86_CPU_FEATURE(0x7, 0, EBX, 1)
277 #define X86_FEATURE_HLE			X86_CPU_FEATURE(0x7, 0, EBX, 4)
278 #define X86_FEATURE_SMEP		X86_CPU_FEATURE(0x7, 0, EBX, 7)
279 #define X86_FEATURE_INVPCID		X86_CPU_FEATURE(0x7, 0, EBX, 10)
280 #define X86_FEATURE_RTM			X86_CPU_FEATURE(0x7, 0, EBX, 11)
281 #define X86_FEATURE_SMAP		X86_CPU_FEATURE(0x7, 0, EBX, 20)
282 #define X86_FEATURE_PCOMMIT		X86_CPU_FEATURE(0x7, 0, EBX, 22)
283 #define X86_FEATURE_CLFLUSHOPT		X86_CPU_FEATURE(0x7, 0, EBX, 23)
284 #define X86_FEATURE_CLWB		X86_CPU_FEATURE(0x7, 0, EBX, 24)
285 #define X86_FEATURE_INTEL_PT		X86_CPU_FEATURE(0x7, 0, EBX, 25)
286 #define X86_FEATURE_UMIP		X86_CPU_FEATURE(0x7, 0, ECX, 2)
287 #define X86_FEATURE_PKU			X86_CPU_FEATURE(0x7, 0, ECX, 3)
288 #define X86_FEATURE_LA57		X86_CPU_FEATURE(0x7, 0, ECX, 16)
289 #define X86_FEATURE_RDPID		X86_CPU_FEATURE(0x7, 0, ECX, 22)
290 #define X86_FEATURE_SHSTK		X86_CPU_FEATURE(0x7, 0, ECX, 7)
291 #define X86_FEATURE_IBT			X86_CPU_FEATURE(0x7, 0, EDX, 20)
292 #define X86_FEATURE_SPEC_CTRL		X86_CPU_FEATURE(0x7, 0, EDX, 26)
293 #define X86_FEATURE_FLUSH_L1D		X86_CPU_FEATURE(0x7, 0, EDX, 28)
294 #define X86_FEATURE_ARCH_CAPABILITIES	X86_CPU_FEATURE(0x7, 0, EDX, 29)
295 #define X86_FEATURE_PKS			X86_CPU_FEATURE(0x7, 0, ECX, 31)
296 #define X86_FEATURE_LAM			X86_CPU_FEATURE(0x7, 1, EAX, 26)
297 
298 /*
299  * KVM defined leafs
300  */
301 #define KVM_FEATURE_ASYNC_PF		X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
302 #define KVM_FEATURE_ASYNC_PF_INT	X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
303 
304 /*
305  * Extended Leafs, a.k.a. AMD defined
306  */
307 #define X86_FEATURE_SVM			X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
308 #define X86_FEATURE_PERFCTR_CORE	X86_CPU_FEATURE(0x80000001, 0, ECX, 23)
309 #define X86_FEATURE_NX			X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
310 #define X86_FEATURE_GBPAGES		X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
311 #define X86_FEATURE_RDTSCP		X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
312 #define X86_FEATURE_LM			X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
313 #define X86_FEATURE_RDPRU		X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
314 #define X86_FEATURE_AMD_IBPB		X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
315 #define X86_FEATURE_NPT			X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
316 #define X86_FEATURE_LBRV		X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
317 #define X86_FEATURE_NRIPS		X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
318 #define X86_FEATURE_TSCRATEMSR		X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
319 #define X86_FEATURE_PAUSEFILTER		X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
320 #define X86_FEATURE_PFTHRESHOLD		X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
321 #define X86_FEATURE_VGIF		X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
322 #define X86_FEATURE_VNMI		X86_CPU_FEATURE(0x8000000A, 0, EDX, 25)
323 #define X86_FEATURE_AMD_PMU_V2		X86_CPU_FEATURE(0x80000022, 0, EAX, 0)
324 
325 /*
326  * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit
327  * value/property as opposed to a single-bit feature.  Again, pack the info
328  * into a 64-bit value to pass by value with no overhead on 64-bit builds.
329  */
330 struct x86_cpu_property {
331 	u32	function;
332 	u8	index;
333 	u8	reg;
334 	u8	lo_bit;
335 	u8	hi_bit;
336 };
337 #define X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit)			\
338 ({										\
339 	struct x86_cpu_property property = {					\
340 		.function = fn,							\
341 		.index = idx,							\
342 		.reg = gpr,							\
343 		.lo_bit = low_bit,						\
344 		.hi_bit = high_bit,						\
345 	};									\
346 										\
347 	static_assert(low_bit < high_bit);					\
348 	static_assert((fn & 0xc0000000) == 0 ||					\
349 		      (fn & 0xc0000000) == 0x40000000 ||			\
350 		      (fn & 0xc0000000) == 0x80000000 ||			\
351 		      (fn & 0xc0000000) == 0xc0000000);				\
352 	static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE));	\
353 	property;								\
354 })
355 
356 #define X86_PROPERTY_MAX_BASIC_LEAF		X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
357 #define X86_PROPERTY_PMU_VERSION		X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
358 #define X86_PROPERTY_PMU_NR_GP_COUNTERS		X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15)
359 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH	X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23)
360 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH	X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31)
361 #define X86_PROPERTY_PMU_EVENTS_MASK		X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7)
362 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK	X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31)
363 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS	X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4)
364 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH	X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12)
365 
366 #define X86_PROPERTY_SUPPORTED_XCR0_LO		X86_CPU_PROPERTY(0xd,  0, EAX,  0, 31)
367 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0	X86_CPU_PROPERTY(0xd,  0, EBX,  0, 31)
368 #define X86_PROPERTY_XSTATE_MAX_SIZE		X86_CPU_PROPERTY(0xd,  0, ECX,  0, 31)
369 #define X86_PROPERTY_SUPPORTED_XCR0_HI		X86_CPU_PROPERTY(0xd,  0, EDX,  0, 31)
370 
371 #define X86_PROPERTY_XSTATE_TILE_SIZE		X86_CPU_PROPERTY(0xd, 18, EAX,  0, 31)
372 #define X86_PROPERTY_XSTATE_TILE_OFFSET		X86_CPU_PROPERTY(0xd, 18, EBX,  0, 31)
373 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES	X86_CPU_PROPERTY(0x1d, 0, EAX,  0, 31)
374 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES	X86_CPU_PROPERTY(0x1d, 1, EAX,  0, 15)
375 #define X86_PROPERTY_AMX_BYTES_PER_TILE		X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
376 #define X86_PROPERTY_AMX_BYTES_PER_ROW		X86_CPU_PROPERTY(0x1d, 1, EBX, 0,  15)
377 #define X86_PROPERTY_AMX_NR_TILE_REGS		X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
378 #define X86_PROPERTY_AMX_MAX_ROWS		X86_CPU_PROPERTY(0x1d, 1, ECX, 0,  15)
379 
380 #define X86_PROPERTY_MAX_KVM_LEAF		X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)
381 
382 #define X86_PROPERTY_MAX_EXT_LEAF		X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31)
383 #define X86_PROPERTY_MAX_PHY_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7)
384 #define X86_PROPERTY_MAX_VIRT_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15)
385 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23)
386 #define X86_PROPERTY_SEV_C_BIT			X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5)
387 #define X86_PROPERTY_PHYS_ADDR_REDUCTION	X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
388 #define X86_PROPERTY_NR_PERFCTR_CORE		X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3)
389 #define X86_PROPERTY_NR_PERFCTR_NB		X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15)
390 
391 #define X86_PROPERTY_MAX_CENTAUR_LEAF		X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
392 
393 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi)
394 {
395 	union {
396 		struct cpuid cpuid;
397 		u32 gprs[4];
398 	} c;
399 
400 	c.cpuid = cpuid_indexed(function, index);
401 
402 	return (c.gprs[reg] & GENMASK(hi, lo)) >> lo;
403 }
404 
405 static inline bool this_cpu_has(struct x86_cpu_feature feature)
406 {
407 	return __this_cpu_has(feature.function, feature.index,
408 			      feature.reg, feature.bit, feature.bit);
409 }
410 
411 static inline uint32_t this_cpu_property(struct x86_cpu_property property)
412 {
413 	return __this_cpu_has(property.function, property.index,
414 			      property.reg, property.lo_bit, property.hi_bit);
415 }
416 
417 static __always_inline bool this_cpu_has_p(struct x86_cpu_property property)
418 {
419 	uint32_t max_leaf;
420 
421 	switch (property.function & 0xc0000000) {
422 	case 0:
423 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
424 		break;
425 	case 0x40000000:
426 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
427 		break;
428 	case 0x80000000:
429 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
430 		break;
431 	case 0xc0000000:
432 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
433 	}
434 	return max_leaf >= property.function;
435 }
436 
437 static inline u8 cpuid_maxphyaddr(void)
438 {
439 	if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR))
440 		return 36;
441 
442 	return this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR);
443 }
444 
445 struct far_pointer32 {
446 	u32 offset;
447 	u16 selector;
448 } __attribute__((packed));
449 
450 struct descriptor_table_ptr {
451 	u16 limit;
452 	ulong base;
453 } __attribute__((packed));
454 
455 static inline void clac(void)
456 {
457 	asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory");
458 }
459 
460 static inline void stac(void)
461 {
462 	asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory");
463 }
464 
465 static inline u16 read_cs(void)
466 {
467 	unsigned val;
468 
469 	asm volatile ("mov %%cs, %0" : "=mr"(val));
470 	return val;
471 }
472 
473 static inline u16 read_ds(void)
474 {
475 	unsigned val;
476 
477 	asm volatile ("mov %%ds, %0" : "=mr"(val));
478 	return val;
479 }
480 
481 static inline u16 read_es(void)
482 {
483 	unsigned val;
484 
485 	asm volatile ("mov %%es, %0" : "=mr"(val));
486 	return val;
487 }
488 
489 static inline u16 read_ss(void)
490 {
491 	unsigned val;
492 
493 	asm volatile ("mov %%ss, %0" : "=mr"(val));
494 	return val;
495 }
496 
497 static inline u16 read_fs(void)
498 {
499 	unsigned val;
500 
501 	asm volatile ("mov %%fs, %0" : "=mr"(val));
502 	return val;
503 }
504 
505 static inline u16 read_gs(void)
506 {
507 	unsigned val;
508 
509 	asm volatile ("mov %%gs, %0" : "=mr"(val));
510 	return val;
511 }
512 
513 static inline unsigned long read_rflags(void)
514 {
515 	unsigned long f;
516 	asm volatile ("pushf; pop %0\n\t" : "=rm"(f));
517 	return f;
518 }
519 
520 static inline void write_ds(unsigned val)
521 {
522 	asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory");
523 }
524 
525 static inline void write_es(unsigned val)
526 {
527 	asm volatile ("mov %0, %%es" : : "rm"(val) : "memory");
528 }
529 
530 static inline void write_ss(unsigned val)
531 {
532 	asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory");
533 }
534 
535 static inline void write_fs(unsigned val)
536 {
537 	asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory");
538 }
539 
540 static inline void write_gs(unsigned val)
541 {
542 	asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory");
543 }
544 
545 static inline void write_rflags(unsigned long f)
546 {
547 	asm volatile ("push %0; popf\n\t" : : "rm"(f));
548 }
549 
550 static inline void set_iopl(int iopl)
551 {
552 	unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL;
553 	flags |= iopl * (X86_EFLAGS_IOPL / 3);
554 	write_rflags(flags);
555 }
556 
557 /*
558  * Don't use the safe variants for rdmsr() or wrmsr().  The exception fixup
559  * infrastructure uses per-CPU data and thus consumes GS.base.  Various tests
560  * temporarily modify MSR_GS_BASE and will explode when trying to determine
561  * whether or not RDMSR/WRMSR faulted.
562  */
563 static inline u64 rdmsr(u32 index)
564 {
565 	u32 a, d;
566 	asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory");
567 	return a | ((u64)d << 32);
568 }
569 
570 static inline void wrmsr(u32 index, u64 val)
571 {
572 	u32 a = val, d = val >> 32;
573 	asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory");
574 }
575 
576 #define __rdreg64_safe(fep, insn, index, val)				\
577 ({									\
578 	uint32_t a, d;							\
579 	int vector;							\
580 									\
581 	vector = __asm_safe_out2(fep, insn, "=a"(a), "=d"(d), "c"(index));\
582 									\
583 	if (vector)							\
584 		*(val) = 0;						\
585 	else								\
586 		*(val) = (uint64_t)a | ((uint64_t)d << 32);		\
587 	vector;								\
588 })
589 
590 #define rdreg64_safe(insn, index, val)					\
591 	__rdreg64_safe("", insn, index, val)
592 
593 #define __wrreg64_safe(fep, insn, index, val)				\
594 ({									\
595 	uint32_t eax = (val), edx = (val) >> 32;			\
596 									\
597 	__asm_safe(fep, insn, "a" (eax), "d" (edx), "c" (index));	\
598 })
599 
600 #define wrreg64_safe(insn, index, val)					\
601 	__wrreg64_safe("", insn, index, val)
602 
603 static inline int rdmsr_safe(u32 index, uint64_t *val)
604 {
605 	return rdreg64_safe("rdmsr", index, val);
606 }
607 
608 static inline int rdmsr_fep_safe(u32 index, uint64_t *val)
609 {
610 	return __rdreg64_safe(KVM_FEP, "rdmsr", index, val);
611 }
612 
613 static inline int wrmsr_safe(u32 index, u64 val)
614 {
615 	return wrreg64_safe("wrmsr", index, val);
616 }
617 
618 static inline int wrmsr_fep_safe(u32 index, u64 val)
619 {
620 	return __wrreg64_safe(KVM_FEP, "wrmsr", index, val);
621 }
622 
623 static inline int rdpmc_safe(u32 index, uint64_t *val)
624 {
625 	return rdreg64_safe("rdpmc", index, val);
626 }
627 
628 static inline uint64_t rdpmc(uint32_t index)
629 {
630 	uint64_t val;
631 	int vector = rdpmc_safe(index, &val);
632 
633 	assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")",
634 		   exception_mnemonic(vector), index);
635 	return val;
636 }
637 
638 static inline int xgetbv_safe(u32 index, u64 *result)
639 {
640 	return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result);
641 }
642 
643 static inline int xsetbv_safe(u32 index, u64 value)
644 {
645 	return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value);
646 }
647 
648 static inline int write_cr0_safe(ulong val)
649 {
650 	return asm_safe("mov %0,%%cr0", "r" (val));
651 }
652 
653 static inline void write_cr0(ulong val)
654 {
655 	int vector = write_cr0_safe(val);
656 
657 	assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx",
658 		   vector, val);
659 }
660 
661 static inline ulong read_cr0(void)
662 {
663 	ulong val;
664 	asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory");
665 	return val;
666 }
667 
668 static inline void write_cr2(ulong val)
669 {
670 	asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory");
671 }
672 
673 static inline ulong read_cr2(void)
674 {
675 	ulong val;
676 	asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory");
677 	return val;
678 }
679 
680 static inline int write_cr3_safe(ulong val)
681 {
682 	return asm_safe("mov %0,%%cr3", "r" (val));
683 }
684 
685 static inline void write_cr3(ulong val)
686 {
687 	int vector = write_cr3_safe(val);
688 
689 	assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx",
690 		   vector, val);
691 }
692 
693 static inline ulong read_cr3(void)
694 {
695 	ulong val;
696 	asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory");
697 	return val;
698 }
699 
700 static inline void update_cr3(void *cr3)
701 {
702 	write_cr3((ulong)cr3);
703 }
704 
705 static inline int write_cr4_safe(ulong val)
706 {
707 	return asm_safe("mov %0,%%cr4", "r" (val));
708 }
709 
710 static inline void write_cr4(ulong val)
711 {
712 	int vector = write_cr4_safe(val);
713 
714 	assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx",
715 		   vector, val);
716 }
717 
718 static inline ulong read_cr4(void)
719 {
720 	ulong val;
721 	asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory");
722 	return val;
723 }
724 
725 static inline void write_cr8(ulong val)
726 {
727 	asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory");
728 }
729 
730 static inline ulong read_cr8(void)
731 {
732 	ulong val;
733 	asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory");
734 	return val;
735 }
736 
737 static inline void lgdt(const struct descriptor_table_ptr *ptr)
738 {
739 	asm volatile ("lgdt %0" : : "m"(*ptr));
740 }
741 
742 static inline int lgdt_safe(const struct descriptor_table_ptr *ptr)
743 {
744 	return asm_safe("lgdt %0", "m"(*ptr));
745 }
746 
747 static inline int lgdt_fep_safe(const struct descriptor_table_ptr *ptr)
748 {
749 	return asm_fep_safe("lgdt %0", "m"(*ptr));
750 }
751 
752 static inline void sgdt(struct descriptor_table_ptr *ptr)
753 {
754 	asm volatile ("sgdt %0" : "=m"(*ptr));
755 }
756 
757 static inline void lidt(const struct descriptor_table_ptr *ptr)
758 {
759 	asm volatile ("lidt %0" : : "m"(*ptr));
760 }
761 
762 static inline int lidt_safe(const struct descriptor_table_ptr *ptr)
763 {
764 	return asm_safe("lidt %0", "m"(*ptr));
765 }
766 
767 static inline int lidt_fep_safe(const struct descriptor_table_ptr *ptr)
768 {
769 	return asm_fep_safe("lidt %0", "m"(*ptr));
770 }
771 
772 static inline void sidt(struct descriptor_table_ptr *ptr)
773 {
774 	asm volatile ("sidt %0" : "=m"(*ptr));
775 }
776 
777 static inline void lldt(u16 val)
778 {
779 	asm volatile ("lldt %0" : : "rm"(val));
780 }
781 
782 static inline int lldt_safe(u16 val)
783 {
784 	return asm_safe("lldt %0", "rm"(val));
785 }
786 
787 static inline int lldt_fep_safe(u16 val)
788 {
789 	return asm_safe("lldt %0", "rm"(val));
790 }
791 
792 static inline u16 sldt(void)
793 {
794 	u16 val;
795 	asm volatile ("sldt %0" : "=rm"(val));
796 	return val;
797 }
798 
799 static inline void ltr(u16 val)
800 {
801 	asm volatile ("ltr %0" : : "rm"(val));
802 }
803 
804 static inline int ltr_safe(u16 val)
805 {
806 	return asm_safe("ltr %0", "rm"(val));
807 }
808 
809 static inline int ltr_fep_safe(u16 val)
810 {
811 	return asm_safe("ltr %0", "rm"(val));
812 }
813 
814 static inline u16 str(void)
815 {
816 	u16 val;
817 	asm volatile ("str %0" : "=rm"(val));
818 	return val;
819 }
820 
821 static inline void write_dr0(void *val)
822 {
823 	asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory");
824 }
825 
826 static inline void write_dr1(void *val)
827 {
828 	asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory");
829 }
830 
831 static inline void write_dr2(void *val)
832 {
833 	asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory");
834 }
835 
836 static inline void write_dr3(void *val)
837 {
838 	asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory");
839 }
840 
841 static inline void write_dr6(ulong val)
842 {
843 	asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory");
844 }
845 
846 static inline ulong read_dr6(void)
847 {
848 	ulong val;
849 	asm volatile ("mov %%dr6, %0" : "=r"(val));
850 	return val;
851 }
852 
853 static inline void write_dr7(ulong val)
854 {
855 	asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory");
856 }
857 
858 static inline ulong read_dr7(void)
859 {
860 	ulong val;
861 	asm volatile ("mov %%dr7, %0" : "=r"(val));
862 	return val;
863 }
864 
865 static inline void pause(void)
866 {
867 	asm volatile ("pause");
868 }
869 
870 static inline void cli(void)
871 {
872 	asm volatile ("cli");
873 }
874 
875 /*
876  * See also safe_halt().
877  */
878 static inline void sti(void)
879 {
880 	asm volatile ("sti");
881 }
882 
883 /*
884  * Enable interrupts and ensure that interrupts are evaluated upon return from
885  * this function, i.e. execute a nop to consume the STi interrupt shadow.
886  */
887 static inline void sti_nop(void)
888 {
889 	asm volatile ("sti; nop");
890 }
891 
892 /*
893  * Enable interrupts for one instruction (nop), to allow the CPU to process all
894  * interrupts that are already pending.
895  */
896 static inline void sti_nop_cli(void)
897 {
898 	asm volatile ("sti; nop; cli");
899 }
900 
901 static inline unsigned long long rdrand(void)
902 {
903 	long long r;
904 
905 	asm volatile("rdrand %0\n\t"
906 		     "jc 1f\n\t"
907 		     "mov $0, %0\n\t"
908 		     "1:\n\t" : "=r" (r));
909 	return r;
910 }
911 
912 static inline unsigned long long rdtsc(void)
913 {
914 	long long r;
915 
916 #ifdef __x86_64__
917 	unsigned a, d;
918 
919 	asm volatile ("rdtsc" : "=a"(a), "=d"(d));
920 	r = a | ((long long)d << 32);
921 #else
922 	asm volatile ("rdtsc" : "=A"(r));
923 #endif
924 	return r;
925 }
926 
927 /*
928  * Per the advice in the SDM, volume 2, the sequence "mfence; lfence"
929  * executed immediately before rdtsc ensures that rdtsc will be
930  * executed only after all previous instructions have executed and all
931  * previous loads and stores are globally visible. In addition, the
932  * lfence immediately after rdtsc ensures that rdtsc will be executed
933  * prior to the execution of any subsequent instruction.
934  */
935 static inline unsigned long long fenced_rdtsc(void)
936 {
937 	unsigned long long tsc;
938 
939 #ifdef __x86_64__
940 	unsigned int eax, edx;
941 
942 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
943 	tsc = eax | ((unsigned long long)edx << 32);
944 #else
945 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc));
946 #endif
947 	return tsc;
948 }
949 
950 static inline unsigned long long rdtscp(u32 *aux)
951 {
952 	long long r;
953 
954 #ifdef __x86_64__
955 	unsigned a, d;
956 
957 	asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux));
958 	r = a | ((long long)d << 32);
959 #else
960 	asm volatile ("rdtscp" : "=A"(r), "=c"(*aux));
961 #endif
962 	return r;
963 }
964 
965 static inline void wrtsc(u64 tsc)
966 {
967 	wrmsr(MSR_IA32_TSC, tsc);
968 }
969 
970 
971 static inline void invlpg(volatile void *va)
972 {
973 	asm volatile("invlpg (%0)" ::"r" (va) : "memory");
974 }
975 
976 struct invpcid_desc {
977 	u64 pcid : 12;
978 	u64 rsv  : 52;
979 	u64 addr : 64;
980 };
981 
982 static inline int invpcid_safe(unsigned long type, struct invpcid_desc *desc)
983 {
984 	/* invpcid (%rax), %rbx */
985 	return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type));
986 }
987 
988 /*
989  * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's
990  * intended to be a wake event arrives *after* HLT is executed.  Modern CPUs,
991  * except for a few oddballs that KVM is unlikely to run on, block IRQs for one
992  * instruction after STI, *if* RFLAGS.IF=0 before STI.  Note, Intel CPUs may
993  * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too.
994  */
995 static inline void safe_halt(void)
996 {
997 	asm volatile("sti; hlt");
998 }
999 
1000 static inline u32 read_pkru(void)
1001 {
1002 	unsigned int eax, edx;
1003 	unsigned int ecx = 0;
1004 	unsigned int pkru;
1005 
1006 	asm volatile(".byte 0x0f,0x01,0xee\n\t"
1007 		     : "=a" (eax), "=d" (edx)
1008 		     : "c" (ecx));
1009 	pkru = eax;
1010 	return pkru;
1011 }
1012 
1013 static inline void write_pkru(u32 pkru)
1014 {
1015 	unsigned int eax = pkru;
1016 	unsigned int ecx = 0;
1017 	unsigned int edx = 0;
1018 
1019 	asm volatile(".byte 0x0f,0x01,0xef\n\t"
1020 		     : : "a" (eax), "c" (ecx), "d" (edx));
1021 }
1022 
1023 static inline bool is_canonical(u64 addr)
1024 {
1025 	int va_width, shift_amt;
1026 
1027 	if (this_cpu_has_p(X86_PROPERTY_MAX_VIRT_ADDR))
1028 		va_width = this_cpu_property(X86_PROPERTY_MAX_VIRT_ADDR);
1029 	else
1030 		va_width = 48;
1031 
1032 	shift_amt = 64 - va_width;
1033 	return (s64)(addr << shift_amt) >> shift_amt == addr;
1034 }
1035 
1036 static inline void flush_tlb(void)
1037 {
1038 	ulong cr4;
1039 
1040 	cr4 = read_cr4();
1041 	write_cr4(cr4 ^ X86_CR4_PGE);
1042 	write_cr4(cr4);
1043 }
1044 
1045 static inline void generate_non_canonical_gp(void)
1046 {
1047 	*(volatile u64 *)NONCANONICAL = 0;
1048 }
1049 
1050 static inline void generate_ud(void)
1051 {
1052 	asm volatile ("ud2");
1053 }
1054 
1055 static inline void generate_de(void)
1056 {
1057 	asm volatile (
1058 		"xor %%eax, %%eax\n\t"
1059 		"xor %%ebx, %%ebx\n\t"
1060 		"xor %%edx, %%edx\n\t"
1061 		"idiv %%ebx\n\t"
1062 		::: "eax", "ebx", "edx");
1063 }
1064 
1065 static inline void generate_bp(void)
1066 {
1067 	asm volatile ("int3");
1068 }
1069 
1070 static inline void generate_single_step_db(void)
1071 {
1072 	write_rflags(read_rflags() | X86_EFLAGS_TF);
1073 	asm volatile("nop");
1074 }
1075 
1076 static inline uint64_t generate_usermode_ac(void)
1077 {
1078 	/*
1079 	 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address.
1080 	 * Disclaimer: It is assumed that the stack pointer is aligned
1081 	 * on a 16-byte boundary as x86_64 stacks should be.
1082 	 */
1083 	asm volatile("movq $0, -0x4(%rsp)");
1084 
1085 	return 0;
1086 }
1087 
1088 /*
1089  * Switch from 64-bit to 32-bit mode and generate #OF via INTO.  Note, if RIP
1090  * or RSP holds a 64-bit value, this helper will NOT generate #OF.
1091  */
1092 static inline void generate_of(void)
1093 {
1094 	struct far_pointer32 fp = {
1095 		.offset = (uintptr_t)&&into,
1096 		.selector = KERNEL_CS32,
1097 	};
1098 	uintptr_t rsp;
1099 
1100 	asm volatile ("mov %%rsp, %0" : "=r"(rsp));
1101 
1102 	if (fp.offset != (uintptr_t)&&into) {
1103 		printf("Code address too high.\n");
1104 		return;
1105 	}
1106 	if ((u32)rsp != rsp) {
1107 		printf("Stack address too high.\n");
1108 		return;
1109 	}
1110 
1111 	asm goto ("lcall *%0" : : "m" (fp) : "rax" : into);
1112 	return;
1113 into:
1114 	asm volatile (".code32;"
1115 		      "movl $0x7fffffff, %eax;"
1116 		      "addl %eax, %eax;"
1117 		      "into;"
1118 		      "lret;"
1119 		      ".code64");
1120 	__builtin_unreachable();
1121 }
1122 
1123 static inline void fnop(void)
1124 {
1125 	asm volatile("fnop");
1126 }
1127 
1128 /* If CR0.TS is set in L2, #NM is generated. */
1129 static inline void generate_cr0_ts_nm(void)
1130 {
1131 	write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS);
1132 	fnop();
1133 }
1134 
1135 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */
1136 static inline void generate_cr0_em_nm(void)
1137 {
1138 	write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM);
1139 	fnop();
1140 }
1141 
1142 static inline bool is_la57_enabled(void)
1143 {
1144 	return !!(read_cr4() & X86_CR4_LA57);
1145 }
1146 
1147 static inline bool is_lam_sup_enabled(void)
1148 {
1149 	return !!(read_cr4() & X86_CR4_LAM_SUP);
1150 }
1151 
1152 static inline bool is_lam_u48_enabled(void)
1153 {
1154 	return (read_cr3() & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)) == X86_CR3_LAM_U48;
1155 }
1156 
1157 static inline bool is_lam_u57_enabled(void)
1158 {
1159 	return !!(read_cr3() & X86_CR3_LAM_U57);
1160 }
1161 
1162 #endif
1163