xref: /kvm-unit-tests/lib/x86/processor.h (revision 5cd94b1b09aad2ae3cfddb40b4a148ebecb498bd)
1 #ifndef _X86_PROCESSOR_H_
2 #define _X86_PROCESSOR_H_
3 
4 #include "libcflat.h"
5 #include "desc.h"
6 #include "msr.h"
7 #include <bitops.h>
8 #include <stdint.h>
9 #include <util.h>
10 
11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull
12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull
13 #define NONCANONICAL	 0xaaaaaaaaaaaaaaaaull
14 
15 #define LAM57_MASK	GENMASK_ULL(62, 57)
16 #define LAM48_MASK	GENMASK_ULL(62, 48)
17 
18 /*
19  * Get a linear address by combining @addr with a non-canonical pattern in the
20  * @mask bits.
21  */
22 static inline u64 get_non_canonical(u64 addr, u64 mask)
23 {
24 	return (addr & ~mask) | (NONCANONICAL & mask);
25 }
26 
27 #ifdef __x86_64__
28 #  define R "r"
29 #  define W "q"
30 #  define S "8"
31 #else
32 #  define R "e"
33 #  define W "l"
34 #  define S "4"
35 #endif
36 
37 #define DE_VECTOR 0
38 #define DB_VECTOR 1
39 #define NMI_VECTOR 2
40 #define BP_VECTOR 3
41 #define OF_VECTOR 4
42 #define BR_VECTOR 5
43 #define UD_VECTOR 6
44 #define NM_VECTOR 7
45 #define DF_VECTOR 8
46 #define TS_VECTOR 10
47 #define NP_VECTOR 11
48 #define SS_VECTOR 12
49 #define GP_VECTOR 13
50 #define PF_VECTOR 14
51 #define MF_VECTOR 16
52 #define AC_VECTOR 17
53 #define MC_VECTOR 18
54 #define XM_VECTOR 19
55 #define XF_VECTOR XM_VECTOR /* AMD */
56 #define VE_VECTOR 20 /* Intel only */
57 #define CP_VECTOR 21
58 #define HV_VECTOR 28 /* AMD only */
59 #define VC_VECTOR 29 /* AMD only */
60 #define SX_VECTOR 30 /* AMD only */
61 
62 #define X86_CR0_PE_BIT		(0)
63 #define X86_CR0_PE		BIT(X86_CR0_PE_BIT)
64 #define X86_CR0_MP_BIT		(1)
65 #define X86_CR0_MP		BIT(X86_CR0_MP_BIT)
66 #define X86_CR0_EM_BIT		(2)
67 #define X86_CR0_EM		BIT(X86_CR0_EM_BIT)
68 #define X86_CR0_TS_BIT		(3)
69 #define X86_CR0_TS		BIT(X86_CR0_TS_BIT)
70 #define X86_CR0_ET_BIT		(4)
71 #define X86_CR0_ET		BIT(X86_CR0_ET_BIT)
72 #define X86_CR0_NE_BIT		(5)
73 #define X86_CR0_NE		BIT(X86_CR0_NE_BIT)
74 #define X86_CR0_WP_BIT		(16)
75 #define X86_CR0_WP		BIT(X86_CR0_WP_BIT)
76 #define X86_CR0_AM_BIT		(18)
77 #define X86_CR0_AM		BIT(X86_CR0_AM_BIT)
78 #define X86_CR0_NW_BIT		(29)
79 #define X86_CR0_NW		BIT(X86_CR0_NW_BIT)
80 #define X86_CR0_CD_BIT		(30)
81 #define X86_CR0_CD		BIT(X86_CR0_CD_BIT)
82 #define X86_CR0_PG_BIT		(31)
83 #define X86_CR0_PG		BIT(X86_CR0_PG_BIT)
84 
85 #define X86_CR3_PCID_MASK	GENMASK(11, 0)
86 #define X86_CR3_LAM_U57_BIT	(61)
87 #define X86_CR3_LAM_U57		BIT_ULL(X86_CR3_LAM_U57_BIT)
88 #define X86_CR3_LAM_U48_BIT	(62)
89 #define X86_CR3_LAM_U48		BIT_ULL(X86_CR3_LAM_U48_BIT)
90 
91 #define X86_CR4_VME_BIT		(0)
92 #define X86_CR4_VME		BIT(X86_CR4_VME_BIT)
93 #define X86_CR4_PVI_BIT		(1)
94 #define X86_CR4_PVI		BIT(X86_CR4_PVI_BIT)
95 #define X86_CR4_TSD_BIT		(2)
96 #define X86_CR4_TSD		BIT(X86_CR4_TSD_BIT)
97 #define X86_CR4_DE_BIT		(3)
98 #define X86_CR4_DE		BIT(X86_CR4_DE_BIT)
99 #define X86_CR4_PSE_BIT		(4)
100 #define X86_CR4_PSE		BIT(X86_CR4_PSE_BIT)
101 #define X86_CR4_PAE_BIT		(5)
102 #define X86_CR4_PAE		BIT(X86_CR4_PAE_BIT)
103 #define X86_CR4_MCE_BIT		(6)
104 #define X86_CR4_MCE		BIT(X86_CR4_MCE_BIT)
105 #define X86_CR4_PGE_BIT		(7)
106 #define X86_CR4_PGE		BIT(X86_CR4_PGE_BIT)
107 #define X86_CR4_PCE_BIT		(8)
108 #define X86_CR4_PCE		BIT(X86_CR4_PCE_BIT)
109 #define X86_CR4_OSFXSR_BIT	(9)
110 #define X86_CR4_OSFXSR		BIT(X86_CR4_OSFXSR_BIT)
111 #define X86_CR4_OSXMMEXCPT_BIT	(10)
112 #define X86_CR4_OSXMMEXCPT	BIT(X86_CR4_OSXMMEXCPT_BIT)
113 #define X86_CR4_UMIP_BIT	(11)
114 #define X86_CR4_UMIP		BIT(X86_CR4_UMIP_BIT)
115 #define X86_CR4_LA57_BIT	(12)
116 #define X86_CR4_LA57		BIT(X86_CR4_LA57_BIT)
117 #define X86_CR4_VMXE_BIT	(13)
118 #define X86_CR4_VMXE		BIT(X86_CR4_VMXE_BIT)
119 #define X86_CR4_SMXE_BIT	(14)
120 #define X86_CR4_SMXE		BIT(X86_CR4_SMXE_BIT)
121 /* UNUSED			(15) */
122 #define X86_CR4_FSGSBASE_BIT	(16)
123 #define X86_CR4_FSGSBASE	BIT(X86_CR4_FSGSBASE_BIT)
124 #define X86_CR4_PCIDE_BIT	(17)
125 #define X86_CR4_PCIDE		BIT(X86_CR4_PCIDE_BIT)
126 #define X86_CR4_OSXSAVE_BIT	(18)
127 #define X86_CR4_OSXSAVE		BIT(X86_CR4_OSXSAVE_BIT)
128 #define X86_CR4_KL_BIT		(19)
129 #define X86_CR4_KL		BIT(X86_CR4_KL_BIT)
130 #define X86_CR4_SMEP_BIT	(20)
131 #define X86_CR4_SMEP		BIT(X86_CR4_SMEP_BIT)
132 #define X86_CR4_SMAP_BIT	(21)
133 #define X86_CR4_SMAP		BIT(X86_CR4_SMAP_BIT)
134 #define X86_CR4_PKE_BIT		(22)
135 #define X86_CR4_PKE		BIT(X86_CR4_PKE_BIT)
136 #define X86_CR4_CET_BIT		(23)
137 #define X86_CR4_CET		BIT(X86_CR4_CET_BIT)
138 #define X86_CR4_PKS_BIT		(24)
139 #define X86_CR4_PKS		BIT(X86_CR4_PKS_BIT)
140 #define X86_CR4_LAM_SUP_BIT	(28)
141 #define X86_CR4_LAM_SUP		BIT(X86_CR4_LAM_SUP_BIT)
142 
143 #define X86_EFLAGS_CF_BIT	(0)
144 #define X86_EFLAGS_CF		BIT(X86_EFLAGS_CF_BIT)
145 #define X86_EFLAGS_FIXED_BIT	(1)
146 #define X86_EFLAGS_FIXED	BIT(X86_EFLAGS_FIXED_BIT)
147 #define X86_EFLAGS_PF_BIT	(2)
148 #define X86_EFLAGS_PF		BIT(X86_EFLAGS_PF_BIT)
149 /* RESERVED 0			(3) */
150 #define X86_EFLAGS_AF_BIT	(4)
151 #define X86_EFLAGS_AF		BIT(X86_EFLAGS_AF_BIT)
152 /* RESERVED 0			(5) */
153 #define X86_EFLAGS_ZF_BIT	(6)
154 #define X86_EFLAGS_ZF		BIT(X86_EFLAGS_ZF_BIT)
155 #define X86_EFLAGS_SF_BIT	(7)
156 #define X86_EFLAGS_SF		BIT(X86_EFLAGS_SF_BIT)
157 #define X86_EFLAGS_TF_BIT	(8)
158 #define X86_EFLAGS_TF		BIT(X86_EFLAGS_TF_BIT)
159 #define X86_EFLAGS_IF_BIT	(9)
160 #define X86_EFLAGS_IF		BIT(X86_EFLAGS_IF_BIT)
161 #define X86_EFLAGS_DF_BIT	(10)
162 #define X86_EFLAGS_DF		BIT(X86_EFLAGS_DF_BIT)
163 #define X86_EFLAGS_OF_BIT	(11)
164 #define X86_EFLAGS_OF		BIT(X86_EFLAGS_OF_BIT)
165 #define X86_EFLAGS_IOPL		GENMASK(13, 12)
166 #define X86_EFLAGS_NT_BIT	(14)
167 #define X86_EFLAGS_NT		BIT(X86_EFLAGS_NT_BIT)
168 /* RESERVED 0			(15) */
169 #define X86_EFLAGS_RF_BIT	(16)
170 #define X86_EFLAGS_RF		BIT(X86_EFLAGS_RF_BIT)
171 #define X86_EFLAGS_VM_BIT	(17)
172 #define X86_EFLAGS_VM		BIT(X86_EFLAGS_VM_BIT)
173 #define X86_EFLAGS_AC_BIT	(18)
174 #define X86_EFLAGS_AC		BIT(X86_EFLAGS_AC_BIT)
175 #define X86_EFLAGS_VIF_BIT	(19)
176 #define X86_EFLAGS_VIF		BIT(X86_EFLAGS_VIF_BIT)
177 #define X86_EFLAGS_VIP_BIT	(20)
178 #define X86_EFLAGS_VIP		BIT(X86_EFLAGS_VIP_BIT)
179 #define X86_EFLAGS_ID_BIT	(21)
180 #define X86_EFLAGS_ID		BIT(X86_EFLAGS_ID_BIT)
181 
182 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \
183 			X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)
184 
185 
186 /*
187  * CPU features
188  */
189 
190 enum cpuid_output_regs {
191 	EAX,
192 	EBX,
193 	ECX,
194 	EDX
195 };
196 
197 struct cpuid { u32 a, b, c, d; };
198 
199 static inline struct cpuid raw_cpuid(u32 function, u32 index)
200 {
201 	struct cpuid r;
202 	asm volatile ("cpuid"
203 		      : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d)
204 		      : "0"(function), "2"(index));
205 	return r;
206 }
207 
208 static inline struct cpuid cpuid_indexed(u32 function, u32 index)
209 {
210 	u32 level = raw_cpuid(function & 0xf0000000, 0).a;
211 	if (level < function)
212 	return (struct cpuid) { 0, 0, 0, 0 };
213 	return raw_cpuid(function, index);
214 }
215 
216 static inline struct cpuid cpuid(u32 function)
217 {
218 	return cpuid_indexed(function, 0);
219 }
220 
221 static inline bool is_intel(void)
222 {
223 	struct cpuid c = cpuid(0);
224 	u32 name[4] = {c.b, c.d, c.c };
225 
226 	return strcmp((char *)name, "GenuineIntel") == 0;
227 }
228 
229 /*
230  * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
231  * passed by value with no overhead.
232  */
233 struct x86_cpu_feature {
234 	u32	function;
235 	u16	index;
236 	u8	reg;
237 	u8	bit;
238 };
239 
240 #define X86_CPU_FEATURE(fn, idx, gpr, __bit)					\
241 ({										\
242 	struct x86_cpu_feature feature = {					\
243 		.function = fn,							\
244 		.index = idx,							\
245 		.reg = gpr,							\
246 		.bit = __bit,							\
247 	};									\
248 										\
249 	static_assert((fn & 0xc0000000) == 0 ||					\
250 		      (fn & 0xc0000000) == 0x40000000 ||			\
251 		      (fn & 0xc0000000) == 0x80000000 ||			\
252 		      (fn & 0xc0000000) == 0xc0000000);				\
253 	static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE));	\
254 	feature;								\
255 })
256 
257 /*
258  * Basic Leafs, a.k.a. Intel defined
259  */
260 #define X86_FEATURE_MWAIT		X86_CPU_FEATURE(0x1, 0, ECX, 3)
261 #define X86_FEATURE_VMX			X86_CPU_FEATURE(0x1, 0, ECX, 5)
262 #define X86_FEATURE_PDCM		X86_CPU_FEATURE(0x1, 0, ECX, 15)
263 #define X86_FEATURE_PCID		X86_CPU_FEATURE(0x1, 0, ECX, 17)
264 #define X86_FEATURE_X2APIC		X86_CPU_FEATURE(0x1, 0, ECX, 21)
265 #define X86_FEATURE_MOVBE		X86_CPU_FEATURE(0x1, 0, ECX, 22)
266 #define X86_FEATURE_TSC_DEADLINE_TIMER	X86_CPU_FEATURE(0x1, 0, ECX, 24)
267 #define X86_FEATURE_XSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 26)
268 #define X86_FEATURE_OSXSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 27)
269 #define X86_FEATURE_RDRAND		X86_CPU_FEATURE(0x1, 0, ECX, 30)
270 #define X86_FEATURE_MCE			X86_CPU_FEATURE(0x1, 0, EDX, 7)
271 #define X86_FEATURE_APIC		X86_CPU_FEATURE(0x1, 0, EDX, 9)
272 #define X86_FEATURE_CLFLUSH		X86_CPU_FEATURE(0x1, 0, EDX, 19)
273 #define X86_FEATURE_DS			X86_CPU_FEATURE(0x1, 0, EDX, 21)
274 #define X86_FEATURE_XMM			X86_CPU_FEATURE(0x1, 0, EDX, 25)
275 #define X86_FEATURE_XMM2		X86_CPU_FEATURE(0x1, 0, EDX, 26)
276 #define X86_FEATURE_TSC_ADJUST		X86_CPU_FEATURE(0x7, 0, EBX, 1)
277 #define X86_FEATURE_HLE			X86_CPU_FEATURE(0x7, 0, EBX, 4)
278 #define X86_FEATURE_SMEP		X86_CPU_FEATURE(0x7, 0, EBX, 7)
279 #define X86_FEATURE_INVPCID		X86_CPU_FEATURE(0x7, 0, EBX, 10)
280 #define X86_FEATURE_RTM			X86_CPU_FEATURE(0x7, 0, EBX, 11)
281 #define X86_FEATURE_SMAP		X86_CPU_FEATURE(0x7, 0, EBX, 20)
282 #define X86_FEATURE_PCOMMIT		X86_CPU_FEATURE(0x7, 0, EBX, 22)
283 #define X86_FEATURE_CLFLUSHOPT		X86_CPU_FEATURE(0x7, 0, EBX, 23)
284 #define X86_FEATURE_CLWB		X86_CPU_FEATURE(0x7, 0, EBX, 24)
285 #define X86_FEATURE_INTEL_PT		X86_CPU_FEATURE(0x7, 0, EBX, 25)
286 #define X86_FEATURE_UMIP		X86_CPU_FEATURE(0x7, 0, ECX, 2)
287 #define X86_FEATURE_PKU			X86_CPU_FEATURE(0x7, 0, ECX, 3)
288 #define X86_FEATURE_LA57		X86_CPU_FEATURE(0x7, 0, ECX, 16)
289 #define X86_FEATURE_RDPID		X86_CPU_FEATURE(0x7, 0, ECX, 22)
290 #define X86_FEATURE_SHSTK		X86_CPU_FEATURE(0x7, 0, ECX, 7)
291 #define X86_FEATURE_IBT			X86_CPU_FEATURE(0x7, 0, EDX, 20)
292 #define X86_FEATURE_SPEC_CTRL		X86_CPU_FEATURE(0x7, 0, EDX, 26)
293 #define X86_FEATURE_FLUSH_L1D		X86_CPU_FEATURE(0x7, 0, EDX, 28)
294 #define X86_FEATURE_ARCH_CAPABILITIES	X86_CPU_FEATURE(0x7, 0, EDX, 29)
295 #define X86_FEATURE_PKS			X86_CPU_FEATURE(0x7, 0, ECX, 31)
296 #define X86_FEATURE_LAM			X86_CPU_FEATURE(0x7, 1, EAX, 26)
297 
298 /*
299  * KVM defined leafs
300  */
301 #define KVM_FEATURE_ASYNC_PF		X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
302 #define KVM_FEATURE_ASYNC_PF_INT	X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
303 
304 /*
305  * Extended Leafs, a.k.a. AMD defined
306  */
307 #define X86_FEATURE_SVM			X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
308 #define X86_FEATURE_PERFCTR_CORE	X86_CPU_FEATURE(0x80000001, 0, ECX, 23)
309 #define X86_FEATURE_NX			X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
310 #define X86_FEATURE_GBPAGES		X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
311 #define X86_FEATURE_RDTSCP		X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
312 #define X86_FEATURE_LM			X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
313 #define X86_FEATURE_RDPRU		X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
314 #define X86_FEATURE_AMD_IBPB		X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
315 #define X86_FEATURE_NPT			X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
316 #define X86_FEATURE_LBRV		X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
317 #define X86_FEATURE_NRIPS		X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
318 #define X86_FEATURE_TSCRATEMSR		X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
319 #define X86_FEATURE_PAUSEFILTER		X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
320 #define X86_FEATURE_PFTHRESHOLD		X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
321 #define X86_FEATURE_VGIF		X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
322 #define X86_FEATURE_VNMI		X86_CPU_FEATURE(0x8000000A, 0, EDX, 25)
323 #define X86_FEATURE_SME			X86_CPU_FEATURE(0x8000001F, 0, EAX,  0)
324 #define X86_FEATURE_SEV			X86_CPU_FEATURE(0x8000001F, 0, EAX,  1)
325 #define X86_FEATURE_VM_PAGE_FLUSH	X86_CPU_FEATURE(0x8000001F, 0, EAX,  2)
326 #define X86_FEATURE_SEV_ES		X86_CPU_FEATURE(0x8000001F, 0, EAX,  3)
327 #define X86_FEATURE_SEV_SNP		X86_CPU_FEATURE(0x8000001F, 0, EAX,  4)
328 #define X86_FEATURE_V_TSC_AUX		X86_CPU_FEATURE(0x8000001F, 0, EAX,  9)
329 #define X86_FEATURE_SME_COHERENT	X86_CPU_FEATURE(0x8000001F, 0, EAX, 10)
330 #define X86_FEATURE_DEBUG_SWAP		X86_CPU_FEATURE(0x8000001F, 0, EAX, 14)
331 #define X86_FEATURE_SVSM		X86_CPU_FEATURE(0x8000001F, 0, EAX, 28)
332 #define X86_FEATURE_SBPB		X86_CPU_FEATURE(0x80000021, 0, EAX, 27)
333 #define X86_FEATURE_AMD_PMU_V2		X86_CPU_FEATURE(0x80000022, 0, EAX, 0)
334 
335 /*
336  * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit
337  * value/property as opposed to a single-bit feature.  Again, pack the info
338  * into a 64-bit value to pass by value with no overhead on 64-bit builds.
339  */
340 struct x86_cpu_property {
341 	u32	function;
342 	u8	index;
343 	u8	reg;
344 	u8	lo_bit;
345 	u8	hi_bit;
346 };
347 #define X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit)			\
348 ({										\
349 	struct x86_cpu_property property = {					\
350 		.function = fn,							\
351 		.index = idx,							\
352 		.reg = gpr,							\
353 		.lo_bit = low_bit,						\
354 		.hi_bit = high_bit,						\
355 	};									\
356 										\
357 	static_assert(low_bit < high_bit);					\
358 	static_assert((fn & 0xc0000000) == 0 ||					\
359 		      (fn & 0xc0000000) == 0x40000000 ||			\
360 		      (fn & 0xc0000000) == 0x80000000 ||			\
361 		      (fn & 0xc0000000) == 0xc0000000);				\
362 	static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE));	\
363 	property;								\
364 })
365 
366 #define X86_PROPERTY_MAX_BASIC_LEAF		X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
367 #define X86_PROPERTY_PMU_VERSION		X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
368 #define X86_PROPERTY_PMU_NR_GP_COUNTERS		X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15)
369 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH	X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23)
370 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH	X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31)
371 #define X86_PROPERTY_PMU_EVENTS_MASK		X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7)
372 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK	X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31)
373 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS	X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4)
374 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH	X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12)
375 
376 #define X86_PROPERTY_SUPPORTED_XCR0_LO		X86_CPU_PROPERTY(0xd,  0, EAX,  0, 31)
377 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0	X86_CPU_PROPERTY(0xd,  0, EBX,  0, 31)
378 #define X86_PROPERTY_XSTATE_MAX_SIZE		X86_CPU_PROPERTY(0xd,  0, ECX,  0, 31)
379 #define X86_PROPERTY_SUPPORTED_XCR0_HI		X86_CPU_PROPERTY(0xd,  0, EDX,  0, 31)
380 
381 #define X86_PROPERTY_XSTATE_TILE_SIZE		X86_CPU_PROPERTY(0xd, 18, EAX,  0, 31)
382 #define X86_PROPERTY_XSTATE_TILE_OFFSET		X86_CPU_PROPERTY(0xd, 18, EBX,  0, 31)
383 
384 #define X86_PROPERTY_INTEL_PT_NR_RANGES		X86_CPU_PROPERTY(0x14, 1, EAX,  0, 2)
385 
386 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES	X86_CPU_PROPERTY(0x1d, 0, EAX,  0, 31)
387 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES	X86_CPU_PROPERTY(0x1d, 1, EAX,  0, 15)
388 #define X86_PROPERTY_AMX_BYTES_PER_TILE		X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
389 #define X86_PROPERTY_AMX_BYTES_PER_ROW		X86_CPU_PROPERTY(0x1d, 1, EBX, 0,  15)
390 #define X86_PROPERTY_AMX_NR_TILE_REGS		X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
391 #define X86_PROPERTY_AMX_MAX_ROWS		X86_CPU_PROPERTY(0x1d, 1, ECX, 0,  15)
392 
393 #define X86_PROPERTY_MAX_KVM_LEAF		X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)
394 
395 #define X86_PROPERTY_MAX_EXT_LEAF		X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31)
396 #define X86_PROPERTY_MAX_PHY_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7)
397 #define X86_PROPERTY_MAX_VIRT_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15)
398 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR		X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23)
399 #define X86_PROPERTY_SEV_C_BIT			X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5)
400 #define X86_PROPERTY_PHYS_ADDR_REDUCTION	X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
401 #define X86_PROPERTY_NR_PERFCTR_CORE		X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3)
402 #define X86_PROPERTY_NR_PERFCTR_NB		X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15)
403 
404 #define X86_PROPERTY_MAX_CENTAUR_LEAF		X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
405 
406 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi)
407 {
408 	union {
409 		struct cpuid cpuid;
410 		u32 gprs[4];
411 	} c;
412 
413 	c.cpuid = cpuid_indexed(function, index);
414 
415 	return (c.gprs[reg] & GENMASK(hi, lo)) >> lo;
416 }
417 
418 static inline bool this_cpu_has(struct x86_cpu_feature feature)
419 {
420 	return __this_cpu_has(feature.function, feature.index,
421 			      feature.reg, feature.bit, feature.bit);
422 }
423 
424 static inline uint32_t this_cpu_property(struct x86_cpu_property property)
425 {
426 	return __this_cpu_has(property.function, property.index,
427 			      property.reg, property.lo_bit, property.hi_bit);
428 }
429 
430 static __always_inline bool this_cpu_has_p(struct x86_cpu_property property)
431 {
432 	uint32_t max_leaf;
433 
434 	switch (property.function & 0xc0000000) {
435 	case 0:
436 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
437 		break;
438 	case 0x40000000:
439 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
440 		break;
441 	case 0x80000000:
442 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
443 		break;
444 	case 0xc0000000:
445 		max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
446 	}
447 	return max_leaf >= property.function;
448 }
449 
450 static inline u8 cpuid_maxphyaddr(void)
451 {
452 	if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR))
453 		return 36;
454 
455 	return this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR);
456 }
457 
458 static inline u64 this_cpu_supported_xcr0(void)
459 {
460 	if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO))
461 		return 0;
462 
463 	return (u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) |
464 	       ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
465 }
466 
467 struct far_pointer32 {
468 	u32 offset;
469 	u16 selector;
470 } __attribute__((packed));
471 
472 struct descriptor_table_ptr {
473 	u16 limit;
474 	ulong base;
475 } __attribute__((packed));
476 
477 static inline void clac(void)
478 {
479 	asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory");
480 }
481 
482 static inline void stac(void)
483 {
484 	asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory");
485 }
486 
487 static inline u16 read_cs(void)
488 {
489 	unsigned val;
490 
491 	asm volatile ("mov %%cs, %0" : "=mr"(val));
492 	return val;
493 }
494 
495 static inline u16 read_ds(void)
496 {
497 	unsigned val;
498 
499 	asm volatile ("mov %%ds, %0" : "=mr"(val));
500 	return val;
501 }
502 
503 static inline u16 read_es(void)
504 {
505 	unsigned val;
506 
507 	asm volatile ("mov %%es, %0" : "=mr"(val));
508 	return val;
509 }
510 
511 static inline u16 read_ss(void)
512 {
513 	unsigned val;
514 
515 	asm volatile ("mov %%ss, %0" : "=mr"(val));
516 	return val;
517 }
518 
519 static inline u16 read_fs(void)
520 {
521 	unsigned val;
522 
523 	asm volatile ("mov %%fs, %0" : "=mr"(val));
524 	return val;
525 }
526 
527 static inline u16 read_gs(void)
528 {
529 	unsigned val;
530 
531 	asm volatile ("mov %%gs, %0" : "=mr"(val));
532 	return val;
533 }
534 
535 static inline unsigned long read_rflags(void)
536 {
537 	unsigned long f;
538 	asm volatile ("pushf; pop %0\n\t" : "=rm"(f));
539 	return f;
540 }
541 
542 static inline void write_ds(unsigned val)
543 {
544 	asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory");
545 }
546 
547 static inline void write_es(unsigned val)
548 {
549 	asm volatile ("mov %0, %%es" : : "rm"(val) : "memory");
550 }
551 
552 static inline void write_ss(unsigned val)
553 {
554 	asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory");
555 }
556 
557 static inline void write_fs(unsigned val)
558 {
559 	asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory");
560 }
561 
562 static inline void write_gs(unsigned val)
563 {
564 	asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory");
565 }
566 
567 static inline void write_rflags(unsigned long f)
568 {
569 	asm volatile ("push %0; popf\n\t" : : "rm"(f));
570 }
571 
572 static inline void set_iopl(int iopl)
573 {
574 	unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL;
575 	flags |= iopl * (X86_EFLAGS_IOPL / 3);
576 	write_rflags(flags);
577 }
578 
579 /*
580  * Don't use the safe variants for rdmsr() or wrmsr().  The exception fixup
581  * infrastructure uses per-CPU data and thus consumes GS.base.  Various tests
582  * temporarily modify MSR_GS_BASE and will explode when trying to determine
583  * whether or not RDMSR/WRMSR faulted.
584  */
585 static inline u64 rdmsr(u32 index)
586 {
587 	u32 a, d;
588 	asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory");
589 	return a | ((u64)d << 32);
590 }
591 
592 static inline void wrmsr(u32 index, u64 val)
593 {
594 	u32 a = val, d = val >> 32;
595 	asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory");
596 }
597 
598 #define __rdreg64_safe(fep, insn, index, val)				\
599 ({									\
600 	uint32_t a, d;							\
601 	int vector;							\
602 									\
603 	vector = __asm_safe_out2(fep, insn, "=a"(a), "=d"(d), "c"(index));\
604 									\
605 	if (vector)							\
606 		*(val) = 0;						\
607 	else								\
608 		*(val) = (uint64_t)a | ((uint64_t)d << 32);		\
609 	vector;								\
610 })
611 
612 #define rdreg64_safe(insn, index, val)					\
613 	__rdreg64_safe("", insn, index, val)
614 
615 #define __wrreg64_safe(fep, insn, index, val)				\
616 ({									\
617 	uint32_t eax = (val), edx = (val) >> 32;			\
618 									\
619 	__asm_safe(fep, insn, "a" (eax), "d" (edx), "c" (index));	\
620 })
621 
622 #define wrreg64_safe(insn, index, val)					\
623 	__wrreg64_safe("", insn, index, val)
624 
625 static inline int rdmsr_safe(u32 index, uint64_t *val)
626 {
627 	return rdreg64_safe("rdmsr", index, val);
628 }
629 
630 static inline int rdmsr_fep_safe(u32 index, uint64_t *val)
631 {
632 	return __rdreg64_safe(KVM_FEP, "rdmsr", index, val);
633 }
634 
635 static inline int wrmsr_safe(u32 index, u64 val)
636 {
637 	return wrreg64_safe("wrmsr", index, val);
638 }
639 
640 static inline int wrmsr_fep_safe(u32 index, u64 val)
641 {
642 	return __wrreg64_safe(KVM_FEP, "wrmsr", index, val);
643 }
644 
645 static inline int rdpmc_safe(u32 index, uint64_t *val)
646 {
647 	return rdreg64_safe("rdpmc", index, val);
648 }
649 
650 static inline uint64_t rdpmc(uint32_t index)
651 {
652 	uint64_t val;
653 	int vector = rdpmc_safe(index, &val);
654 
655 	assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")",
656 		   exception_mnemonic(vector), index);
657 	return val;
658 }
659 
660 static inline int xgetbv_safe(u32 index, u64 *result)
661 {
662 	return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result);
663 }
664 
665 static inline int xsetbv_safe(u32 index, u64 value)
666 {
667 	return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value);
668 }
669 
670 static inline int write_cr0_safe(ulong val)
671 {
672 	return asm_safe("mov %0,%%cr0", "r" (val));
673 }
674 
675 static inline void write_cr0(ulong val)
676 {
677 	int vector = write_cr0_safe(val);
678 
679 	assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx",
680 		   vector, val);
681 }
682 
683 static inline ulong read_cr0(void)
684 {
685 	ulong val;
686 	asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory");
687 	return val;
688 }
689 
690 static inline void write_cr2(ulong val)
691 {
692 	asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory");
693 }
694 
695 static inline ulong read_cr2(void)
696 {
697 	ulong val;
698 	asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory");
699 	return val;
700 }
701 
702 static inline int write_cr3_safe(ulong val)
703 {
704 	return asm_safe("mov %0,%%cr3", "r" (val));
705 }
706 
707 static inline void write_cr3(ulong val)
708 {
709 	int vector = write_cr3_safe(val);
710 
711 	assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx",
712 		   vector, val);
713 }
714 
715 static inline ulong read_cr3(void)
716 {
717 	ulong val;
718 	asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory");
719 	return val;
720 }
721 
722 static inline void update_cr3(void *cr3)
723 {
724 	write_cr3((ulong)cr3);
725 }
726 
727 static inline int write_cr4_safe(ulong val)
728 {
729 	return asm_safe("mov %0,%%cr4", "r" (val));
730 }
731 
732 static inline void write_cr4(ulong val)
733 {
734 	int vector = write_cr4_safe(val);
735 
736 	assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx",
737 		   vector, val);
738 }
739 
740 static inline ulong read_cr4(void)
741 {
742 	ulong val;
743 	asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory");
744 	return val;
745 }
746 
747 static inline void write_cr8(ulong val)
748 {
749 	asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory");
750 }
751 
752 static inline ulong read_cr8(void)
753 {
754 	ulong val;
755 	asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory");
756 	return val;
757 }
758 
759 static inline void lgdt(const struct descriptor_table_ptr *ptr)
760 {
761 	asm volatile ("lgdt %0" : : "m"(*ptr));
762 }
763 
764 static inline int lgdt_safe(const struct descriptor_table_ptr *ptr)
765 {
766 	return asm_safe("lgdt %0", "m"(*ptr));
767 }
768 
769 static inline int lgdt_fep_safe(const struct descriptor_table_ptr *ptr)
770 {
771 	return asm_fep_safe("lgdt %0", "m"(*ptr));
772 }
773 
774 static inline void sgdt(struct descriptor_table_ptr *ptr)
775 {
776 	asm volatile ("sgdt %0" : "=m"(*ptr));
777 }
778 
779 static inline void lidt(const struct descriptor_table_ptr *ptr)
780 {
781 	asm volatile ("lidt %0" : : "m"(*ptr));
782 }
783 
784 static inline int lidt_safe(const struct descriptor_table_ptr *ptr)
785 {
786 	return asm_safe("lidt %0", "m"(*ptr));
787 }
788 
789 static inline int lidt_fep_safe(const struct descriptor_table_ptr *ptr)
790 {
791 	return asm_fep_safe("lidt %0", "m"(*ptr));
792 }
793 
794 static inline void sidt(struct descriptor_table_ptr *ptr)
795 {
796 	asm volatile ("sidt %0" : "=m"(*ptr));
797 }
798 
799 static inline void lldt(u16 val)
800 {
801 	asm volatile ("lldt %0" : : "rm"(val));
802 }
803 
804 static inline int lldt_safe(u16 val)
805 {
806 	return asm_safe("lldt %0", "rm"(val));
807 }
808 
809 static inline int lldt_fep_safe(u16 val)
810 {
811 	return asm_safe("lldt %0", "rm"(val));
812 }
813 
814 static inline u16 sldt(void)
815 {
816 	u16 val;
817 	asm volatile ("sldt %0" : "=rm"(val));
818 	return val;
819 }
820 
821 static inline void ltr(u16 val)
822 {
823 	asm volatile ("ltr %0" : : "rm"(val));
824 }
825 
826 static inline int ltr_safe(u16 val)
827 {
828 	return asm_safe("ltr %0", "rm"(val));
829 }
830 
831 static inline int ltr_fep_safe(u16 val)
832 {
833 	return asm_safe("ltr %0", "rm"(val));
834 }
835 
836 static inline u16 str(void)
837 {
838 	u16 val;
839 	asm volatile ("str %0" : "=rm"(val));
840 	return val;
841 }
842 
843 static inline void write_dr0(void *val)
844 {
845 	asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory");
846 }
847 
848 static inline void write_dr1(void *val)
849 {
850 	asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory");
851 }
852 
853 static inline void write_dr2(void *val)
854 {
855 	asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory");
856 }
857 
858 static inline void write_dr3(void *val)
859 {
860 	asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory");
861 }
862 
863 static inline void write_dr6(ulong val)
864 {
865 	asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory");
866 }
867 
868 static inline ulong read_dr6(void)
869 {
870 	ulong val;
871 	asm volatile ("mov %%dr6, %0" : "=r"(val));
872 	return val;
873 }
874 
875 static inline void write_dr7(ulong val)
876 {
877 	asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory");
878 }
879 
880 static inline ulong read_dr7(void)
881 {
882 	ulong val;
883 	asm volatile ("mov %%dr7, %0" : "=r"(val));
884 	return val;
885 }
886 
887 static inline void pause(void)
888 {
889 	asm volatile ("pause");
890 }
891 
892 static inline void cli(void)
893 {
894 	asm volatile ("cli");
895 }
896 
897 /*
898  * See also safe_halt().
899  */
900 static inline void sti(void)
901 {
902 	asm volatile ("sti");
903 }
904 
905 /*
906  * Enable interrupts and ensure that interrupts are evaluated upon return from
907  * this function, i.e. execute a nop to consume the STi interrupt shadow.
908  */
909 static inline void sti_nop(void)
910 {
911 	asm volatile ("sti; nop");
912 }
913 
914 /*
915  * Enable interrupts for one instruction (nop), to allow the CPU to process all
916  * interrupts that are already pending.
917  */
918 static inline void sti_nop_cli(void)
919 {
920 	asm volatile ("sti; nop; cli");
921 }
922 
923 static inline unsigned long long rdrand(void)
924 {
925 	long long r;
926 
927 	asm volatile("rdrand %0\n\t"
928 		     "jc 1f\n\t"
929 		     "mov $0, %0\n\t"
930 		     "1:\n\t" : "=r" (r));
931 	return r;
932 }
933 
934 static inline unsigned long long rdtsc(void)
935 {
936 	long long r;
937 
938 #ifdef __x86_64__
939 	unsigned a, d;
940 
941 	asm volatile ("rdtsc" : "=a"(a), "=d"(d));
942 	r = a | ((long long)d << 32);
943 #else
944 	asm volatile ("rdtsc" : "=A"(r));
945 #endif
946 	return r;
947 }
948 
949 /*
950  * Per the advice in the SDM, volume 2, the sequence "mfence; lfence"
951  * executed immediately before rdtsc ensures that rdtsc will be
952  * executed only after all previous instructions have executed and all
953  * previous loads and stores are globally visible. In addition, the
954  * lfence immediately after rdtsc ensures that rdtsc will be executed
955  * prior to the execution of any subsequent instruction.
956  */
957 static inline unsigned long long fenced_rdtsc(void)
958 {
959 	unsigned long long tsc;
960 
961 #ifdef __x86_64__
962 	unsigned int eax, edx;
963 
964 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
965 	tsc = eax | ((unsigned long long)edx << 32);
966 #else
967 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc));
968 #endif
969 	return tsc;
970 }
971 
972 static inline unsigned long long rdtscp(u32 *aux)
973 {
974 	long long r;
975 
976 #ifdef __x86_64__
977 	unsigned a, d;
978 
979 	asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux));
980 	r = a | ((long long)d << 32);
981 #else
982 	asm volatile ("rdtscp" : "=A"(r), "=c"(*aux));
983 #endif
984 	return r;
985 }
986 
987 static inline void wrtsc(u64 tsc)
988 {
989 	wrmsr(MSR_IA32_TSC, tsc);
990 }
991 
992 
993 static inline void invlpg(volatile void *va)
994 {
995 	asm volatile("invlpg (%0)" ::"r" (va) : "memory");
996 }
997 
998 struct invpcid_desc {
999 	u64 pcid : 12;
1000 	u64 rsv  : 52;
1001 	u64 addr : 64;
1002 };
1003 
1004 static inline int invpcid_safe(unsigned long type, struct invpcid_desc *desc)
1005 {
1006 	/* invpcid (%rax), %rbx */
1007 	return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type));
1008 }
1009 
1010 /*
1011  * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's
1012  * intended to be a wake event arrives *after* HLT is executed.  Modern CPUs,
1013  * except for a few oddballs that KVM is unlikely to run on, block IRQs for one
1014  * instruction after STI, *if* RFLAGS.IF=0 before STI.  Note, Intel CPUs may
1015  * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too.
1016  */
1017 static inline void safe_halt(void)
1018 {
1019 	asm volatile("sti; hlt");
1020 }
1021 
1022 static inline u32 read_pkru(void)
1023 {
1024 	unsigned int eax, edx;
1025 	unsigned int ecx = 0;
1026 	unsigned int pkru;
1027 
1028 	asm volatile(".byte 0x0f,0x01,0xee\n\t"
1029 		     : "=a" (eax), "=d" (edx)
1030 		     : "c" (ecx));
1031 	pkru = eax;
1032 	return pkru;
1033 }
1034 
1035 static inline void write_pkru(u32 pkru)
1036 {
1037 	unsigned int eax = pkru;
1038 	unsigned int ecx = 0;
1039 	unsigned int edx = 0;
1040 
1041 	asm volatile(".byte 0x0f,0x01,0xef\n\t"
1042 		     : : "a" (eax), "c" (ecx), "d" (edx));
1043 }
1044 
1045 static inline bool is_canonical(u64 addr)
1046 {
1047 	int va_width, shift_amt;
1048 
1049 	if (this_cpu_has_p(X86_PROPERTY_MAX_VIRT_ADDR))
1050 		va_width = this_cpu_property(X86_PROPERTY_MAX_VIRT_ADDR);
1051 	else
1052 		va_width = 48;
1053 
1054 	shift_amt = 64 - va_width;
1055 	return (s64)(addr << shift_amt) >> shift_amt == addr;
1056 }
1057 
1058 static inline void flush_tlb(void)
1059 {
1060 	ulong cr4;
1061 
1062 	cr4 = read_cr4();
1063 	write_cr4(cr4 ^ X86_CR4_PGE);
1064 	write_cr4(cr4);
1065 }
1066 
1067 static inline void generate_non_canonical_gp(void)
1068 {
1069 	*(volatile u64 *)NONCANONICAL = 0;
1070 }
1071 
1072 static inline void generate_ud(void)
1073 {
1074 	asm volatile ("ud2");
1075 }
1076 
1077 static inline void generate_de(void)
1078 {
1079 	asm volatile (
1080 		"xor %%eax, %%eax\n\t"
1081 		"xor %%ebx, %%ebx\n\t"
1082 		"xor %%edx, %%edx\n\t"
1083 		"idiv %%ebx\n\t"
1084 		::: "eax", "ebx", "edx");
1085 }
1086 
1087 static inline void generate_bp(void)
1088 {
1089 	asm volatile ("int3");
1090 }
1091 
1092 static inline void generate_single_step_db(void)
1093 {
1094 	write_rflags(read_rflags() | X86_EFLAGS_TF);
1095 	asm volatile("nop");
1096 }
1097 
1098 static inline uint64_t generate_usermode_ac(void)
1099 {
1100 	/*
1101 	 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address.
1102 	 * Disclaimer: It is assumed that the stack pointer is aligned
1103 	 * on a 16-byte boundary as x86_64 stacks should be.
1104 	 */
1105 	asm volatile("movq $0, -0x4(%rsp)");
1106 
1107 	return 0;
1108 }
1109 
1110 /*
1111  * Switch from 64-bit to 32-bit mode and generate #OF via INTO.  Note, if RIP
1112  * or RSP holds a 64-bit value, this helper will NOT generate #OF.
1113  */
1114 static inline void generate_of(void)
1115 {
1116 	struct far_pointer32 fp = {
1117 		.offset = (uintptr_t)&&into,
1118 		.selector = KERNEL_CS32,
1119 	};
1120 	uintptr_t rsp;
1121 
1122 	asm volatile ("mov %%rsp, %0" : "=r"(rsp));
1123 
1124 	if (fp.offset != (uintptr_t)&&into) {
1125 		printf("Code address too high.\n");
1126 		return;
1127 	}
1128 	if ((u32)rsp != rsp) {
1129 		printf("Stack address too high.\n");
1130 		return;
1131 	}
1132 
1133 	asm goto ("lcall *%0" : : "m" (fp) : "rax" : into);
1134 	return;
1135 into:
1136 	asm volatile (".code32;"
1137 		      "movl $0x7fffffff, %eax;"
1138 		      "addl %eax, %eax;"
1139 		      "into;"
1140 		      "lret;"
1141 		      ".code64");
1142 	__builtin_unreachable();
1143 }
1144 
1145 static inline void fnop(void)
1146 {
1147 	asm volatile("fnop");
1148 }
1149 
1150 /* If CR0.TS is set in L2, #NM is generated. */
1151 static inline void generate_cr0_ts_nm(void)
1152 {
1153 	write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS);
1154 	fnop();
1155 }
1156 
1157 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */
1158 static inline void generate_cr0_em_nm(void)
1159 {
1160 	write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM);
1161 	fnop();
1162 }
1163 
1164 static inline bool is_la57_enabled(void)
1165 {
1166 	return !!(read_cr4() & X86_CR4_LA57);
1167 }
1168 
1169 static inline bool is_lam_sup_enabled(void)
1170 {
1171 	return !!(read_cr4() & X86_CR4_LAM_SUP);
1172 }
1173 
1174 static inline bool is_lam_u48_enabled(void)
1175 {
1176 	return (read_cr3() & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)) == X86_CR3_LAM_U48;
1177 }
1178 
1179 static inline bool is_lam_u57_enabled(void)
1180 {
1181 	return !!(read_cr3() & X86_CR3_LAM_U57);
1182 }
1183 
1184 #endif
1185