1 #ifndef LIBCFLAT_PROCESSOR_H 2 #define LIBCFLAT_PROCESSOR_H 3 4 #include "libcflat.h" 5 #include "msr.h" 6 #include <stdint.h> 7 8 #ifdef __x86_64__ 9 # define R "r" 10 # define W "q" 11 # define S "8" 12 #else 13 # define R "e" 14 # define W "l" 15 # define S "4" 16 #endif 17 18 #define DB_VECTOR 1 19 #define BP_VECTOR 3 20 #define UD_VECTOR 6 21 #define DF_VECTOR 8 22 #define TS_VECTOR 10 23 #define NP_VECTOR 11 24 #define SS_VECTOR 12 25 #define GP_VECTOR 13 26 #define PF_VECTOR 14 27 #define AC_VECTOR 17 28 29 #define X86_CR0_PE 0x00000001 30 #define X86_CR0_MP 0x00000002 31 #define X86_CR0_EM 0x00000004 32 #define X86_CR0_TS 0x00000008 33 #define X86_CR0_WP 0x00010000 34 #define X86_CR0_AM 0x00040000 35 #define X86_CR0_PG 0x80000000 36 #define X86_CR3_PCID_MASK 0x00000fff 37 #define X86_CR4_TSD 0x00000004 38 #define X86_CR4_DE 0x00000008 39 #define X86_CR4_PSE 0x00000010 40 #define X86_CR4_PAE 0x00000020 41 #define X86_CR4_MCE 0x00000040 42 #define X86_CR4_PGE 0x00000080 43 #define X86_CR4_PCE 0x00000100 44 #define X86_CR4_UMIP 0x00000800 45 #define X86_CR4_VMXE 0x00002000 46 #define X86_CR4_PCIDE 0x00020000 47 #define X86_CR4_SMEP 0x00100000 48 #define X86_CR4_SMAP 0x00200000 49 #define X86_CR4_PKE 0x00400000 50 51 #define X86_EFLAGS_CF 0x00000001 52 #define X86_EFLAGS_FIXED 0x00000002 53 #define X86_EFLAGS_PF 0x00000004 54 #define X86_EFLAGS_AF 0x00000010 55 #define X86_EFLAGS_ZF 0x00000040 56 #define X86_EFLAGS_SF 0x00000080 57 #define X86_EFLAGS_TF 0x00000100 58 #define X86_EFLAGS_IF 0x00000200 59 #define X86_EFLAGS_DF 0x00000400 60 #define X86_EFLAGS_OF 0x00000800 61 #define X86_EFLAGS_IOPL 0x00003000 62 #define X86_EFLAGS_NT 0x00004000 63 #define X86_EFLAGS_AC 0x00040000 64 65 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 66 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 67 68 #define X86_IA32_EFER 0xc0000080 69 #define X86_EFER_LMA (1UL << 8) 70 71 /* 72 * CPU features 73 */ 74 75 enum cpuid_output_regs { 76 EAX, 77 EBX, 78 ECX, 79 EDX 80 }; 81 82 struct cpuid { u32 a, b, c, d; }; 83 84 static inline struct cpuid raw_cpuid(u32 function, u32 index) 85 { 86 struct cpuid r; 87 asm volatile ("cpuid" 88 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 89 : "0"(function), "2"(index)); 90 return r; 91 } 92 93 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 94 { 95 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 96 if (level < function) 97 return (struct cpuid) { 0, 0, 0, 0 }; 98 return raw_cpuid(function, index); 99 } 100 101 static inline struct cpuid cpuid(u32 function) 102 { 103 return cpuid_indexed(function, 0); 104 } 105 106 static inline u8 cpuid_maxphyaddr(void) 107 { 108 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 109 return 36; 110 return raw_cpuid(0x80000008, 0).a & 0xff; 111 } 112 113 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 114 (c << 8) | d) 115 116 /* 117 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 118 * CPUID meta-data: 119 * 120 * [63:32] : input value for EAX 121 * [31:16] : input value for ECX 122 * [15:8] : output register 123 * [7:0] : bit position in output register 124 */ 125 126 /* 127 * Intel CPUID features 128 */ 129 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 130 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 131 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 132 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 133 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 134 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 135 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 136 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 137 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 138 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 139 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 140 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 141 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 142 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 143 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 144 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 145 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 146 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 147 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 148 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 149 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 150 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 151 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 152 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 153 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 154 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 155 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 156 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 157 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 158 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 159 160 /* 161 * AMD CPUID features 162 */ 163 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 164 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 165 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 166 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 167 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 168 169 170 static inline bool this_cpu_has(u64 feature) 171 { 172 u32 input_eax = feature >> 32; 173 u32 input_ecx = (feature >> 16) & 0xffff; 174 u32 output_reg = (feature >> 8) & 0xff; 175 u8 bit = feature & 0xff; 176 struct cpuid c; 177 u32 *tmp; 178 179 c = cpuid_indexed(input_eax, input_ecx); 180 tmp = (u32 *)&c; 181 182 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 183 } 184 185 struct far_pointer32 { 186 u32 offset; 187 u16 selector; 188 } __attribute__((packed)); 189 190 struct descriptor_table_ptr { 191 u16 limit; 192 ulong base; 193 } __attribute__((packed)); 194 195 static inline void barrier(void) 196 { 197 asm volatile ("" : : : "memory"); 198 } 199 200 static inline void clac(void) 201 { 202 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 203 } 204 205 static inline void stac(void) 206 { 207 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 208 } 209 210 static inline u16 read_cs(void) 211 { 212 unsigned val; 213 214 asm volatile ("mov %%cs, %0" : "=mr"(val)); 215 return val; 216 } 217 218 static inline u16 read_ds(void) 219 { 220 unsigned val; 221 222 asm volatile ("mov %%ds, %0" : "=mr"(val)); 223 return val; 224 } 225 226 static inline u16 read_es(void) 227 { 228 unsigned val; 229 230 asm volatile ("mov %%es, %0" : "=mr"(val)); 231 return val; 232 } 233 234 static inline u16 read_ss(void) 235 { 236 unsigned val; 237 238 asm volatile ("mov %%ss, %0" : "=mr"(val)); 239 return val; 240 } 241 242 static inline u16 read_fs(void) 243 { 244 unsigned val; 245 246 asm volatile ("mov %%fs, %0" : "=mr"(val)); 247 return val; 248 } 249 250 static inline u16 read_gs(void) 251 { 252 unsigned val; 253 254 asm volatile ("mov %%gs, %0" : "=mr"(val)); 255 return val; 256 } 257 258 static inline unsigned long read_rflags(void) 259 { 260 unsigned long f; 261 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 262 return f; 263 } 264 265 static inline void write_ds(unsigned val) 266 { 267 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 268 } 269 270 static inline void write_es(unsigned val) 271 { 272 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 273 } 274 275 static inline void write_ss(unsigned val) 276 { 277 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 278 } 279 280 static inline void write_fs(unsigned val) 281 { 282 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 283 } 284 285 static inline void write_gs(unsigned val) 286 { 287 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 288 } 289 290 static inline void write_rflags(unsigned long f) 291 { 292 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 293 } 294 295 static inline void set_iopl(int iopl) 296 { 297 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 298 flags |= iopl * (X86_EFLAGS_IOPL / 3); 299 write_rflags(flags); 300 } 301 302 static inline u64 rdmsr(u32 index) 303 { 304 u32 a, d; 305 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 306 return a | ((u64)d << 32); 307 } 308 309 static inline void wrmsr(u32 index, u64 val) 310 { 311 u32 a = val, d = val >> 32; 312 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 313 } 314 315 static inline uint64_t rdpmc(uint32_t index) 316 { 317 uint32_t a, d; 318 asm volatile ("rdpmc" : "=a"(a), "=d"(d) : "c"(index)); 319 return a | ((uint64_t)d << 32); 320 } 321 322 static inline void write_cr0(ulong val) 323 { 324 asm volatile ("mov %0, %%cr0" : : "r"(val) : "memory"); 325 } 326 327 static inline ulong read_cr0(void) 328 { 329 ulong val; 330 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 331 return val; 332 } 333 334 static inline void write_cr2(ulong val) 335 { 336 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 337 } 338 339 static inline ulong read_cr2(void) 340 { 341 ulong val; 342 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 343 return val; 344 } 345 346 static inline void write_cr3(ulong val) 347 { 348 asm volatile ("mov %0, %%cr3" : : "r"(val) : "memory"); 349 } 350 351 static inline ulong read_cr3(void) 352 { 353 ulong val; 354 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 355 return val; 356 } 357 358 static inline void write_cr4(ulong val) 359 { 360 asm volatile ("mov %0, %%cr4" : : "r"(val) : "memory"); 361 } 362 363 static inline ulong read_cr4(void) 364 { 365 ulong val; 366 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 367 return val; 368 } 369 370 static inline void write_cr8(ulong val) 371 { 372 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 373 } 374 375 static inline ulong read_cr8(void) 376 { 377 ulong val; 378 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 379 return val; 380 } 381 382 static inline void lgdt(const struct descriptor_table_ptr *ptr) 383 { 384 asm volatile ("lgdt %0" : : "m"(*ptr)); 385 } 386 387 static inline void sgdt(struct descriptor_table_ptr *ptr) 388 { 389 asm volatile ("sgdt %0" : "=m"(*ptr)); 390 } 391 392 static inline void lidt(const struct descriptor_table_ptr *ptr) 393 { 394 asm volatile ("lidt %0" : : "m"(*ptr)); 395 } 396 397 static inline void sidt(struct descriptor_table_ptr *ptr) 398 { 399 asm volatile ("sidt %0" : "=m"(*ptr)); 400 } 401 402 static inline void lldt(unsigned val) 403 { 404 asm volatile ("lldt %0" : : "rm"(val)); 405 } 406 407 static inline u16 sldt(void) 408 { 409 u16 val; 410 asm volatile ("sldt %0" : "=rm"(val)); 411 return val; 412 } 413 414 static inline void ltr(u16 val) 415 { 416 asm volatile ("ltr %0" : : "rm"(val)); 417 } 418 419 static inline u16 str(void) 420 { 421 u16 val; 422 asm volatile ("str %0" : "=rm"(val)); 423 return val; 424 } 425 426 static inline void write_dr6(ulong val) 427 { 428 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 429 } 430 431 static inline ulong read_dr6(void) 432 { 433 ulong val; 434 asm volatile ("mov %%dr6, %0" : "=r"(val)); 435 return val; 436 } 437 438 static inline void write_dr7(ulong val) 439 { 440 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 441 } 442 443 static inline ulong read_dr7(void) 444 { 445 ulong val; 446 asm volatile ("mov %%dr7, %0" : "=r"(val)); 447 return val; 448 } 449 450 static inline void pause(void) 451 { 452 asm volatile ("pause"); 453 } 454 455 static inline void cli(void) 456 { 457 asm volatile ("cli"); 458 } 459 460 static inline void sti(void) 461 { 462 asm volatile ("sti"); 463 } 464 465 static inline unsigned long long rdtsc(void) 466 { 467 long long r; 468 469 #ifdef __x86_64__ 470 unsigned a, d; 471 472 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 473 r = a | ((long long)d << 32); 474 #else 475 asm volatile ("rdtsc" : "=A"(r)); 476 #endif 477 return r; 478 } 479 480 static inline unsigned long long rdtscp(u32 *aux) 481 { 482 long long r; 483 484 #ifdef __x86_64__ 485 unsigned a, d; 486 487 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 488 r = a | ((long long)d << 32); 489 #else 490 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 491 #endif 492 return r; 493 } 494 495 static inline void wrtsc(u64 tsc) 496 { 497 unsigned a = tsc, d = tsc >> 32; 498 499 asm volatile("wrmsr" : : "a"(a), "d"(d), "c"(0x10)); 500 } 501 502 static inline void irq_disable(void) 503 { 504 asm volatile("cli"); 505 } 506 507 /* Note that irq_enable() does not ensure an interrupt shadow due 508 * to the vagaries of compiler optimizations. If you need the 509 * shadow, use a single asm with "sti" and the instruction after it. 510 */ 511 static inline void irq_enable(void) 512 { 513 asm volatile("sti"); 514 } 515 516 static inline void invlpg(volatile void *va) 517 { 518 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 519 } 520 521 static inline void safe_halt(void) 522 { 523 asm volatile("sti; hlt"); 524 } 525 526 static inline u32 read_pkru(void) 527 { 528 unsigned int eax, edx; 529 unsigned int ecx = 0; 530 unsigned int pkru; 531 532 asm volatile(".byte 0x0f,0x01,0xee\n\t" 533 : "=a" (eax), "=d" (edx) 534 : "c" (ecx)); 535 pkru = eax; 536 return pkru; 537 } 538 539 static inline void write_pkru(u32 pkru) 540 { 541 unsigned int eax = pkru; 542 unsigned int ecx = 0; 543 unsigned int edx = 0; 544 545 asm volatile(".byte 0x0f,0x01,0xef\n\t" 546 : : "a" (eax), "c" (ecx), "d" (edx)); 547 } 548 549 static inline bool is_canonical(u64 addr) 550 { 551 return (s64)(addr << 16) >> 16 == addr; 552 } 553 554 static inline void clear_bit(int bit, u8 *addr) 555 { 556 __asm__ __volatile__("btr %1, %0" 557 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 558 } 559 560 static inline void set_bit(int bit, u8 *addr) 561 { 562 __asm__ __volatile__("bts %1, %0" 563 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 564 } 565 566 static inline void flush_tlb(void) 567 { 568 ulong cr4; 569 570 cr4 = read_cr4(); 571 write_cr4(cr4 ^ X86_CR4_PGE); 572 write_cr4(cr4); 573 } 574 575 static inline int has_spec_ctrl(void) 576 { 577 return !!(this_cpu_has(X86_FEATURE_SPEC_CTRL)); 578 } 579 580 static inline int cpu_has_efer_nx(void) 581 { 582 return !!(this_cpu_has(X86_FEATURE_NX)); 583 } 584 585 #endif 586