xref: /kvm-unit-tests/lib/x86/processor.h (revision 361f623cb12e71ef56727cabefc273508ef29950)
1 #ifndef _X86_PROCESSOR_H_
2 #define _X86_PROCESSOR_H_
3 
4 #include "libcflat.h"
5 #include "desc.h"
6 #include "msr.h"
7 #include <bitops.h>
8 #include <stdint.h>
9 #include <util.h>
10 
11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull
12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull
13 #define NONCANONICAL	 0xaaaaaaaaaaaaaaaaull
14 
15 #define LAM57_MASK	GENMASK_ULL(62, 57)
16 #define LAM48_MASK	GENMASK_ULL(62, 48)
17 
18 /*
19  * Get a linear address by combining @addr with a non-canonical pattern in the
20  * @mask bits.
21  */
22 static inline u64 get_non_canonical(u64 addr, u64 mask)
23 {
24 	return (addr & ~mask) | (NONCANONICAL & mask);
25 }
26 
27 #ifdef __x86_64__
28 #  define R "r"
29 #  define W "q"
30 #  define S "8"
31 #else
32 #  define R "e"
33 #  define W "l"
34 #  define S "4"
35 #endif
36 
37 #define DE_VECTOR 0
38 #define DB_VECTOR 1
39 #define NMI_VECTOR 2
40 #define BP_VECTOR 3
41 #define OF_VECTOR 4
42 #define BR_VECTOR 5
43 #define UD_VECTOR 6
44 #define NM_VECTOR 7
45 #define DF_VECTOR 8
46 #define TS_VECTOR 10
47 #define NP_VECTOR 11
48 #define SS_VECTOR 12
49 #define GP_VECTOR 13
50 #define PF_VECTOR 14
51 #define MF_VECTOR 16
52 #define AC_VECTOR 17
53 #define MC_VECTOR 18
54 #define XM_VECTOR 19
55 #define XF_VECTOR XM_VECTOR /* AMD */
56 #define VE_VECTOR 20 /* Intel only */
57 #define CP_VECTOR 21
58 #define HV_VECTOR 28 /* AMD only */
59 #define VC_VECTOR 29 /* AMD only */
60 #define SX_VECTOR 30 /* AMD only */
61 
62 #define X86_CR0_PE_BIT		(0)
63 #define X86_CR0_PE		BIT(X86_CR0_PE_BIT)
64 #define X86_CR0_MP_BIT		(1)
65 #define X86_CR0_MP		BIT(X86_CR0_MP_BIT)
66 #define X86_CR0_EM_BIT		(2)
67 #define X86_CR0_EM		BIT(X86_CR0_EM_BIT)
68 #define X86_CR0_TS_BIT		(3)
69 #define X86_CR0_TS		BIT(X86_CR0_TS_BIT)
70 #define X86_CR0_ET_BIT		(4)
71 #define X86_CR0_ET		BIT(X86_CR0_ET_BIT)
72 #define X86_CR0_NE_BIT		(5)
73 #define X86_CR0_NE		BIT(X86_CR0_NE_BIT)
74 #define X86_CR0_WP_BIT		(16)
75 #define X86_CR0_WP		BIT(X86_CR0_WP_BIT)
76 #define X86_CR0_AM_BIT		(18)
77 #define X86_CR0_AM		BIT(X86_CR0_AM_BIT)
78 #define X86_CR0_NW_BIT		(29)
79 #define X86_CR0_NW		BIT(X86_CR0_NW_BIT)
80 #define X86_CR0_CD_BIT		(30)
81 #define X86_CR0_CD		BIT(X86_CR0_CD_BIT)
82 #define X86_CR0_PG_BIT		(31)
83 #define X86_CR0_PG		BIT(X86_CR0_PG_BIT)
84 
85 #define X86_CR3_PCID_MASK	GENMASK(11, 0)
86 #define X86_CR3_LAM_U57_BIT	(61)
87 #define X86_CR3_LAM_U57		BIT_ULL(X86_CR3_LAM_U57_BIT)
88 #define X86_CR3_LAM_U48_BIT	(62)
89 #define X86_CR3_LAM_U48		BIT_ULL(X86_CR3_LAM_U48_BIT)
90 
91 #define X86_CR4_VME_BIT		(0)
92 #define X86_CR4_VME		BIT(X86_CR4_VME_BIT)
93 #define X86_CR4_PVI_BIT		(1)
94 #define X86_CR4_PVI		BIT(X86_CR4_PVI_BIT)
95 #define X86_CR4_TSD_BIT		(2)
96 #define X86_CR4_TSD		BIT(X86_CR4_TSD_BIT)
97 #define X86_CR4_DE_BIT		(3)
98 #define X86_CR4_DE		BIT(X86_CR4_DE_BIT)
99 #define X86_CR4_PSE_BIT		(4)
100 #define X86_CR4_PSE		BIT(X86_CR4_PSE_BIT)
101 #define X86_CR4_PAE_BIT		(5)
102 #define X86_CR4_PAE		BIT(X86_CR4_PAE_BIT)
103 #define X86_CR4_MCE_BIT		(6)
104 #define X86_CR4_MCE		BIT(X86_CR4_MCE_BIT)
105 #define X86_CR4_PGE_BIT		(7)
106 #define X86_CR4_PGE		BIT(X86_CR4_PGE_BIT)
107 #define X86_CR4_PCE_BIT		(8)
108 #define X86_CR4_PCE		BIT(X86_CR4_PCE_BIT)
109 #define X86_CR4_OSFXSR_BIT	(9)
110 #define X86_CR4_OSFXSR		BIT(X86_CR4_OSFXSR_BIT)
111 #define X86_CR4_OSXMMEXCPT_BIT	(10)
112 #define X86_CR4_OSXMMEXCPT	BIT(X86_CR4_OSXMMEXCPT_BIT)
113 #define X86_CR4_UMIP_BIT	(11)
114 #define X86_CR4_UMIP		BIT(X86_CR4_UMIP_BIT)
115 #define X86_CR4_LA57_BIT	(12)
116 #define X86_CR4_LA57		BIT(X86_CR4_LA57_BIT)
117 #define X86_CR4_VMXE_BIT	(13)
118 #define X86_CR4_VMXE		BIT(X86_CR4_VMXE_BIT)
119 #define X86_CR4_SMXE_BIT	(14)
120 #define X86_CR4_SMXE		BIT(X86_CR4_SMXE_BIT)
121 /* UNUSED			(15) */
122 #define X86_CR4_FSGSBASE_BIT	(16)
123 #define X86_CR4_FSGSBASE	BIT(X86_CR4_FSGSBASE_BIT)
124 #define X86_CR4_PCIDE_BIT	(17)
125 #define X86_CR4_PCIDE		BIT(X86_CR4_PCIDE_BIT)
126 #define X86_CR4_OSXSAVE_BIT	(18)
127 #define X86_CR4_OSXSAVE		BIT(X86_CR4_OSXSAVE_BIT)
128 #define X86_CR4_KL_BIT		(19)
129 #define X86_CR4_KL		BIT(X86_CR4_KL_BIT)
130 #define X86_CR4_SMEP_BIT	(20)
131 #define X86_CR4_SMEP		BIT(X86_CR4_SMEP_BIT)
132 #define X86_CR4_SMAP_BIT	(21)
133 #define X86_CR4_SMAP		BIT(X86_CR4_SMAP_BIT)
134 #define X86_CR4_PKE_BIT		(22)
135 #define X86_CR4_PKE		BIT(X86_CR4_PKE_BIT)
136 #define X86_CR4_CET_BIT		(23)
137 #define X86_CR4_CET		BIT(X86_CR4_CET_BIT)
138 #define X86_CR4_PKS_BIT		(24)
139 #define X86_CR4_PKS		BIT(X86_CR4_PKS_BIT)
140 #define X86_CR4_LAM_SUP_BIT	(28)
141 #define X86_CR4_LAM_SUP		BIT(X86_CR4_LAM_SUP_BIT)
142 
143 #define X86_EFLAGS_CF_BIT	(0)
144 #define X86_EFLAGS_CF		BIT(X86_EFLAGS_CF_BIT)
145 #define X86_EFLAGS_FIXED_BIT	(1)
146 #define X86_EFLAGS_FIXED	BIT(X86_EFLAGS_FIXED_BIT)
147 #define X86_EFLAGS_PF_BIT	(2)
148 #define X86_EFLAGS_PF		BIT(X86_EFLAGS_PF_BIT)
149 /* RESERVED 0			(3) */
150 #define X86_EFLAGS_AF_BIT	(4)
151 #define X86_EFLAGS_AF		BIT(X86_EFLAGS_AF_BIT)
152 /* RESERVED 0			(5) */
153 #define X86_EFLAGS_ZF_BIT	(6)
154 #define X86_EFLAGS_ZF		BIT(X86_EFLAGS_ZF_BIT)
155 #define X86_EFLAGS_SF_BIT	(7)
156 #define X86_EFLAGS_SF		BIT(X86_EFLAGS_SF_BIT)
157 #define X86_EFLAGS_TF_BIT	(8)
158 #define X86_EFLAGS_TF		BIT(X86_EFLAGS_TF_BIT)
159 #define X86_EFLAGS_IF_BIT	(9)
160 #define X86_EFLAGS_IF		BIT(X86_EFLAGS_IF_BIT)
161 #define X86_EFLAGS_DF_BIT	(10)
162 #define X86_EFLAGS_DF		BIT(X86_EFLAGS_DF_BIT)
163 #define X86_EFLAGS_OF_BIT	(11)
164 #define X86_EFLAGS_OF		BIT(X86_EFLAGS_OF_BIT)
165 #define X86_EFLAGS_IOPL		GENMASK(13, 12)
166 #define X86_EFLAGS_NT_BIT	(14)
167 #define X86_EFLAGS_NT		BIT(X86_EFLAGS_NT_BIT)
168 /* RESERVED 0			(15) */
169 #define X86_EFLAGS_RF_BIT	(16)
170 #define X86_EFLAGS_RF		BIT(X86_EFLAGS_RF_BIT)
171 #define X86_EFLAGS_VM_BIT	(17)
172 #define X86_EFLAGS_VM		BIT(X86_EFLAGS_VM_BIT)
173 #define X86_EFLAGS_AC_BIT	(18)
174 #define X86_EFLAGS_AC		BIT(X86_EFLAGS_AC_BIT)
175 #define X86_EFLAGS_VIF_BIT	(19)
176 #define X86_EFLAGS_VIF		BIT(X86_EFLAGS_VIF_BIT)
177 #define X86_EFLAGS_VIP_BIT	(20)
178 #define X86_EFLAGS_VIP		BIT(X86_EFLAGS_VIP_BIT)
179 #define X86_EFLAGS_ID_BIT	(21)
180 #define X86_EFLAGS_ID		BIT(X86_EFLAGS_ID_BIT)
181 
182 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \
183 			X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)
184 
185 
186 /*
187  * CPU features
188  */
189 
190 enum cpuid_output_regs {
191 	EAX,
192 	EBX,
193 	ECX,
194 	EDX
195 };
196 
197 struct cpuid { u32 a, b, c, d; };
198 
199 static inline struct cpuid raw_cpuid(u32 function, u32 index)
200 {
201 	struct cpuid r;
202 	asm volatile ("cpuid"
203 		      : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d)
204 		      : "0"(function), "2"(index));
205 	return r;
206 }
207 
208 static inline struct cpuid cpuid_indexed(u32 function, u32 index)
209 {
210 	u32 level = raw_cpuid(function & 0xf0000000, 0).a;
211 	if (level < function)
212 	return (struct cpuid) { 0, 0, 0, 0 };
213 	return raw_cpuid(function, index);
214 }
215 
216 static inline struct cpuid cpuid(u32 function)
217 {
218 	return cpuid_indexed(function, 0);
219 }
220 
221 static inline u8 cpuid_maxphyaddr(void)
222 {
223 	if (raw_cpuid(0x80000000, 0).a < 0x80000008)
224 	return 36;
225 	return raw_cpuid(0x80000008, 0).a & 0xff;
226 }
227 
228 static inline bool is_intel(void)
229 {
230 	struct cpuid c = cpuid(0);
231 	u32 name[4] = {c.b, c.d, c.c };
232 
233 	return strcmp((char *)name, "GenuineIntel") == 0;
234 }
235 
236 /*
237  * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
238  * passed by value with no overhead.
239  */
240 struct x86_cpu_feature {
241 	u32	function;
242 	u16	index;
243 	u8	reg;
244 	u8	bit;
245 };
246 
247 #define X86_CPU_FEATURE(fn, idx, gpr, __bit)					\
248 ({										\
249 	struct x86_cpu_feature feature = {					\
250 		.function = fn,							\
251 		.index = idx,							\
252 		.reg = gpr,							\
253 		.bit = __bit,							\
254 	};									\
255 										\
256 	static_assert((fn & 0xc0000000) == 0 ||					\
257 		      (fn & 0xc0000000) == 0x40000000 ||			\
258 		      (fn & 0xc0000000) == 0x80000000 ||			\
259 		      (fn & 0xc0000000) == 0xc0000000);				\
260 	static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE));	\
261 	feature;								\
262 })
263 
264 /*
265  * Basic Leafs, a.k.a. Intel defined
266  */
267 #define X86_FEATURE_MWAIT		X86_CPU_FEATURE(0x1, 0, ECX, 3)
268 #define X86_FEATURE_VMX			X86_CPU_FEATURE(0x1, 0, ECX, 5)
269 #define X86_FEATURE_PDCM		X86_CPU_FEATURE(0x1, 0, ECX, 15)
270 #define X86_FEATURE_PCID		X86_CPU_FEATURE(0x1, 0, ECX, 17)
271 #define X86_FEATURE_X2APIC		X86_CPU_FEATURE(0x1, 0, ECX, 21)
272 #define X86_FEATURE_MOVBE		X86_CPU_FEATURE(0x1, 0, ECX, 22)
273 #define X86_FEATURE_TSC_DEADLINE_TIMER	X86_CPU_FEATURE(0x1, 0, ECX, 24)
274 #define X86_FEATURE_XSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 26)
275 #define X86_FEATURE_OSXSAVE		X86_CPU_FEATURE(0x1, 0, ECX, 27)
276 #define X86_FEATURE_RDRAND		X86_CPU_FEATURE(0x1, 0, ECX, 30)
277 #define X86_FEATURE_MCE			X86_CPU_FEATURE(0x1, 0, EDX, 7)
278 #define X86_FEATURE_APIC		X86_CPU_FEATURE(0x1, 0, EDX, 9)
279 #define X86_FEATURE_CLFLUSH		X86_CPU_FEATURE(0x1, 0, EDX, 19)
280 #define X86_FEATURE_DS			X86_CPU_FEATURE(0x1, 0, EDX, 21)
281 #define X86_FEATURE_XMM			X86_CPU_FEATURE(0x1, 0, EDX, 25)
282 #define X86_FEATURE_XMM2		X86_CPU_FEATURE(0x1, 0, EDX, 26)
283 #define X86_FEATURE_TSC_ADJUST		X86_CPU_FEATURE(0x7, 0, EBX, 1)
284 #define X86_FEATURE_HLE			X86_CPU_FEATURE(0x7, 0, EBX, 4)
285 #define X86_FEATURE_SMEP		X86_CPU_FEATURE(0x7, 0, EBX, 7)
286 #define X86_FEATURE_INVPCID		X86_CPU_FEATURE(0x7, 0, EBX, 10)
287 #define X86_FEATURE_RTM			X86_CPU_FEATURE(0x7, 0, EBX, 11)
288 #define X86_FEATURE_SMAP		X86_CPU_FEATURE(0x7, 0, EBX, 20)
289 #define X86_FEATURE_PCOMMIT		X86_CPU_FEATURE(0x7, 0, EBX, 22)
290 #define X86_FEATURE_CLFLUSHOPT		X86_CPU_FEATURE(0x7, 0, EBX, 23)
291 #define X86_FEATURE_CLWB		X86_CPU_FEATURE(0x7, 0, EBX, 24)
292 #define X86_FEATURE_INTEL_PT		X86_CPU_FEATURE(0x7, 0, EBX, 25)
293 #define X86_FEATURE_UMIP		X86_CPU_FEATURE(0x7, 0, ECX, 2)
294 #define X86_FEATURE_PKU			X86_CPU_FEATURE(0x7, 0, ECX, 3)
295 #define X86_FEATURE_LA57		X86_CPU_FEATURE(0x7, 0, ECX, 16)
296 #define X86_FEATURE_RDPID		X86_CPU_FEATURE(0x7, 0, ECX, 22)
297 #define X86_FEATURE_SHSTK		X86_CPU_FEATURE(0x7, 0, ECX, 7)
298 #define X86_FEATURE_IBT			X86_CPU_FEATURE(0x7, 0, EDX, 20)
299 #define X86_FEATURE_SPEC_CTRL		X86_CPU_FEATURE(0x7, 0, EDX, 26)
300 #define X86_FEATURE_FLUSH_L1D		X86_CPU_FEATURE(0x7, 0, EDX, 28)
301 #define X86_FEATURE_ARCH_CAPABILITIES	X86_CPU_FEATURE(0x7, 0, EDX, 29)
302 #define X86_FEATURE_PKS			X86_CPU_FEATURE(0x7, 0, ECX, 31)
303 #define X86_FEATURE_LAM			X86_CPU_FEATURE(0x7, 1, EAX, 26)
304 
305 /*
306  * KVM defined leafs
307  */
308 #define KVM_FEATURE_ASYNC_PF		X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
309 #define KVM_FEATURE_ASYNC_PF_INT	X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
310 
311 /*
312  * Extended Leafs, a.k.a. AMD defined
313  */
314 #define X86_FEATURE_SVM			X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
315 #define X86_FEATURE_PERFCTR_CORE	X86_CPU_FEATURE(0x80000001, 0, ECX, 23)
316 #define X86_FEATURE_NX			X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
317 #define X86_FEATURE_GBPAGES		X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
318 #define X86_FEATURE_RDTSCP		X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
319 #define X86_FEATURE_LM			X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
320 #define X86_FEATURE_RDPRU		X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
321 #define X86_FEATURE_AMD_IBPB		X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
322 #define X86_FEATURE_NPT			X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
323 #define X86_FEATURE_LBRV		X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
324 #define X86_FEATURE_NRIPS		X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
325 #define X86_FEATURE_TSCRATEMSR		X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
326 #define X86_FEATURE_PAUSEFILTER		X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
327 #define X86_FEATURE_PFTHRESHOLD		X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
328 #define X86_FEATURE_VGIF		X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
329 #define X86_FEATURE_VNMI		X86_CPU_FEATURE(0x8000000A, 0, EDX, 25)
330 #define X86_FEATURE_AMD_PMU_V2		X86_CPU_FEATURE(0x80000022, 0, EAX, 0)
331 
332 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi)
333 {
334 	union {
335 		struct cpuid cpuid;
336 		u32 gprs[4];
337 	} c;
338 
339 	c.cpuid = cpuid_indexed(function, index);
340 
341 	return (c.gprs[reg] & GENMASK(hi, lo)) >> lo;
342 }
343 
344 static inline bool this_cpu_has(struct x86_cpu_feature feature)
345 {
346 	return __this_cpu_has(feature.function, feature.index,
347 			      feature.reg, feature.bit, feature.bit);
348 }
349 
350 struct far_pointer32 {
351 	u32 offset;
352 	u16 selector;
353 } __attribute__((packed));
354 
355 struct descriptor_table_ptr {
356 	u16 limit;
357 	ulong base;
358 } __attribute__((packed));
359 
360 static inline void clac(void)
361 {
362 	asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory");
363 }
364 
365 static inline void stac(void)
366 {
367 	asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory");
368 }
369 
370 static inline u16 read_cs(void)
371 {
372 	unsigned val;
373 
374 	asm volatile ("mov %%cs, %0" : "=mr"(val));
375 	return val;
376 }
377 
378 static inline u16 read_ds(void)
379 {
380 	unsigned val;
381 
382 	asm volatile ("mov %%ds, %0" : "=mr"(val));
383 	return val;
384 }
385 
386 static inline u16 read_es(void)
387 {
388 	unsigned val;
389 
390 	asm volatile ("mov %%es, %0" : "=mr"(val));
391 	return val;
392 }
393 
394 static inline u16 read_ss(void)
395 {
396 	unsigned val;
397 
398 	asm volatile ("mov %%ss, %0" : "=mr"(val));
399 	return val;
400 }
401 
402 static inline u16 read_fs(void)
403 {
404 	unsigned val;
405 
406 	asm volatile ("mov %%fs, %0" : "=mr"(val));
407 	return val;
408 }
409 
410 static inline u16 read_gs(void)
411 {
412 	unsigned val;
413 
414 	asm volatile ("mov %%gs, %0" : "=mr"(val));
415 	return val;
416 }
417 
418 static inline unsigned long read_rflags(void)
419 {
420 	unsigned long f;
421 	asm volatile ("pushf; pop %0\n\t" : "=rm"(f));
422 	return f;
423 }
424 
425 static inline void write_ds(unsigned val)
426 {
427 	asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory");
428 }
429 
430 static inline void write_es(unsigned val)
431 {
432 	asm volatile ("mov %0, %%es" : : "rm"(val) : "memory");
433 }
434 
435 static inline void write_ss(unsigned val)
436 {
437 	asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory");
438 }
439 
440 static inline void write_fs(unsigned val)
441 {
442 	asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory");
443 }
444 
445 static inline void write_gs(unsigned val)
446 {
447 	asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory");
448 }
449 
450 static inline void write_rflags(unsigned long f)
451 {
452 	asm volatile ("push %0; popf\n\t" : : "rm"(f));
453 }
454 
455 static inline void set_iopl(int iopl)
456 {
457 	unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL;
458 	flags |= iopl * (X86_EFLAGS_IOPL / 3);
459 	write_rflags(flags);
460 }
461 
462 /*
463  * Don't use the safe variants for rdmsr() or wrmsr().  The exception fixup
464  * infrastructure uses per-CPU data and thus consumes GS.base.  Various tests
465  * temporarily modify MSR_GS_BASE and will explode when trying to determine
466  * whether or not RDMSR/WRMSR faulted.
467  */
468 static inline u64 rdmsr(u32 index)
469 {
470 	u32 a, d;
471 	asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory");
472 	return a | ((u64)d << 32);
473 }
474 
475 static inline void wrmsr(u32 index, u64 val)
476 {
477 	u32 a = val, d = val >> 32;
478 	asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory");
479 }
480 
481 #define __rdreg64_safe(fep, insn, index, val)				\
482 ({									\
483 	uint32_t a, d;							\
484 	int vector;							\
485 									\
486 	vector = __asm_safe_out2(fep, insn, "=a"(a), "=d"(d), "c"(index));\
487 									\
488 	if (vector)							\
489 		*(val) = 0;						\
490 	else								\
491 		*(val) = (uint64_t)a | ((uint64_t)d << 32);		\
492 	vector;								\
493 })
494 
495 #define rdreg64_safe(insn, index, val)					\
496 	__rdreg64_safe("", insn, index, val)
497 
498 #define __wrreg64_safe(fep, insn, index, val)				\
499 ({									\
500 	uint32_t eax = (val), edx = (val) >> 32;			\
501 									\
502 	__asm_safe(fep, insn, "a" (eax), "d" (edx), "c" (index));	\
503 })
504 
505 #define wrreg64_safe(insn, index, val)					\
506 	__wrreg64_safe("", insn, index, val)
507 
508 static inline int rdmsr_safe(u32 index, uint64_t *val)
509 {
510 	return rdreg64_safe("rdmsr", index, val);
511 }
512 
513 static inline int rdmsr_fep_safe(u32 index, uint64_t *val)
514 {
515 	return __rdreg64_safe(KVM_FEP, "rdmsr", index, val);
516 }
517 
518 static inline int wrmsr_safe(u32 index, u64 val)
519 {
520 	return wrreg64_safe("wrmsr", index, val);
521 }
522 
523 static inline int wrmsr_fep_safe(u32 index, u64 val)
524 {
525 	return __wrreg64_safe(KVM_FEP, "wrmsr", index, val);
526 }
527 
528 static inline int rdpmc_safe(u32 index, uint64_t *val)
529 {
530 	return rdreg64_safe("rdpmc", index, val);
531 }
532 
533 static inline uint64_t rdpmc(uint32_t index)
534 {
535 	uint64_t val;
536 	int vector = rdpmc_safe(index, &val);
537 
538 	assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")",
539 		   exception_mnemonic(vector), index);
540 	return val;
541 }
542 
543 static inline int xgetbv_safe(u32 index, u64 *result)
544 {
545 	return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result);
546 }
547 
548 static inline int xsetbv_safe(u32 index, u64 value)
549 {
550 	return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value);
551 }
552 
553 static inline int write_cr0_safe(ulong val)
554 {
555 	return asm_safe("mov %0,%%cr0", "r" (val));
556 }
557 
558 static inline void write_cr0(ulong val)
559 {
560 	int vector = write_cr0_safe(val);
561 
562 	assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx",
563 		   vector, val);
564 }
565 
566 static inline ulong read_cr0(void)
567 {
568 	ulong val;
569 	asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory");
570 	return val;
571 }
572 
573 static inline void write_cr2(ulong val)
574 {
575 	asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory");
576 }
577 
578 static inline ulong read_cr2(void)
579 {
580 	ulong val;
581 	asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory");
582 	return val;
583 }
584 
585 static inline int write_cr3_safe(ulong val)
586 {
587 	return asm_safe("mov %0,%%cr3", "r" (val));
588 }
589 
590 static inline void write_cr3(ulong val)
591 {
592 	int vector = write_cr3_safe(val);
593 
594 	assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx",
595 		   vector, val);
596 }
597 
598 static inline ulong read_cr3(void)
599 {
600 	ulong val;
601 	asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory");
602 	return val;
603 }
604 
605 static inline void update_cr3(void *cr3)
606 {
607 	write_cr3((ulong)cr3);
608 }
609 
610 static inline int write_cr4_safe(ulong val)
611 {
612 	return asm_safe("mov %0,%%cr4", "r" (val));
613 }
614 
615 static inline void write_cr4(ulong val)
616 {
617 	int vector = write_cr4_safe(val);
618 
619 	assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx",
620 		   vector, val);
621 }
622 
623 static inline ulong read_cr4(void)
624 {
625 	ulong val;
626 	asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory");
627 	return val;
628 }
629 
630 static inline void write_cr8(ulong val)
631 {
632 	asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory");
633 }
634 
635 static inline ulong read_cr8(void)
636 {
637 	ulong val;
638 	asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory");
639 	return val;
640 }
641 
642 static inline void lgdt(const struct descriptor_table_ptr *ptr)
643 {
644 	asm volatile ("lgdt %0" : : "m"(*ptr));
645 }
646 
647 static inline int lgdt_safe(const struct descriptor_table_ptr *ptr)
648 {
649 	return asm_safe("lgdt %0", "m"(*ptr));
650 }
651 
652 static inline int lgdt_fep_safe(const struct descriptor_table_ptr *ptr)
653 {
654 	return asm_fep_safe("lgdt %0", "m"(*ptr));
655 }
656 
657 static inline void sgdt(struct descriptor_table_ptr *ptr)
658 {
659 	asm volatile ("sgdt %0" : "=m"(*ptr));
660 }
661 
662 static inline void lidt(const struct descriptor_table_ptr *ptr)
663 {
664 	asm volatile ("lidt %0" : : "m"(*ptr));
665 }
666 
667 static inline int lidt_safe(const struct descriptor_table_ptr *ptr)
668 {
669 	return asm_safe("lidt %0", "m"(*ptr));
670 }
671 
672 static inline int lidt_fep_safe(const struct descriptor_table_ptr *ptr)
673 {
674 	return asm_fep_safe("lidt %0", "m"(*ptr));
675 }
676 
677 static inline void sidt(struct descriptor_table_ptr *ptr)
678 {
679 	asm volatile ("sidt %0" : "=m"(*ptr));
680 }
681 
682 static inline void lldt(u16 val)
683 {
684 	asm volatile ("lldt %0" : : "rm"(val));
685 }
686 
687 static inline int lldt_safe(u16 val)
688 {
689 	return asm_safe("lldt %0", "rm"(val));
690 }
691 
692 static inline int lldt_fep_safe(u16 val)
693 {
694 	return asm_safe("lldt %0", "rm"(val));
695 }
696 
697 static inline u16 sldt(void)
698 {
699 	u16 val;
700 	asm volatile ("sldt %0" : "=rm"(val));
701 	return val;
702 }
703 
704 static inline void ltr(u16 val)
705 {
706 	asm volatile ("ltr %0" : : "rm"(val));
707 }
708 
709 static inline int ltr_safe(u16 val)
710 {
711 	return asm_safe("ltr %0", "rm"(val));
712 }
713 
714 static inline int ltr_fep_safe(u16 val)
715 {
716 	return asm_safe("ltr %0", "rm"(val));
717 }
718 
719 static inline u16 str(void)
720 {
721 	u16 val;
722 	asm volatile ("str %0" : "=rm"(val));
723 	return val;
724 }
725 
726 static inline void write_dr0(void *val)
727 {
728 	asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory");
729 }
730 
731 static inline void write_dr1(void *val)
732 {
733 	asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory");
734 }
735 
736 static inline void write_dr2(void *val)
737 {
738 	asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory");
739 }
740 
741 static inline void write_dr3(void *val)
742 {
743 	asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory");
744 }
745 
746 static inline void write_dr6(ulong val)
747 {
748 	asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory");
749 }
750 
751 static inline ulong read_dr6(void)
752 {
753 	ulong val;
754 	asm volatile ("mov %%dr6, %0" : "=r"(val));
755 	return val;
756 }
757 
758 static inline void write_dr7(ulong val)
759 {
760 	asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory");
761 }
762 
763 static inline ulong read_dr7(void)
764 {
765 	ulong val;
766 	asm volatile ("mov %%dr7, %0" : "=r"(val));
767 	return val;
768 }
769 
770 static inline void pause(void)
771 {
772 	asm volatile ("pause");
773 }
774 
775 static inline void cli(void)
776 {
777 	asm volatile ("cli");
778 }
779 
780 /*
781  * See also safe_halt().
782  */
783 static inline void sti(void)
784 {
785 	asm volatile ("sti");
786 }
787 
788 /*
789  * Enable interrupts and ensure that interrupts are evaluated upon return from
790  * this function, i.e. execute a nop to consume the STi interrupt shadow.
791  */
792 static inline void sti_nop(void)
793 {
794 	asm volatile ("sti; nop");
795 }
796 
797 /*
798  * Enable interrupts for one instruction (nop), to allow the CPU to process all
799  * interrupts that are already pending.
800  */
801 static inline void sti_nop_cli(void)
802 {
803 	asm volatile ("sti; nop; cli");
804 }
805 
806 static inline unsigned long long rdrand(void)
807 {
808 	long long r;
809 
810 	asm volatile("rdrand %0\n\t"
811 		     "jc 1f\n\t"
812 		     "mov $0, %0\n\t"
813 		     "1:\n\t" : "=r" (r));
814 	return r;
815 }
816 
817 static inline unsigned long long rdtsc(void)
818 {
819 	long long r;
820 
821 #ifdef __x86_64__
822 	unsigned a, d;
823 
824 	asm volatile ("rdtsc" : "=a"(a), "=d"(d));
825 	r = a | ((long long)d << 32);
826 #else
827 	asm volatile ("rdtsc" : "=A"(r));
828 #endif
829 	return r;
830 }
831 
832 /*
833  * Per the advice in the SDM, volume 2, the sequence "mfence; lfence"
834  * executed immediately before rdtsc ensures that rdtsc will be
835  * executed only after all previous instructions have executed and all
836  * previous loads and stores are globally visible. In addition, the
837  * lfence immediately after rdtsc ensures that rdtsc will be executed
838  * prior to the execution of any subsequent instruction.
839  */
840 static inline unsigned long long fenced_rdtsc(void)
841 {
842 	unsigned long long tsc;
843 
844 #ifdef __x86_64__
845 	unsigned int eax, edx;
846 
847 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
848 	tsc = eax | ((unsigned long long)edx << 32);
849 #else
850 	asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc));
851 #endif
852 	return tsc;
853 }
854 
855 static inline unsigned long long rdtscp(u32 *aux)
856 {
857 	long long r;
858 
859 #ifdef __x86_64__
860 	unsigned a, d;
861 
862 	asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux));
863 	r = a | ((long long)d << 32);
864 #else
865 	asm volatile ("rdtscp" : "=A"(r), "=c"(*aux));
866 #endif
867 	return r;
868 }
869 
870 static inline void wrtsc(u64 tsc)
871 {
872 	wrmsr(MSR_IA32_TSC, tsc);
873 }
874 
875 
876 static inline void invlpg(volatile void *va)
877 {
878 	asm volatile("invlpg (%0)" ::"r" (va) : "memory");
879 }
880 
881 struct invpcid_desc {
882 	u64 pcid : 12;
883 	u64 rsv  : 52;
884 	u64 addr : 64;
885 };
886 
887 static inline int invpcid_safe(unsigned long type, struct invpcid_desc *desc)
888 {
889 	/* invpcid (%rax), %rbx */
890 	return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type));
891 }
892 
893 /*
894  * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's
895  * intended to be a wake event arrives *after* HLT is executed.  Modern CPUs,
896  * except for a few oddballs that KVM is unlikely to run on, block IRQs for one
897  * instruction after STI, *if* RFLAGS.IF=0 before STI.  Note, Intel CPUs may
898  * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too.
899  */
900 static inline void safe_halt(void)
901 {
902 	asm volatile("sti; hlt");
903 }
904 
905 static inline u32 read_pkru(void)
906 {
907 	unsigned int eax, edx;
908 	unsigned int ecx = 0;
909 	unsigned int pkru;
910 
911 	asm volatile(".byte 0x0f,0x01,0xee\n\t"
912 		     : "=a" (eax), "=d" (edx)
913 		     : "c" (ecx));
914 	pkru = eax;
915 	return pkru;
916 }
917 
918 static inline void write_pkru(u32 pkru)
919 {
920 	unsigned int eax = pkru;
921 	unsigned int ecx = 0;
922 	unsigned int edx = 0;
923 
924 	asm volatile(".byte 0x0f,0x01,0xef\n\t"
925 		     : : "a" (eax), "c" (ecx), "d" (edx));
926 }
927 
928 static inline bool is_canonical(u64 addr)
929 {
930 	int va_width = (raw_cpuid(0x80000008, 0).a & 0xff00) >> 8;
931 	int shift_amt = 64 - va_width;
932 
933 	return (s64)(addr << shift_amt) >> shift_amt == addr;
934 }
935 
936 static inline void flush_tlb(void)
937 {
938 	ulong cr4;
939 
940 	cr4 = read_cr4();
941 	write_cr4(cr4 ^ X86_CR4_PGE);
942 	write_cr4(cr4);
943 }
944 
945 static inline void generate_non_canonical_gp(void)
946 {
947 	*(volatile u64 *)NONCANONICAL = 0;
948 }
949 
950 static inline void generate_ud(void)
951 {
952 	asm volatile ("ud2");
953 }
954 
955 static inline void generate_de(void)
956 {
957 	asm volatile (
958 		"xor %%eax, %%eax\n\t"
959 		"xor %%ebx, %%ebx\n\t"
960 		"xor %%edx, %%edx\n\t"
961 		"idiv %%ebx\n\t"
962 		::: "eax", "ebx", "edx");
963 }
964 
965 static inline void generate_bp(void)
966 {
967 	asm volatile ("int3");
968 }
969 
970 static inline void generate_single_step_db(void)
971 {
972 	write_rflags(read_rflags() | X86_EFLAGS_TF);
973 	asm volatile("nop");
974 }
975 
976 static inline uint64_t generate_usermode_ac(void)
977 {
978 	/*
979 	 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address.
980 	 * Disclaimer: It is assumed that the stack pointer is aligned
981 	 * on a 16-byte boundary as x86_64 stacks should be.
982 	 */
983 	asm volatile("movq $0, -0x4(%rsp)");
984 
985 	return 0;
986 }
987 
988 /*
989  * Switch from 64-bit to 32-bit mode and generate #OF via INTO.  Note, if RIP
990  * or RSP holds a 64-bit value, this helper will NOT generate #OF.
991  */
992 static inline void generate_of(void)
993 {
994 	struct far_pointer32 fp = {
995 		.offset = (uintptr_t)&&into,
996 		.selector = KERNEL_CS32,
997 	};
998 	uintptr_t rsp;
999 
1000 	asm volatile ("mov %%rsp, %0" : "=r"(rsp));
1001 
1002 	if (fp.offset != (uintptr_t)&&into) {
1003 		printf("Code address too high.\n");
1004 		return;
1005 	}
1006 	if ((u32)rsp != rsp) {
1007 		printf("Stack address too high.\n");
1008 		return;
1009 	}
1010 
1011 	asm goto ("lcall *%0" : : "m" (fp) : "rax" : into);
1012 	return;
1013 into:
1014 	asm volatile (".code32;"
1015 		      "movl $0x7fffffff, %eax;"
1016 		      "addl %eax, %eax;"
1017 		      "into;"
1018 		      "lret;"
1019 		      ".code64");
1020 	__builtin_unreachable();
1021 }
1022 
1023 static inline void fnop(void)
1024 {
1025 	asm volatile("fnop");
1026 }
1027 
1028 /* If CR0.TS is set in L2, #NM is generated. */
1029 static inline void generate_cr0_ts_nm(void)
1030 {
1031 	write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS);
1032 	fnop();
1033 }
1034 
1035 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */
1036 static inline void generate_cr0_em_nm(void)
1037 {
1038 	write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM);
1039 	fnop();
1040 }
1041 
1042 static inline bool is_la57_enabled(void)
1043 {
1044 	return !!(read_cr4() & X86_CR4_LA57);
1045 }
1046 
1047 static inline bool is_lam_sup_enabled(void)
1048 {
1049 	return !!(read_cr4() & X86_CR4_LAM_SUP);
1050 }
1051 
1052 static inline bool is_lam_u48_enabled(void)
1053 {
1054 	return (read_cr3() & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)) == X86_CR3_LAM_U48;
1055 }
1056 
1057 static inline bool is_lam_u57_enabled(void)
1058 {
1059 	return !!(read_cr3() & X86_CR3_LAM_U57);
1060 }
1061 
1062 #endif
1063