1 #ifndef LIBCFLAT_PROCESSOR_H 2 #define LIBCFLAT_PROCESSOR_H 3 4 #include "libcflat.h" 5 #include "msr.h" 6 #include <stdint.h> 7 8 #ifdef __x86_64__ 9 # define R "r" 10 # define W "q" 11 # define S "8" 12 #else 13 # define R "e" 14 # define W "l" 15 # define S "4" 16 #endif 17 18 #define DB_VECTOR 1 19 #define BP_VECTOR 3 20 #define UD_VECTOR 6 21 #define DF_VECTOR 8 22 #define TS_VECTOR 10 23 #define NP_VECTOR 11 24 #define SS_VECTOR 12 25 #define GP_VECTOR 13 26 #define PF_VECTOR 14 27 #define AC_VECTOR 17 28 29 #define X86_CR0_PE 0x00000001 30 #define X86_CR0_MP 0x00000002 31 #define X86_CR0_EM 0x00000004 32 #define X86_CR0_TS 0x00000008 33 #define X86_CR0_WP 0x00010000 34 #define X86_CR0_AM 0x00040000 35 #define X86_CR0_NW 0x20000000 36 #define X86_CR0_CD 0x40000000 37 #define X86_CR0_PG 0x80000000 38 #define X86_CR3_PCID_MASK 0x00000fff 39 #define X86_CR4_TSD 0x00000004 40 #define X86_CR4_DE 0x00000008 41 #define X86_CR4_PSE 0x00000010 42 #define X86_CR4_PAE 0x00000020 43 #define X86_CR4_MCE 0x00000040 44 #define X86_CR4_PGE 0x00000080 45 #define X86_CR4_PCE 0x00000100 46 #define X86_CR4_UMIP 0x00000800 47 #define X86_CR4_VMXE 0x00002000 48 #define X86_CR4_PCIDE 0x00020000 49 #define X86_CR4_SMEP 0x00100000 50 #define X86_CR4_SMAP 0x00200000 51 #define X86_CR4_PKE 0x00400000 52 53 #define X86_EFLAGS_CF 0x00000001 54 #define X86_EFLAGS_FIXED 0x00000002 55 #define X86_EFLAGS_PF 0x00000004 56 #define X86_EFLAGS_AF 0x00000010 57 #define X86_EFLAGS_ZF 0x00000040 58 #define X86_EFLAGS_SF 0x00000080 59 #define X86_EFLAGS_TF 0x00000100 60 #define X86_EFLAGS_IF 0x00000200 61 #define X86_EFLAGS_DF 0x00000400 62 #define X86_EFLAGS_OF 0x00000800 63 #define X86_EFLAGS_IOPL 0x00003000 64 #define X86_EFLAGS_NT 0x00004000 65 #define X86_EFLAGS_AC 0x00040000 66 67 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 68 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 69 70 #define X86_IA32_EFER 0xc0000080 71 #define X86_EFER_LMA (1UL << 8) 72 73 /* 74 * CPU features 75 */ 76 77 enum cpuid_output_regs { 78 EAX, 79 EBX, 80 ECX, 81 EDX 82 }; 83 84 struct cpuid { u32 a, b, c, d; }; 85 86 static inline struct cpuid raw_cpuid(u32 function, u32 index) 87 { 88 struct cpuid r; 89 asm volatile ("cpuid" 90 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 91 : "0"(function), "2"(index)); 92 return r; 93 } 94 95 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 96 { 97 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 98 if (level < function) 99 return (struct cpuid) { 0, 0, 0, 0 }; 100 return raw_cpuid(function, index); 101 } 102 103 static inline struct cpuid cpuid(u32 function) 104 { 105 return cpuid_indexed(function, 0); 106 } 107 108 static inline u8 cpuid_maxphyaddr(void) 109 { 110 if (raw_cpuid(0x80000000, 0).a < 0x80000008) 111 return 36; 112 return raw_cpuid(0x80000008, 0).a & 0xff; 113 } 114 115 #define CPUID(a, b, c, d) ((((unsigned long long) a) << 32) | (b << 16) | \ 116 (c << 8) | d) 117 118 /* 119 * Each X86_FEATURE_XXX definition is 64-bit and contains the following 120 * CPUID meta-data: 121 * 122 * [63:32] : input value for EAX 123 * [31:16] : input value for ECX 124 * [15:8] : output register 125 * [7:0] : bit position in output register 126 */ 127 128 /* 129 * Intel CPUID features 130 */ 131 #define X86_FEATURE_MWAIT (CPUID(0x1, 0, ECX, 3)) 132 #define X86_FEATURE_VMX (CPUID(0x1, 0, ECX, 5)) 133 #define X86_FEATURE_PCID (CPUID(0x1, 0, ECX, 17)) 134 #define X86_FEATURE_MOVBE (CPUID(0x1, 0, ECX, 22)) 135 #define X86_FEATURE_TSC_DEADLINE_TIMER (CPUID(0x1, 0, ECX, 24)) 136 #define X86_FEATURE_XSAVE (CPUID(0x1, 0, ECX, 26)) 137 #define X86_FEATURE_OSXSAVE (CPUID(0x1, 0, ECX, 27)) 138 #define X86_FEATURE_RDRAND (CPUID(0x1, 0, ECX, 30)) 139 #define X86_FEATURE_MCE (CPUID(0x1, 0, EDX, 7)) 140 #define X86_FEATURE_APIC (CPUID(0x1, 0, EDX, 9)) 141 #define X86_FEATURE_CLFLUSH (CPUID(0x1, 0, EDX, 19)) 142 #define X86_FEATURE_XMM (CPUID(0x1, 0, EDX, 25)) 143 #define X86_FEATURE_XMM2 (CPUID(0x1, 0, EDX, 26)) 144 #define X86_FEATURE_TSC_ADJUST (CPUID(0x7, 0, EBX, 1)) 145 #define X86_FEATURE_HLE (CPUID(0x7, 0, EBX, 4)) 146 #define X86_FEATURE_SMEP (CPUID(0x7, 0, EBX, 7)) 147 #define X86_FEATURE_INVPCID (CPUID(0x7, 0, EBX, 10)) 148 #define X86_FEATURE_RTM (CPUID(0x7, 0, EBX, 11)) 149 #define X86_FEATURE_SMAP (CPUID(0x7, 0, EBX, 20)) 150 #define X86_FEATURE_PCOMMIT (CPUID(0x7, 0, EBX, 22)) 151 #define X86_FEATURE_CLFLUSHOPT (CPUID(0x7, 0, EBX, 23)) 152 #define X86_FEATURE_CLWB (CPUID(0x7, 0, EBX, 24)) 153 #define X86_FEATURE_UMIP (CPUID(0x7, 0, ECX, 2)) 154 #define X86_FEATURE_PKU (CPUID(0x7, 0, ECX, 3)) 155 #define X86_FEATURE_LA57 (CPUID(0x7, 0, ECX, 16)) 156 #define X86_FEATURE_RDPID (CPUID(0x7, 0, ECX, 22)) 157 #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) 158 #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) 159 #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) 160 #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) 161 162 /* 163 * AMD CPUID features 164 */ 165 #define X86_FEATURE_SVM (CPUID(0x80000001, 0, ECX, 2)) 166 #define X86_FEATURE_RDTSCP (CPUID(0x80000001, 0, EDX, 27)) 167 #define X86_FEATURE_AMD_IBPB (CPUID(0x80000008, 0, EBX, 12)) 168 #define X86_FEATURE_NPT (CPUID(0x8000000A, 0, EDX, 0)) 169 #define X86_FEATURE_NRIPS (CPUID(0x8000000A, 0, EDX, 3)) 170 171 172 static inline bool this_cpu_has(u64 feature) 173 { 174 u32 input_eax = feature >> 32; 175 u32 input_ecx = (feature >> 16) & 0xffff; 176 u32 output_reg = (feature >> 8) & 0xff; 177 u8 bit = feature & 0xff; 178 struct cpuid c; 179 u32 *tmp; 180 181 c = cpuid_indexed(input_eax, input_ecx); 182 tmp = (u32 *)&c; 183 184 return ((*(tmp + (output_reg % 32))) & (1 << bit)); 185 } 186 187 struct far_pointer32 { 188 u32 offset; 189 u16 selector; 190 } __attribute__((packed)); 191 192 struct descriptor_table_ptr { 193 u16 limit; 194 ulong base; 195 } __attribute__((packed)); 196 197 static inline void barrier(void) 198 { 199 asm volatile ("" : : : "memory"); 200 } 201 202 static inline void clac(void) 203 { 204 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 205 } 206 207 static inline void stac(void) 208 { 209 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 210 } 211 212 static inline u16 read_cs(void) 213 { 214 unsigned val; 215 216 asm volatile ("mov %%cs, %0" : "=mr"(val)); 217 return val; 218 } 219 220 static inline u16 read_ds(void) 221 { 222 unsigned val; 223 224 asm volatile ("mov %%ds, %0" : "=mr"(val)); 225 return val; 226 } 227 228 static inline u16 read_es(void) 229 { 230 unsigned val; 231 232 asm volatile ("mov %%es, %0" : "=mr"(val)); 233 return val; 234 } 235 236 static inline u16 read_ss(void) 237 { 238 unsigned val; 239 240 asm volatile ("mov %%ss, %0" : "=mr"(val)); 241 return val; 242 } 243 244 static inline u16 read_fs(void) 245 { 246 unsigned val; 247 248 asm volatile ("mov %%fs, %0" : "=mr"(val)); 249 return val; 250 } 251 252 static inline u16 read_gs(void) 253 { 254 unsigned val; 255 256 asm volatile ("mov %%gs, %0" : "=mr"(val)); 257 return val; 258 } 259 260 static inline unsigned long read_rflags(void) 261 { 262 unsigned long f; 263 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 264 return f; 265 } 266 267 static inline void write_ds(unsigned val) 268 { 269 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 270 } 271 272 static inline void write_es(unsigned val) 273 { 274 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 275 } 276 277 static inline void write_ss(unsigned val) 278 { 279 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 280 } 281 282 static inline void write_fs(unsigned val) 283 { 284 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 285 } 286 287 static inline void write_gs(unsigned val) 288 { 289 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 290 } 291 292 static inline void write_rflags(unsigned long f) 293 { 294 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 295 } 296 297 static inline void set_iopl(int iopl) 298 { 299 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 300 flags |= iopl * (X86_EFLAGS_IOPL / 3); 301 write_rflags(flags); 302 } 303 304 static inline u64 rdmsr(u32 index) 305 { 306 u32 a, d; 307 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 308 return a | ((u64)d << 32); 309 } 310 311 static inline void wrmsr(u32 index, u64 val) 312 { 313 u32 a = val, d = val >> 32; 314 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 315 } 316 317 static inline uint64_t rdpmc(uint32_t index) 318 { 319 uint32_t a, d; 320 asm volatile ("rdpmc" : "=a"(a), "=d"(d) : "c"(index)); 321 return a | ((uint64_t)d << 32); 322 } 323 324 static inline void write_cr0(ulong val) 325 { 326 asm volatile ("mov %0, %%cr0" : : "r"(val) : "memory"); 327 } 328 329 static inline ulong read_cr0(void) 330 { 331 ulong val; 332 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 333 return val; 334 } 335 336 static inline void write_cr2(ulong val) 337 { 338 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 339 } 340 341 static inline ulong read_cr2(void) 342 { 343 ulong val; 344 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 345 return val; 346 } 347 348 static inline void write_cr3(ulong val) 349 { 350 asm volatile ("mov %0, %%cr3" : : "r"(val) : "memory"); 351 } 352 353 static inline ulong read_cr3(void) 354 { 355 ulong val; 356 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 357 return val; 358 } 359 360 static inline void write_cr4(ulong val) 361 { 362 asm volatile ("mov %0, %%cr4" : : "r"(val) : "memory"); 363 } 364 365 static inline ulong read_cr4(void) 366 { 367 ulong val; 368 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 369 return val; 370 } 371 372 static inline void write_cr8(ulong val) 373 { 374 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 375 } 376 377 static inline ulong read_cr8(void) 378 { 379 ulong val; 380 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 381 return val; 382 } 383 384 static inline void lgdt(const struct descriptor_table_ptr *ptr) 385 { 386 asm volatile ("lgdt %0" : : "m"(*ptr)); 387 } 388 389 static inline void sgdt(struct descriptor_table_ptr *ptr) 390 { 391 asm volatile ("sgdt %0" : "=m"(*ptr)); 392 } 393 394 static inline void lidt(const struct descriptor_table_ptr *ptr) 395 { 396 asm volatile ("lidt %0" : : "m"(*ptr)); 397 } 398 399 static inline void sidt(struct descriptor_table_ptr *ptr) 400 { 401 asm volatile ("sidt %0" : "=m"(*ptr)); 402 } 403 404 static inline void lldt(unsigned val) 405 { 406 asm volatile ("lldt %0" : : "rm"(val)); 407 } 408 409 static inline u16 sldt(void) 410 { 411 u16 val; 412 asm volatile ("sldt %0" : "=rm"(val)); 413 return val; 414 } 415 416 static inline void ltr(u16 val) 417 { 418 asm volatile ("ltr %0" : : "rm"(val)); 419 } 420 421 static inline u16 str(void) 422 { 423 u16 val; 424 asm volatile ("str %0" : "=rm"(val)); 425 return val; 426 } 427 428 static inline void write_dr6(ulong val) 429 { 430 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 431 } 432 433 static inline ulong read_dr6(void) 434 { 435 ulong val; 436 asm volatile ("mov %%dr6, %0" : "=r"(val)); 437 return val; 438 } 439 440 static inline void write_dr7(ulong val) 441 { 442 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 443 } 444 445 static inline ulong read_dr7(void) 446 { 447 ulong val; 448 asm volatile ("mov %%dr7, %0" : "=r"(val)); 449 return val; 450 } 451 452 static inline void pause(void) 453 { 454 asm volatile ("pause"); 455 } 456 457 static inline void cli(void) 458 { 459 asm volatile ("cli"); 460 } 461 462 static inline void sti(void) 463 { 464 asm volatile ("sti"); 465 } 466 467 static inline unsigned long long rdtsc(void) 468 { 469 long long r; 470 471 #ifdef __x86_64__ 472 unsigned a, d; 473 474 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 475 r = a | ((long long)d << 32); 476 #else 477 asm volatile ("rdtsc" : "=A"(r)); 478 #endif 479 return r; 480 } 481 482 static inline unsigned long long rdtscp(u32 *aux) 483 { 484 long long r; 485 486 #ifdef __x86_64__ 487 unsigned a, d; 488 489 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 490 r = a | ((long long)d << 32); 491 #else 492 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 493 #endif 494 return r; 495 } 496 497 static inline void wrtsc(u64 tsc) 498 { 499 unsigned a = tsc, d = tsc >> 32; 500 501 asm volatile("wrmsr" : : "a"(a), "d"(d), "c"(0x10)); 502 } 503 504 static inline void irq_disable(void) 505 { 506 asm volatile("cli"); 507 } 508 509 /* Note that irq_enable() does not ensure an interrupt shadow due 510 * to the vagaries of compiler optimizations. If you need the 511 * shadow, use a single asm with "sti" and the instruction after it. 512 */ 513 static inline void irq_enable(void) 514 { 515 asm volatile("sti"); 516 } 517 518 static inline void invlpg(volatile void *va) 519 { 520 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 521 } 522 523 static inline void safe_halt(void) 524 { 525 asm volatile("sti; hlt"); 526 } 527 528 static inline u32 read_pkru(void) 529 { 530 unsigned int eax, edx; 531 unsigned int ecx = 0; 532 unsigned int pkru; 533 534 asm volatile(".byte 0x0f,0x01,0xee\n\t" 535 : "=a" (eax), "=d" (edx) 536 : "c" (ecx)); 537 pkru = eax; 538 return pkru; 539 } 540 541 static inline void write_pkru(u32 pkru) 542 { 543 unsigned int eax = pkru; 544 unsigned int ecx = 0; 545 unsigned int edx = 0; 546 547 asm volatile(".byte 0x0f,0x01,0xef\n\t" 548 : : "a" (eax), "c" (ecx), "d" (edx)); 549 } 550 551 static inline bool is_canonical(u64 addr) 552 { 553 return (s64)(addr << 16) >> 16 == addr; 554 } 555 556 static inline void clear_bit(int bit, u8 *addr) 557 { 558 __asm__ __volatile__("btr %1, %0" 559 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 560 } 561 562 static inline void set_bit(int bit, u8 *addr) 563 { 564 __asm__ __volatile__("bts %1, %0" 565 : "+m" (*addr) : "Ir" (bit) : "cc", "memory"); 566 } 567 568 static inline void flush_tlb(void) 569 { 570 ulong cr4; 571 572 cr4 = read_cr4(); 573 write_cr4(cr4 ^ X86_CR4_PGE); 574 write_cr4(cr4); 575 } 576 577 static inline int has_spec_ctrl(void) 578 { 579 return !!(this_cpu_has(X86_FEATURE_SPEC_CTRL)); 580 } 581 582 static inline int cpu_has_efer_nx(void) 583 { 584 return !!(this_cpu_has(X86_FEATURE_NX)); 585 } 586 587 #endif 588