1 #ifndef _X86_PROCESSOR_H_ 2 #define _X86_PROCESSOR_H_ 3 4 #include "libcflat.h" 5 #include "desc.h" 6 #include "msr.h" 7 #include <bitops.h> 8 #include <stdint.h> 9 #include <util.h> 10 11 #define CANONICAL_48_VAL 0xffffaaaaaaaaaaaaull 12 #define CANONICAL_57_VAL 0xffaaaaaaaaaaaaaaull 13 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 14 15 #define LAM57_MASK GENMASK_ULL(62, 57) 16 #define LAM48_MASK GENMASK_ULL(62, 48) 17 18 /* 19 * Get a linear address by combining @addr with a non-canonical pattern in the 20 * @mask bits. 21 */ 22 static inline u64 get_non_canonical(u64 addr, u64 mask) 23 { 24 return (addr & ~mask) | (NONCANONICAL & mask); 25 } 26 27 #ifdef __x86_64__ 28 # define R "r" 29 # define W "q" 30 # define S "8" 31 #else 32 # define R "e" 33 # define W "l" 34 # define S "4" 35 #endif 36 37 #define DE_VECTOR 0 38 #define DB_VECTOR 1 39 #define NMI_VECTOR 2 40 #define BP_VECTOR 3 41 #define OF_VECTOR 4 42 #define BR_VECTOR 5 43 #define UD_VECTOR 6 44 #define NM_VECTOR 7 45 #define DF_VECTOR 8 46 #define TS_VECTOR 10 47 #define NP_VECTOR 11 48 #define SS_VECTOR 12 49 #define GP_VECTOR 13 50 #define PF_VECTOR 14 51 #define MF_VECTOR 16 52 #define AC_VECTOR 17 53 #define MC_VECTOR 18 54 #define XM_VECTOR 19 55 #define XF_VECTOR XM_VECTOR /* AMD */ 56 #define VE_VECTOR 20 /* Intel only */ 57 #define CP_VECTOR 21 58 #define HV_VECTOR 28 /* AMD only */ 59 #define VC_VECTOR 29 /* AMD only */ 60 #define SX_VECTOR 30 /* AMD only */ 61 62 #define X86_CR0_PE_BIT (0) 63 #define X86_CR0_PE BIT(X86_CR0_PE_BIT) 64 #define X86_CR0_MP_BIT (1) 65 #define X86_CR0_MP BIT(X86_CR0_MP_BIT) 66 #define X86_CR0_EM_BIT (2) 67 #define X86_CR0_EM BIT(X86_CR0_EM_BIT) 68 #define X86_CR0_TS_BIT (3) 69 #define X86_CR0_TS BIT(X86_CR0_TS_BIT) 70 #define X86_CR0_ET_BIT (4) 71 #define X86_CR0_ET BIT(X86_CR0_ET_BIT) 72 #define X86_CR0_NE_BIT (5) 73 #define X86_CR0_NE BIT(X86_CR0_NE_BIT) 74 #define X86_CR0_WP_BIT (16) 75 #define X86_CR0_WP BIT(X86_CR0_WP_BIT) 76 #define X86_CR0_AM_BIT (18) 77 #define X86_CR0_AM BIT(X86_CR0_AM_BIT) 78 #define X86_CR0_NW_BIT (29) 79 #define X86_CR0_NW BIT(X86_CR0_NW_BIT) 80 #define X86_CR0_CD_BIT (30) 81 #define X86_CR0_CD BIT(X86_CR0_CD_BIT) 82 #define X86_CR0_PG_BIT (31) 83 #define X86_CR0_PG BIT(X86_CR0_PG_BIT) 84 85 #define X86_CR3_PCID_MASK GENMASK(11, 0) 86 #define X86_CR3_LAM_U57_BIT (61) 87 #define X86_CR3_LAM_U57 BIT_ULL(X86_CR3_LAM_U57_BIT) 88 #define X86_CR3_LAM_U48_BIT (62) 89 #define X86_CR3_LAM_U48 BIT_ULL(X86_CR3_LAM_U48_BIT) 90 91 #define X86_CR4_VME_BIT (0) 92 #define X86_CR4_VME BIT(X86_CR4_VME_BIT) 93 #define X86_CR4_PVI_BIT (1) 94 #define X86_CR4_PVI BIT(X86_CR4_PVI_BIT) 95 #define X86_CR4_TSD_BIT (2) 96 #define X86_CR4_TSD BIT(X86_CR4_TSD_BIT) 97 #define X86_CR4_DE_BIT (3) 98 #define X86_CR4_DE BIT(X86_CR4_DE_BIT) 99 #define X86_CR4_PSE_BIT (4) 100 #define X86_CR4_PSE BIT(X86_CR4_PSE_BIT) 101 #define X86_CR4_PAE_BIT (5) 102 #define X86_CR4_PAE BIT(X86_CR4_PAE_BIT) 103 #define X86_CR4_MCE_BIT (6) 104 #define X86_CR4_MCE BIT(X86_CR4_MCE_BIT) 105 #define X86_CR4_PGE_BIT (7) 106 #define X86_CR4_PGE BIT(X86_CR4_PGE_BIT) 107 #define X86_CR4_PCE_BIT (8) 108 #define X86_CR4_PCE BIT(X86_CR4_PCE_BIT) 109 #define X86_CR4_OSFXSR_BIT (9) 110 #define X86_CR4_OSFXSR BIT(X86_CR4_OSFXSR_BIT) 111 #define X86_CR4_OSXMMEXCPT_BIT (10) 112 #define X86_CR4_OSXMMEXCPT BIT(X86_CR4_OSXMMEXCPT_BIT) 113 #define X86_CR4_UMIP_BIT (11) 114 #define X86_CR4_UMIP BIT(X86_CR4_UMIP_BIT) 115 #define X86_CR4_LA57_BIT (12) 116 #define X86_CR4_LA57 BIT(X86_CR4_LA57_BIT) 117 #define X86_CR4_VMXE_BIT (13) 118 #define X86_CR4_VMXE BIT(X86_CR4_VMXE_BIT) 119 #define X86_CR4_SMXE_BIT (14) 120 #define X86_CR4_SMXE BIT(X86_CR4_SMXE_BIT) 121 /* UNUSED (15) */ 122 #define X86_CR4_FSGSBASE_BIT (16) 123 #define X86_CR4_FSGSBASE BIT(X86_CR4_FSGSBASE_BIT) 124 #define X86_CR4_PCIDE_BIT (17) 125 #define X86_CR4_PCIDE BIT(X86_CR4_PCIDE_BIT) 126 #define X86_CR4_OSXSAVE_BIT (18) 127 #define X86_CR4_OSXSAVE BIT(X86_CR4_OSXSAVE_BIT) 128 #define X86_CR4_KL_BIT (19) 129 #define X86_CR4_KL BIT(X86_CR4_KL_BIT) 130 #define X86_CR4_SMEP_BIT (20) 131 #define X86_CR4_SMEP BIT(X86_CR4_SMEP_BIT) 132 #define X86_CR4_SMAP_BIT (21) 133 #define X86_CR4_SMAP BIT(X86_CR4_SMAP_BIT) 134 #define X86_CR4_PKE_BIT (22) 135 #define X86_CR4_PKE BIT(X86_CR4_PKE_BIT) 136 #define X86_CR4_CET_BIT (23) 137 #define X86_CR4_CET BIT(X86_CR4_CET_BIT) 138 #define X86_CR4_PKS_BIT (24) 139 #define X86_CR4_PKS BIT(X86_CR4_PKS_BIT) 140 #define X86_CR4_LAM_SUP_BIT (28) 141 #define X86_CR4_LAM_SUP BIT(X86_CR4_LAM_SUP_BIT) 142 143 #define X86_EFLAGS_CF_BIT (0) 144 #define X86_EFLAGS_CF BIT(X86_EFLAGS_CF_BIT) 145 #define X86_EFLAGS_FIXED_BIT (1) 146 #define X86_EFLAGS_FIXED BIT(X86_EFLAGS_FIXED_BIT) 147 #define X86_EFLAGS_PF_BIT (2) 148 #define X86_EFLAGS_PF BIT(X86_EFLAGS_PF_BIT) 149 /* RESERVED 0 (3) */ 150 #define X86_EFLAGS_AF_BIT (4) 151 #define X86_EFLAGS_AF BIT(X86_EFLAGS_AF_BIT) 152 /* RESERVED 0 (5) */ 153 #define X86_EFLAGS_ZF_BIT (6) 154 #define X86_EFLAGS_ZF BIT(X86_EFLAGS_ZF_BIT) 155 #define X86_EFLAGS_SF_BIT (7) 156 #define X86_EFLAGS_SF BIT(X86_EFLAGS_SF_BIT) 157 #define X86_EFLAGS_TF_BIT (8) 158 #define X86_EFLAGS_TF BIT(X86_EFLAGS_TF_BIT) 159 #define X86_EFLAGS_IF_BIT (9) 160 #define X86_EFLAGS_IF BIT(X86_EFLAGS_IF_BIT) 161 #define X86_EFLAGS_DF_BIT (10) 162 #define X86_EFLAGS_DF BIT(X86_EFLAGS_DF_BIT) 163 #define X86_EFLAGS_OF_BIT (11) 164 #define X86_EFLAGS_OF BIT(X86_EFLAGS_OF_BIT) 165 #define X86_EFLAGS_IOPL GENMASK(13, 12) 166 #define X86_EFLAGS_NT_BIT (14) 167 #define X86_EFLAGS_NT BIT(X86_EFLAGS_NT_BIT) 168 /* RESERVED 0 (15) */ 169 #define X86_EFLAGS_RF_BIT (16) 170 #define X86_EFLAGS_RF BIT(X86_EFLAGS_RF_BIT) 171 #define X86_EFLAGS_VM_BIT (17) 172 #define X86_EFLAGS_VM BIT(X86_EFLAGS_VM_BIT) 173 #define X86_EFLAGS_AC_BIT (18) 174 #define X86_EFLAGS_AC BIT(X86_EFLAGS_AC_BIT) 175 #define X86_EFLAGS_VIF_BIT (19) 176 #define X86_EFLAGS_VIF BIT(X86_EFLAGS_VIF_BIT) 177 #define X86_EFLAGS_VIP_BIT (20) 178 #define X86_EFLAGS_VIP BIT(X86_EFLAGS_VIP_BIT) 179 #define X86_EFLAGS_ID_BIT (21) 180 #define X86_EFLAGS_ID BIT(X86_EFLAGS_ID_BIT) 181 182 #define X86_EFLAGS_ALU (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 183 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 184 185 186 /* 187 * CPU features 188 */ 189 190 enum cpuid_output_regs { 191 EAX, 192 EBX, 193 ECX, 194 EDX 195 }; 196 197 struct cpuid { u32 a, b, c, d; }; 198 199 static inline struct cpuid raw_cpuid(u32 function, u32 index) 200 { 201 struct cpuid r; 202 asm volatile ("cpuid" 203 : "=a"(r.a), "=b"(r.b), "=c"(r.c), "=d"(r.d) 204 : "0"(function), "2"(index)); 205 return r; 206 } 207 208 static inline struct cpuid cpuid_indexed(u32 function, u32 index) 209 { 210 u32 level = raw_cpuid(function & 0xf0000000, 0).a; 211 if (level < function) 212 return (struct cpuid) { 0, 0, 0, 0 }; 213 return raw_cpuid(function, index); 214 } 215 216 static inline struct cpuid cpuid(u32 function) 217 { 218 return cpuid_indexed(function, 0); 219 } 220 221 static inline bool is_intel(void) 222 { 223 struct cpuid c = cpuid(0); 224 u32 name[4] = {c.b, c.d, c.c }; 225 226 return strcmp((char *)name, "GenuineIntel") == 0; 227 } 228 229 /* 230 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 231 * passed by value with no overhead. 232 */ 233 struct x86_cpu_feature { 234 u32 function; 235 u16 index; 236 u8 reg; 237 u8 bit; 238 }; 239 240 #define X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 241 ({ \ 242 struct x86_cpu_feature feature = { \ 243 .function = fn, \ 244 .index = idx, \ 245 .reg = gpr, \ 246 .bit = __bit, \ 247 }; \ 248 \ 249 static_assert((fn & 0xc0000000) == 0 || \ 250 (fn & 0xc0000000) == 0x40000000 || \ 251 (fn & 0xc0000000) == 0x80000000 || \ 252 (fn & 0xc0000000) == 0xc0000000); \ 253 static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 254 feature; \ 255 }) 256 257 /* 258 * Basic Leafs, a.k.a. Intel defined 259 */ 260 #define X86_FEATURE_MWAIT X86_CPU_FEATURE(0x1, 0, ECX, 3) 261 #define X86_FEATURE_VMX X86_CPU_FEATURE(0x1, 0, ECX, 5) 262 #define X86_FEATURE_PDCM X86_CPU_FEATURE(0x1, 0, ECX, 15) 263 #define X86_FEATURE_PCID X86_CPU_FEATURE(0x1, 0, ECX, 17) 264 #define X86_FEATURE_X2APIC X86_CPU_FEATURE(0x1, 0, ECX, 21) 265 #define X86_FEATURE_MOVBE X86_CPU_FEATURE(0x1, 0, ECX, 22) 266 #define X86_FEATURE_TSC_DEADLINE_TIMER X86_CPU_FEATURE(0x1, 0, ECX, 24) 267 #define X86_FEATURE_XSAVE X86_CPU_FEATURE(0x1, 0, ECX, 26) 268 #define X86_FEATURE_OSXSAVE X86_CPU_FEATURE(0x1, 0, ECX, 27) 269 #define X86_FEATURE_RDRAND X86_CPU_FEATURE(0x1, 0, ECX, 30) 270 #define X86_FEATURE_MCE X86_CPU_FEATURE(0x1, 0, EDX, 7) 271 #define X86_FEATURE_APIC X86_CPU_FEATURE(0x1, 0, EDX, 9) 272 #define X86_FEATURE_CLFLUSH X86_CPU_FEATURE(0x1, 0, EDX, 19) 273 #define X86_FEATURE_DS X86_CPU_FEATURE(0x1, 0, EDX, 21) 274 #define X86_FEATURE_XMM X86_CPU_FEATURE(0x1, 0, EDX, 25) 275 #define X86_FEATURE_XMM2 X86_CPU_FEATURE(0x1, 0, EDX, 26) 276 #define X86_FEATURE_TSC_ADJUST X86_CPU_FEATURE(0x7, 0, EBX, 1) 277 #define X86_FEATURE_HLE X86_CPU_FEATURE(0x7, 0, EBX, 4) 278 #define X86_FEATURE_SMEP X86_CPU_FEATURE(0x7, 0, EBX, 7) 279 #define X86_FEATURE_INVPCID X86_CPU_FEATURE(0x7, 0, EBX, 10) 280 #define X86_FEATURE_RTM X86_CPU_FEATURE(0x7, 0, EBX, 11) 281 #define X86_FEATURE_SMAP X86_CPU_FEATURE(0x7, 0, EBX, 20) 282 #define X86_FEATURE_PCOMMIT X86_CPU_FEATURE(0x7, 0, EBX, 22) 283 #define X86_FEATURE_CLFLUSHOPT X86_CPU_FEATURE(0x7, 0, EBX, 23) 284 #define X86_FEATURE_CLWB X86_CPU_FEATURE(0x7, 0, EBX, 24) 285 #define X86_FEATURE_INTEL_PT X86_CPU_FEATURE(0x7, 0, EBX, 25) 286 #define X86_FEATURE_UMIP X86_CPU_FEATURE(0x7, 0, ECX, 2) 287 #define X86_FEATURE_PKU X86_CPU_FEATURE(0x7, 0, ECX, 3) 288 #define X86_FEATURE_LA57 X86_CPU_FEATURE(0x7, 0, ECX, 16) 289 #define X86_FEATURE_RDPID X86_CPU_FEATURE(0x7, 0, ECX, 22) 290 #define X86_FEATURE_SHSTK X86_CPU_FEATURE(0x7, 0, ECX, 7) 291 #define X86_FEATURE_IBT X86_CPU_FEATURE(0x7, 0, EDX, 20) 292 #define X86_FEATURE_SPEC_CTRL X86_CPU_FEATURE(0x7, 0, EDX, 26) 293 #define X86_FEATURE_FLUSH_L1D X86_CPU_FEATURE(0x7, 0, EDX, 28) 294 #define X86_FEATURE_ARCH_CAPABILITIES X86_CPU_FEATURE(0x7, 0, EDX, 29) 295 #define X86_FEATURE_PKS X86_CPU_FEATURE(0x7, 0, ECX, 31) 296 #define X86_FEATURE_LAM X86_CPU_FEATURE(0x7, 1, EAX, 26) 297 298 /* 299 * KVM defined leafs 300 */ 301 #define KVM_FEATURE_ASYNC_PF X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 302 #define KVM_FEATURE_ASYNC_PF_INT X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 303 304 /* 305 * Extended Leafs, a.k.a. AMD defined 306 */ 307 #define X86_FEATURE_SVM X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 308 #define X86_FEATURE_PERFCTR_CORE X86_CPU_FEATURE(0x80000001, 0, ECX, 23) 309 #define X86_FEATURE_NX X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 310 #define X86_FEATURE_GBPAGES X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 311 #define X86_FEATURE_RDTSCP X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 312 #define X86_FEATURE_LM X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 313 #define X86_FEATURE_RDPRU X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 314 #define X86_FEATURE_AMD_IBPB X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 315 #define X86_FEATURE_NPT X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 316 #define X86_FEATURE_LBRV X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 317 #define X86_FEATURE_NRIPS X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 318 #define X86_FEATURE_TSCRATEMSR X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 319 #define X86_FEATURE_PAUSEFILTER X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 320 #define X86_FEATURE_PFTHRESHOLD X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 321 #define X86_FEATURE_VGIF X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 322 #define X86_FEATURE_VNMI X86_CPU_FEATURE(0x8000000A, 0, EDX, 25) 323 #define X86_FEATURE_AMD_PMU_V2 X86_CPU_FEATURE(0x80000022, 0, EAX, 0) 324 325 /* 326 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 327 * value/property as opposed to a single-bit feature. Again, pack the info 328 * into a 64-bit value to pass by value with no overhead on 64-bit builds. 329 */ 330 struct x86_cpu_property { 331 u32 function; 332 u8 index; 333 u8 reg; 334 u8 lo_bit; 335 u8 hi_bit; 336 }; 337 #define X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 338 ({ \ 339 struct x86_cpu_property property = { \ 340 .function = fn, \ 341 .index = idx, \ 342 .reg = gpr, \ 343 .lo_bit = low_bit, \ 344 .hi_bit = high_bit, \ 345 }; \ 346 \ 347 static_assert(low_bit < high_bit); \ 348 static_assert((fn & 0xc0000000) == 0 || \ 349 (fn & 0xc0000000) == 0x40000000 || \ 350 (fn & 0xc0000000) == 0x80000000 || \ 351 (fn & 0xc0000000) == 0xc0000000); \ 352 static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 353 property; \ 354 }) 355 356 #define X86_PROPERTY_MAX_BASIC_LEAF X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 357 #define X86_PROPERTY_PMU_VERSION X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 358 #define X86_PROPERTY_PMU_NR_GP_COUNTERS X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 359 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 360 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 361 #define X86_PROPERTY_PMU_EVENTS_MASK X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7) 362 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 363 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 364 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 365 366 #define X86_PROPERTY_SUPPORTED_XCR0_LO X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 367 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 368 #define X86_PROPERTY_XSTATE_MAX_SIZE X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 369 #define X86_PROPERTY_SUPPORTED_XCR0_HI X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 370 371 #define X86_PROPERTY_XSTATE_TILE_SIZE X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 372 #define X86_PROPERTY_XSTATE_TILE_OFFSET X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 373 374 #define X86_PROPERTY_INTEL_PT_NR_RANGES X86_CPU_PROPERTY(0x14, 1, EAX, 0, 2) 375 376 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 377 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 378 #define X86_PROPERTY_AMX_BYTES_PER_TILE X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 379 #define X86_PROPERTY_AMX_BYTES_PER_ROW X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 380 #define X86_PROPERTY_AMX_NR_TILE_REGS X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 381 #define X86_PROPERTY_AMX_MAX_ROWS X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 382 383 #define X86_PROPERTY_MAX_KVM_LEAF X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 384 385 #define X86_PROPERTY_MAX_EXT_LEAF X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 386 #define X86_PROPERTY_MAX_PHY_ADDR X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 387 #define X86_PROPERTY_MAX_VIRT_ADDR X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 388 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 389 #define X86_PROPERTY_SEV_C_BIT X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 390 #define X86_PROPERTY_PHYS_ADDR_REDUCTION X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 391 #define X86_PROPERTY_NR_PERFCTR_CORE X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) 392 #define X86_PROPERTY_NR_PERFCTR_NB X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) 393 394 #define X86_PROPERTY_MAX_CENTAUR_LEAF X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 395 396 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi) 397 { 398 union { 399 struct cpuid cpuid; 400 u32 gprs[4]; 401 } c; 402 403 c.cpuid = cpuid_indexed(function, index); 404 405 return (c.gprs[reg] & GENMASK(hi, lo)) >> lo; 406 } 407 408 static inline bool this_cpu_has(struct x86_cpu_feature feature) 409 { 410 return __this_cpu_has(feature.function, feature.index, 411 feature.reg, feature.bit, feature.bit); 412 } 413 414 static inline uint32_t this_cpu_property(struct x86_cpu_property property) 415 { 416 return __this_cpu_has(property.function, property.index, 417 property.reg, property.lo_bit, property.hi_bit); 418 } 419 420 static __always_inline bool this_cpu_has_p(struct x86_cpu_property property) 421 { 422 uint32_t max_leaf; 423 424 switch (property.function & 0xc0000000) { 425 case 0: 426 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 427 break; 428 case 0x40000000: 429 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 430 break; 431 case 0x80000000: 432 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 433 break; 434 case 0xc0000000: 435 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 436 } 437 return max_leaf >= property.function; 438 } 439 440 static inline u8 cpuid_maxphyaddr(void) 441 { 442 if (!this_cpu_has_p(X86_PROPERTY_MAX_PHY_ADDR)) 443 return 36; 444 445 return this_cpu_property(X86_PROPERTY_MAX_PHY_ADDR); 446 } 447 448 static inline u64 this_cpu_supported_xcr0(void) 449 { 450 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 451 return 0; 452 453 return (u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 454 ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 455 } 456 457 struct far_pointer32 { 458 u32 offset; 459 u16 selector; 460 } __attribute__((packed)); 461 462 struct descriptor_table_ptr { 463 u16 limit; 464 ulong base; 465 } __attribute__((packed)); 466 467 static inline void clac(void) 468 { 469 asm volatile (".byte 0x0f, 0x01, 0xca" : : : "memory"); 470 } 471 472 static inline void stac(void) 473 { 474 asm volatile (".byte 0x0f, 0x01, 0xcb" : : : "memory"); 475 } 476 477 static inline u16 read_cs(void) 478 { 479 unsigned val; 480 481 asm volatile ("mov %%cs, %0" : "=mr"(val)); 482 return val; 483 } 484 485 static inline u16 read_ds(void) 486 { 487 unsigned val; 488 489 asm volatile ("mov %%ds, %0" : "=mr"(val)); 490 return val; 491 } 492 493 static inline u16 read_es(void) 494 { 495 unsigned val; 496 497 asm volatile ("mov %%es, %0" : "=mr"(val)); 498 return val; 499 } 500 501 static inline u16 read_ss(void) 502 { 503 unsigned val; 504 505 asm volatile ("mov %%ss, %0" : "=mr"(val)); 506 return val; 507 } 508 509 static inline u16 read_fs(void) 510 { 511 unsigned val; 512 513 asm volatile ("mov %%fs, %0" : "=mr"(val)); 514 return val; 515 } 516 517 static inline u16 read_gs(void) 518 { 519 unsigned val; 520 521 asm volatile ("mov %%gs, %0" : "=mr"(val)); 522 return val; 523 } 524 525 static inline unsigned long read_rflags(void) 526 { 527 unsigned long f; 528 asm volatile ("pushf; pop %0\n\t" : "=rm"(f)); 529 return f; 530 } 531 532 static inline void write_ds(unsigned val) 533 { 534 asm volatile ("mov %0, %%ds" : : "rm"(val) : "memory"); 535 } 536 537 static inline void write_es(unsigned val) 538 { 539 asm volatile ("mov %0, %%es" : : "rm"(val) : "memory"); 540 } 541 542 static inline void write_ss(unsigned val) 543 { 544 asm volatile ("mov %0, %%ss" : : "rm"(val) : "memory"); 545 } 546 547 static inline void write_fs(unsigned val) 548 { 549 asm volatile ("mov %0, %%fs" : : "rm"(val) : "memory"); 550 } 551 552 static inline void write_gs(unsigned val) 553 { 554 asm volatile ("mov %0, %%gs" : : "rm"(val) : "memory"); 555 } 556 557 static inline void write_rflags(unsigned long f) 558 { 559 asm volatile ("push %0; popf\n\t" : : "rm"(f)); 560 } 561 562 static inline void set_iopl(int iopl) 563 { 564 unsigned long flags = read_rflags() & ~X86_EFLAGS_IOPL; 565 flags |= iopl * (X86_EFLAGS_IOPL / 3); 566 write_rflags(flags); 567 } 568 569 /* 570 * Don't use the safe variants for rdmsr() or wrmsr(). The exception fixup 571 * infrastructure uses per-CPU data and thus consumes GS.base. Various tests 572 * temporarily modify MSR_GS_BASE and will explode when trying to determine 573 * whether or not RDMSR/WRMSR faulted. 574 */ 575 static inline u64 rdmsr(u32 index) 576 { 577 u32 a, d; 578 asm volatile ("rdmsr" : "=a"(a), "=d"(d) : "c"(index) : "memory"); 579 return a | ((u64)d << 32); 580 } 581 582 static inline void wrmsr(u32 index, u64 val) 583 { 584 u32 a = val, d = val >> 32; 585 asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); 586 } 587 588 #define __rdreg64_safe(fep, insn, index, val) \ 589 ({ \ 590 uint32_t a, d; \ 591 int vector; \ 592 \ 593 vector = __asm_safe_out2(fep, insn, "=a"(a), "=d"(d), "c"(index));\ 594 \ 595 if (vector) \ 596 *(val) = 0; \ 597 else \ 598 *(val) = (uint64_t)a | ((uint64_t)d << 32); \ 599 vector; \ 600 }) 601 602 #define rdreg64_safe(insn, index, val) \ 603 __rdreg64_safe("", insn, index, val) 604 605 #define __wrreg64_safe(fep, insn, index, val) \ 606 ({ \ 607 uint32_t eax = (val), edx = (val) >> 32; \ 608 \ 609 __asm_safe(fep, insn, "a" (eax), "d" (edx), "c" (index)); \ 610 }) 611 612 #define wrreg64_safe(insn, index, val) \ 613 __wrreg64_safe("", insn, index, val) 614 615 static inline int rdmsr_safe(u32 index, uint64_t *val) 616 { 617 return rdreg64_safe("rdmsr", index, val); 618 } 619 620 static inline int rdmsr_fep_safe(u32 index, uint64_t *val) 621 { 622 return __rdreg64_safe(KVM_FEP, "rdmsr", index, val); 623 } 624 625 static inline int wrmsr_safe(u32 index, u64 val) 626 { 627 return wrreg64_safe("wrmsr", index, val); 628 } 629 630 static inline int wrmsr_fep_safe(u32 index, u64 val) 631 { 632 return __wrreg64_safe(KVM_FEP, "wrmsr", index, val); 633 } 634 635 static inline int rdpmc_safe(u32 index, uint64_t *val) 636 { 637 return rdreg64_safe("rdpmc", index, val); 638 } 639 640 static inline uint64_t rdpmc(uint32_t index) 641 { 642 uint64_t val; 643 int vector = rdpmc_safe(index, &val); 644 645 assert_msg(!vector, "Unexpected %s on RDPMC(%" PRId32 ")", 646 exception_mnemonic(vector), index); 647 return val; 648 } 649 650 static inline int xgetbv_safe(u32 index, u64 *result) 651 { 652 return rdreg64_safe(".byte 0x0f,0x01,0xd0", index, result); 653 } 654 655 static inline int xsetbv_safe(u32 index, u64 value) 656 { 657 return wrreg64_safe(".byte 0x0f,0x01,0xd1", index, value); 658 } 659 660 static inline int write_cr0_safe(ulong val) 661 { 662 return asm_safe("mov %0,%%cr0", "r" (val)); 663 } 664 665 static inline void write_cr0(ulong val) 666 { 667 int vector = write_cr0_safe(val); 668 669 assert_msg(!vector, "Unexpected fault '%d' writing CR0 = %lx", 670 vector, val); 671 } 672 673 static inline ulong read_cr0(void) 674 { 675 ulong val; 676 asm volatile ("mov %%cr0, %0" : "=r"(val) : : "memory"); 677 return val; 678 } 679 680 static inline void write_cr2(ulong val) 681 { 682 asm volatile ("mov %0, %%cr2" : : "r"(val) : "memory"); 683 } 684 685 static inline ulong read_cr2(void) 686 { 687 ulong val; 688 asm volatile ("mov %%cr2, %0" : "=r"(val) : : "memory"); 689 return val; 690 } 691 692 static inline int write_cr3_safe(ulong val) 693 { 694 return asm_safe("mov %0,%%cr3", "r" (val)); 695 } 696 697 static inline void write_cr3(ulong val) 698 { 699 int vector = write_cr3_safe(val); 700 701 assert_msg(!vector, "Unexpected fault '%d' writing CR3 = %lx", 702 vector, val); 703 } 704 705 static inline ulong read_cr3(void) 706 { 707 ulong val; 708 asm volatile ("mov %%cr3, %0" : "=r"(val) : : "memory"); 709 return val; 710 } 711 712 static inline void update_cr3(void *cr3) 713 { 714 write_cr3((ulong)cr3); 715 } 716 717 static inline int write_cr4_safe(ulong val) 718 { 719 return asm_safe("mov %0,%%cr4", "r" (val)); 720 } 721 722 static inline void write_cr4(ulong val) 723 { 724 int vector = write_cr4_safe(val); 725 726 assert_msg(!vector, "Unexpected fault '%d' writing CR4 = %lx", 727 vector, val); 728 } 729 730 static inline ulong read_cr4(void) 731 { 732 ulong val; 733 asm volatile ("mov %%cr4, %0" : "=r"(val) : : "memory"); 734 return val; 735 } 736 737 static inline void write_cr8(ulong val) 738 { 739 asm volatile ("mov %0, %%cr8" : : "r"(val) : "memory"); 740 } 741 742 static inline ulong read_cr8(void) 743 { 744 ulong val; 745 asm volatile ("mov %%cr8, %0" : "=r"(val) : : "memory"); 746 return val; 747 } 748 749 static inline void lgdt(const struct descriptor_table_ptr *ptr) 750 { 751 asm volatile ("lgdt %0" : : "m"(*ptr)); 752 } 753 754 static inline int lgdt_safe(const struct descriptor_table_ptr *ptr) 755 { 756 return asm_safe("lgdt %0", "m"(*ptr)); 757 } 758 759 static inline int lgdt_fep_safe(const struct descriptor_table_ptr *ptr) 760 { 761 return asm_fep_safe("lgdt %0", "m"(*ptr)); 762 } 763 764 static inline void sgdt(struct descriptor_table_ptr *ptr) 765 { 766 asm volatile ("sgdt %0" : "=m"(*ptr)); 767 } 768 769 static inline void lidt(const struct descriptor_table_ptr *ptr) 770 { 771 asm volatile ("lidt %0" : : "m"(*ptr)); 772 } 773 774 static inline int lidt_safe(const struct descriptor_table_ptr *ptr) 775 { 776 return asm_safe("lidt %0", "m"(*ptr)); 777 } 778 779 static inline int lidt_fep_safe(const struct descriptor_table_ptr *ptr) 780 { 781 return asm_fep_safe("lidt %0", "m"(*ptr)); 782 } 783 784 static inline void sidt(struct descriptor_table_ptr *ptr) 785 { 786 asm volatile ("sidt %0" : "=m"(*ptr)); 787 } 788 789 static inline void lldt(u16 val) 790 { 791 asm volatile ("lldt %0" : : "rm"(val)); 792 } 793 794 static inline int lldt_safe(u16 val) 795 { 796 return asm_safe("lldt %0", "rm"(val)); 797 } 798 799 static inline int lldt_fep_safe(u16 val) 800 { 801 return asm_safe("lldt %0", "rm"(val)); 802 } 803 804 static inline u16 sldt(void) 805 { 806 u16 val; 807 asm volatile ("sldt %0" : "=rm"(val)); 808 return val; 809 } 810 811 static inline void ltr(u16 val) 812 { 813 asm volatile ("ltr %0" : : "rm"(val)); 814 } 815 816 static inline int ltr_safe(u16 val) 817 { 818 return asm_safe("ltr %0", "rm"(val)); 819 } 820 821 static inline int ltr_fep_safe(u16 val) 822 { 823 return asm_safe("ltr %0", "rm"(val)); 824 } 825 826 static inline u16 str(void) 827 { 828 u16 val; 829 asm volatile ("str %0" : "=rm"(val)); 830 return val; 831 } 832 833 static inline void write_dr0(void *val) 834 { 835 asm volatile ("mov %0, %%dr0" : : "r"(val) : "memory"); 836 } 837 838 static inline void write_dr1(void *val) 839 { 840 asm volatile ("mov %0, %%dr1" : : "r"(val) : "memory"); 841 } 842 843 static inline void write_dr2(void *val) 844 { 845 asm volatile ("mov %0, %%dr2" : : "r"(val) : "memory"); 846 } 847 848 static inline void write_dr3(void *val) 849 { 850 asm volatile ("mov %0, %%dr3" : : "r"(val) : "memory"); 851 } 852 853 static inline void write_dr6(ulong val) 854 { 855 asm volatile ("mov %0, %%dr6" : : "r"(val) : "memory"); 856 } 857 858 static inline ulong read_dr6(void) 859 { 860 ulong val; 861 asm volatile ("mov %%dr6, %0" : "=r"(val)); 862 return val; 863 } 864 865 static inline void write_dr7(ulong val) 866 { 867 asm volatile ("mov %0, %%dr7" : : "r"(val) : "memory"); 868 } 869 870 static inline ulong read_dr7(void) 871 { 872 ulong val; 873 asm volatile ("mov %%dr7, %0" : "=r"(val)); 874 return val; 875 } 876 877 static inline void pause(void) 878 { 879 asm volatile ("pause"); 880 } 881 882 static inline void cli(void) 883 { 884 asm volatile ("cli"); 885 } 886 887 /* 888 * See also safe_halt(). 889 */ 890 static inline void sti(void) 891 { 892 asm volatile ("sti"); 893 } 894 895 /* 896 * Enable interrupts and ensure that interrupts are evaluated upon return from 897 * this function, i.e. execute a nop to consume the STi interrupt shadow. 898 */ 899 static inline void sti_nop(void) 900 { 901 asm volatile ("sti; nop"); 902 } 903 904 /* 905 * Enable interrupts for one instruction (nop), to allow the CPU to process all 906 * interrupts that are already pending. 907 */ 908 static inline void sti_nop_cli(void) 909 { 910 asm volatile ("sti; nop; cli"); 911 } 912 913 static inline unsigned long long rdrand(void) 914 { 915 long long r; 916 917 asm volatile("rdrand %0\n\t" 918 "jc 1f\n\t" 919 "mov $0, %0\n\t" 920 "1:\n\t" : "=r" (r)); 921 return r; 922 } 923 924 static inline unsigned long long rdtsc(void) 925 { 926 long long r; 927 928 #ifdef __x86_64__ 929 unsigned a, d; 930 931 asm volatile ("rdtsc" : "=a"(a), "=d"(d)); 932 r = a | ((long long)d << 32); 933 #else 934 asm volatile ("rdtsc" : "=A"(r)); 935 #endif 936 return r; 937 } 938 939 /* 940 * Per the advice in the SDM, volume 2, the sequence "mfence; lfence" 941 * executed immediately before rdtsc ensures that rdtsc will be 942 * executed only after all previous instructions have executed and all 943 * previous loads and stores are globally visible. In addition, the 944 * lfence immediately after rdtsc ensures that rdtsc will be executed 945 * prior to the execution of any subsequent instruction. 946 */ 947 static inline unsigned long long fenced_rdtsc(void) 948 { 949 unsigned long long tsc; 950 951 #ifdef __x86_64__ 952 unsigned int eax, edx; 953 954 asm volatile ("mfence; lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 955 tsc = eax | ((unsigned long long)edx << 32); 956 #else 957 asm volatile ("mfence; lfence; rdtsc; lfence" : "=A"(tsc)); 958 #endif 959 return tsc; 960 } 961 962 static inline unsigned long long rdtscp(u32 *aux) 963 { 964 long long r; 965 966 #ifdef __x86_64__ 967 unsigned a, d; 968 969 asm volatile ("rdtscp" : "=a"(a), "=d"(d), "=c"(*aux)); 970 r = a | ((long long)d << 32); 971 #else 972 asm volatile ("rdtscp" : "=A"(r), "=c"(*aux)); 973 #endif 974 return r; 975 } 976 977 static inline void wrtsc(u64 tsc) 978 { 979 wrmsr(MSR_IA32_TSC, tsc); 980 } 981 982 983 static inline void invlpg(volatile void *va) 984 { 985 asm volatile("invlpg (%0)" ::"r" (va) : "memory"); 986 } 987 988 struct invpcid_desc { 989 u64 pcid : 12; 990 u64 rsv : 52; 991 u64 addr : 64; 992 }; 993 994 static inline int invpcid_safe(unsigned long type, struct invpcid_desc *desc) 995 { 996 /* invpcid (%rax), %rbx */ 997 return asm_safe(".byte 0x66,0x0f,0x38,0x82,0x18", "a" (desc), "b" (type)); 998 } 999 1000 /* 1001 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 1002 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 1003 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 1004 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 1005 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 1006 */ 1007 static inline void safe_halt(void) 1008 { 1009 asm volatile("sti; hlt"); 1010 } 1011 1012 static inline u32 read_pkru(void) 1013 { 1014 unsigned int eax, edx; 1015 unsigned int ecx = 0; 1016 unsigned int pkru; 1017 1018 asm volatile(".byte 0x0f,0x01,0xee\n\t" 1019 : "=a" (eax), "=d" (edx) 1020 : "c" (ecx)); 1021 pkru = eax; 1022 return pkru; 1023 } 1024 1025 static inline void write_pkru(u32 pkru) 1026 { 1027 unsigned int eax = pkru; 1028 unsigned int ecx = 0; 1029 unsigned int edx = 0; 1030 1031 asm volatile(".byte 0x0f,0x01,0xef\n\t" 1032 : : "a" (eax), "c" (ecx), "d" (edx)); 1033 } 1034 1035 static inline bool is_canonical(u64 addr) 1036 { 1037 int va_width, shift_amt; 1038 1039 if (this_cpu_has_p(X86_PROPERTY_MAX_VIRT_ADDR)) 1040 va_width = this_cpu_property(X86_PROPERTY_MAX_VIRT_ADDR); 1041 else 1042 va_width = 48; 1043 1044 shift_amt = 64 - va_width; 1045 return (s64)(addr << shift_amt) >> shift_amt == addr; 1046 } 1047 1048 static inline void flush_tlb(void) 1049 { 1050 ulong cr4; 1051 1052 cr4 = read_cr4(); 1053 write_cr4(cr4 ^ X86_CR4_PGE); 1054 write_cr4(cr4); 1055 } 1056 1057 static inline void generate_non_canonical_gp(void) 1058 { 1059 *(volatile u64 *)NONCANONICAL = 0; 1060 } 1061 1062 static inline void generate_ud(void) 1063 { 1064 asm volatile ("ud2"); 1065 } 1066 1067 static inline void generate_de(void) 1068 { 1069 asm volatile ( 1070 "xor %%eax, %%eax\n\t" 1071 "xor %%ebx, %%ebx\n\t" 1072 "xor %%edx, %%edx\n\t" 1073 "idiv %%ebx\n\t" 1074 ::: "eax", "ebx", "edx"); 1075 } 1076 1077 static inline void generate_bp(void) 1078 { 1079 asm volatile ("int3"); 1080 } 1081 1082 static inline void generate_single_step_db(void) 1083 { 1084 write_rflags(read_rflags() | X86_EFLAGS_TF); 1085 asm volatile("nop"); 1086 } 1087 1088 static inline uint64_t generate_usermode_ac(void) 1089 { 1090 /* 1091 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 1092 * Disclaimer: It is assumed that the stack pointer is aligned 1093 * on a 16-byte boundary as x86_64 stacks should be. 1094 */ 1095 asm volatile("movq $0, -0x4(%rsp)"); 1096 1097 return 0; 1098 } 1099 1100 /* 1101 * Switch from 64-bit to 32-bit mode and generate #OF via INTO. Note, if RIP 1102 * or RSP holds a 64-bit value, this helper will NOT generate #OF. 1103 */ 1104 static inline void generate_of(void) 1105 { 1106 struct far_pointer32 fp = { 1107 .offset = (uintptr_t)&&into, 1108 .selector = KERNEL_CS32, 1109 }; 1110 uintptr_t rsp; 1111 1112 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 1113 1114 if (fp.offset != (uintptr_t)&&into) { 1115 printf("Code address too high.\n"); 1116 return; 1117 } 1118 if ((u32)rsp != rsp) { 1119 printf("Stack address too high.\n"); 1120 return; 1121 } 1122 1123 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 1124 return; 1125 into: 1126 asm volatile (".code32;" 1127 "movl $0x7fffffff, %eax;" 1128 "addl %eax, %eax;" 1129 "into;" 1130 "lret;" 1131 ".code64"); 1132 __builtin_unreachable(); 1133 } 1134 1135 static inline void fnop(void) 1136 { 1137 asm volatile("fnop"); 1138 } 1139 1140 /* If CR0.TS is set in L2, #NM is generated. */ 1141 static inline void generate_cr0_ts_nm(void) 1142 { 1143 write_cr0((read_cr0() & ~X86_CR0_EM) | X86_CR0_TS); 1144 fnop(); 1145 } 1146 1147 /* If CR0.TS is cleared and CR0.EM is set, #NM is generated. */ 1148 static inline void generate_cr0_em_nm(void) 1149 { 1150 write_cr0((read_cr0() & ~X86_CR0_TS) | X86_CR0_EM); 1151 fnop(); 1152 } 1153 1154 static inline bool is_la57_enabled(void) 1155 { 1156 return !!(read_cr4() & X86_CR4_LA57); 1157 } 1158 1159 static inline bool is_lam_sup_enabled(void) 1160 { 1161 return !!(read_cr4() & X86_CR4_LAM_SUP); 1162 } 1163 1164 static inline bool is_lam_u48_enabled(void) 1165 { 1166 return (read_cr3() & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)) == X86_CR3_LAM_U48; 1167 } 1168 1169 static inline bool is_lam_u57_enabled(void) 1170 { 1171 return !!(read_cr3() & X86_CR3_LAM_U57); 1172 } 1173 1174 #endif 1175