1 #ifndef _X86_MSR_H_ 2 #define _X86_MSR_H_ 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_SPEC_CTRL 0x00000048 36 #define MSR_IA32_PRED_CMD 0x00000049 37 38 #define MSR_IA32_PMC0 0x000004c1 39 #define MSR_IA32_PERFCTR0 0x000000c1 40 #define MSR_IA32_PERFCTR1 0x000000c2 41 #define MSR_FSB_FREQ 0x000000cd 42 43 #define MSR_MTRRcap 0x000000fe 44 #define MSR_IA32_BBL_CR_CTL 0x00000119 45 46 #define MSR_IA32_SYSENTER_CS 0x00000174 47 #define MSR_IA32_SYSENTER_ESP 0x00000175 48 #define MSR_IA32_SYSENTER_EIP 0x00000176 49 50 #define MSR_IA32_MCG_CAP 0x00000179 51 #define MSR_IA32_MCG_STATUS 0x0000017a 52 #define MSR_IA32_MCG_CTL 0x0000017b 53 54 #define MSR_IA32_PEBS_ENABLE 0x000003f1 55 #define MSR_IA32_DS_AREA 0x00000600 56 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 57 58 #define MSR_MTRRfix64K_00000 0x00000250 59 #define MSR_MTRRfix16K_80000 0x00000258 60 #define MSR_MTRRfix16K_A0000 0x00000259 61 #define MSR_MTRRfix4K_C0000 0x00000268 62 #define MSR_MTRRfix4K_C8000 0x00000269 63 #define MSR_MTRRfix4K_D0000 0x0000026a 64 #define MSR_MTRRfix4K_D8000 0x0000026b 65 #define MSR_MTRRfix4K_E0000 0x0000026c 66 #define MSR_MTRRfix4K_E8000 0x0000026d 67 #define MSR_MTRRfix4K_F0000 0x0000026e 68 #define MSR_MTRRfix4K_F8000 0x0000026f 69 #define MSR_MTRRdefType 0x000002ff 70 71 #define MSR_IA32_CR_PAT 0x00000277 72 73 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 74 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 75 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 76 #define MSR_IA32_LASTINTFROMIP 0x000001dd 77 #define MSR_IA32_LASTINTTOIP 0x000001de 78 79 /* DEBUGCTLMSR bits (others vary by model): */ 80 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 81 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 82 #define DEBUGCTLMSR_TR (1UL << 6) 83 #define DEBUGCTLMSR_BTS (1UL << 7) 84 #define DEBUGCTLMSR_BTINT (1UL << 8) 85 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 86 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 87 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 88 89 #define MSR_LBR_NHM_FROM 0x00000680 90 #define MSR_LBR_NHM_TO 0x000006c0 91 #define MSR_LBR_CORE_FROM 0x00000040 92 #define MSR_LBR_CORE_TO 0x00000060 93 #define MSR_LBR_TOS 0x000001c9 94 #define MSR_LBR_SELECT 0x000001c8 95 96 #define MSR_IA32_MC0_CTL 0x00000400 97 #define MSR_IA32_MC0_STATUS 0x00000401 98 #define MSR_IA32_MC0_ADDR 0x00000402 99 #define MSR_IA32_MC0_MISC 0x00000403 100 101 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 102 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 103 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 104 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 105 106 /* These are consecutive and not in the normal 4er MCE bank block */ 107 #define MSR_IA32_MC0_CTL2 0x00000280 108 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 109 110 #define CMCI_EN (1ULL << 30) 111 #define CMCI_THRESHOLD_MASK 0xffffULL 112 113 #define MSR_P6_PERFCTR0 0x000000c1 114 #define MSR_P6_PERFCTR1 0x000000c2 115 #define MSR_P6_EVNTSEL0 0x00000186 116 #define MSR_P6_EVNTSEL1 0x00000187 117 118 /* AMD64 MSRs. Not complete. See the architecture manual for a more 119 complete list. */ 120 121 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 122 #define MSR_AMD64_NB_CFG 0xc001001f 123 #define MSR_AMD64_PATCH_LOADER 0xc0010020 124 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 125 #define MSR_AMD64_OSVW_STATUS 0xc0010141 126 #define MSR_AMD64_DC_CFG 0xc0011022 127 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 128 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 129 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 130 #define MSR_AMD64_IBSOPCTL 0xc0011033 131 #define MSR_AMD64_IBSOPRIP 0xc0011034 132 #define MSR_AMD64_IBSOPDATA 0xc0011035 133 #define MSR_AMD64_IBSOPDATA2 0xc0011036 134 #define MSR_AMD64_IBSOPDATA3 0xc0011037 135 #define MSR_AMD64_IBSDCLINAD 0xc0011038 136 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 137 #define MSR_AMD64_IBSCTL 0xc001103a 138 139 /* Fam 10h MSRs */ 140 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 141 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 142 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 143 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 144 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 145 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 146 #define MSR_FAM10H_NODE_ID 0xc001100c 147 148 /* K8 MSRs */ 149 #define MSR_K8_TOP_MEM1 0xc001001a 150 #define MSR_K8_TOP_MEM2 0xc001001d 151 #define MSR_K8_SYSCFG 0xc0010010 152 #define MSR_K8_INT_PENDING_MSG 0xc0010055 153 /* C1E active bits in int pending message */ 154 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 155 #define MSR_K8_TSEG_ADDR 0xc0010112 156 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 157 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 158 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 159 160 /* K7 MSRs */ 161 #define MSR_K7_EVNTSEL0 0xc0010000 162 #define MSR_K7_PERFCTR0 0xc0010004 163 #define MSR_K7_EVNTSEL1 0xc0010001 164 #define MSR_K7_PERFCTR1 0xc0010005 165 #define MSR_K7_EVNTSEL2 0xc0010002 166 #define MSR_K7_PERFCTR2 0xc0010006 167 #define MSR_K7_EVNTSEL3 0xc0010003 168 #define MSR_K7_PERFCTR3 0xc0010007 169 #define MSR_K7_CLK_CTL 0xc001001b 170 #define MSR_K7_HWCR 0xc0010015 171 #define MSR_K7_FID_VID_CTL 0xc0010041 172 #define MSR_K7_FID_VID_STATUS 0xc0010042 173 174 /* K6 MSRs */ 175 #define MSR_K6_EFER 0xc0000080 176 #define MSR_K6_STAR 0xc0000081 177 #define MSR_K6_WHCR 0xc0000082 178 #define MSR_K6_UWCCR 0xc0000085 179 #define MSR_K6_EPMR 0xc0000086 180 #define MSR_K6_PSOR 0xc0000087 181 #define MSR_K6_PFIR 0xc0000088 182 183 /* Centaur-Hauls/IDT defined MSRs. */ 184 #define MSR_IDT_FCR1 0x00000107 185 #define MSR_IDT_FCR2 0x00000108 186 #define MSR_IDT_FCR3 0x00000109 187 #define MSR_IDT_FCR4 0x0000010a 188 189 #define MSR_IDT_MCR0 0x00000110 190 #define MSR_IDT_MCR1 0x00000111 191 #define MSR_IDT_MCR2 0x00000112 192 #define MSR_IDT_MCR3 0x00000113 193 #define MSR_IDT_MCR4 0x00000114 194 #define MSR_IDT_MCR5 0x00000115 195 #define MSR_IDT_MCR6 0x00000116 196 #define MSR_IDT_MCR7 0x00000117 197 #define MSR_IDT_MCR_CTRL 0x00000120 198 199 /* VIA Cyrix defined MSRs*/ 200 #define MSR_VIA_FCR 0x00001107 201 #define MSR_VIA_LONGHAUL 0x0000110a 202 #define MSR_VIA_RNG 0x0000110b 203 #define MSR_VIA_BCR2 0x00001147 204 205 /* Transmeta defined MSRs */ 206 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 207 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 208 #define MSR_TMTA_LRTI_READOUT 0x80868018 209 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 210 211 /* Intel defined MSRs. */ 212 #define MSR_IA32_P5_MC_ADDR 0x00000000 213 #define MSR_IA32_P5_MC_TYPE 0x00000001 214 #define MSR_IA32_TSC 0x00000010 215 #define MSR_IA32_PLATFORM_ID 0x00000017 216 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 217 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 218 #define MSR_IA32_TSC_ADJUST 0x0000003b 219 #define MSR_IA32_U_CET 0x000006a0 220 #define MSR_IA32_PL3_SSP 0x000006a7 221 #define MSR_IA32_PKRS 0x000006e1 222 223 #define FEATURE_CONTROL_LOCKED (1<<0) 224 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 225 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 226 227 #define MSR_IA32_APICBASE 0x0000001b 228 #define MSR_IA32_APICBASE_BSP (1<<8) 229 #define MSR_IA32_APICBASE_ENABLE (1<<11) 230 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 231 232 #define MSR_IA32_UCODE_WRITE 0x00000079 233 #define MSR_IA32_UCODE_REV 0x0000008b 234 235 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 236 #define ARCH_CAP_RDCL_NO (1ULL << 0) 237 #define ARCH_CAP_IBRS_ALL (1ULL << 1) 238 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1ULL << 3) 239 #define ARCH_CAP_SSB_NO (1ULL << 4) 240 #define ARCH_CAP_MDS_NO (1ULL << 5) 241 #define ARCH_CAP_PSCHANGE_MC_NO (1ULL << 6) 242 #define ARCH_CAP_TSX_CTRL_MSR (1ULL << 7) 243 #define ARCH_CAP_TAA_NO (1ULL << 8) 244 245 #define MSR_IA32_TSX_CTRL 0x00000122 246 #define TSX_CTRL_RTM_DISABLE (1ULL << 0) 247 #define TSX_CTRL_CPUID_CLEAR (1ULL << 1) 248 249 #define MSR_IA32_PERF_STATUS 0x00000198 250 #define MSR_IA32_PERF_CTL 0x00000199 251 252 #define MSR_IA32_MPERF 0x000000e7 253 #define MSR_IA32_APERF 0x000000e8 254 255 #define MSR_IA32_THERM_CONTROL 0x0000019a 256 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 257 258 #define THERM_INT_LOW_ENABLE (1 << 0) 259 #define THERM_INT_HIGH_ENABLE (1 << 1) 260 261 #define MSR_IA32_THERM_STATUS 0x0000019c 262 263 #define THERM_STATUS_PROCHOT (1 << 0) 264 265 #define MSR_THERM2_CTL 0x0000019d 266 267 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 268 269 #define MSR_IA32_MISC_ENABLE 0x000001a0 270 271 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 272 273 /* MISC_ENABLE bits: architectural */ 274 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 275 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 276 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 277 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 278 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 279 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 280 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 281 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 282 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 283 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 284 285 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 286 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 287 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 288 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 289 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 290 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 291 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 292 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 293 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 294 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 295 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 296 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 297 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 298 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 299 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 300 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 301 302 /* P4/Xeon+ specific */ 303 #define MSR_IA32_MCG_EAX 0x00000180 304 #define MSR_IA32_MCG_EBX 0x00000181 305 #define MSR_IA32_MCG_ECX 0x00000182 306 #define MSR_IA32_MCG_EDX 0x00000183 307 #define MSR_IA32_MCG_ESI 0x00000184 308 #define MSR_IA32_MCG_EDI 0x00000185 309 #define MSR_IA32_MCG_EBP 0x00000186 310 #define MSR_IA32_MCG_ESP 0x00000187 311 #define MSR_IA32_MCG_EFLAGS 0x00000188 312 #define MSR_IA32_MCG_EIP 0x00000189 313 #define MSR_IA32_MCG_RESERVED 0x0000018a 314 315 /* Pentium IV performance counter MSRs */ 316 #define MSR_P4_BPU_PERFCTR0 0x00000300 317 #define MSR_P4_BPU_PERFCTR1 0x00000301 318 #define MSR_P4_BPU_PERFCTR2 0x00000302 319 #define MSR_P4_BPU_PERFCTR3 0x00000303 320 #define MSR_P4_MS_PERFCTR0 0x00000304 321 #define MSR_P4_MS_PERFCTR1 0x00000305 322 #define MSR_P4_MS_PERFCTR2 0x00000306 323 #define MSR_P4_MS_PERFCTR3 0x00000307 324 #define MSR_P4_FLAME_PERFCTR0 0x00000308 325 #define MSR_P4_FLAME_PERFCTR1 0x00000309 326 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 327 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 328 #define MSR_P4_IQ_PERFCTR0 0x0000030c 329 #define MSR_P4_IQ_PERFCTR1 0x0000030d 330 #define MSR_P4_IQ_PERFCTR2 0x0000030e 331 #define MSR_P4_IQ_PERFCTR3 0x0000030f 332 #define MSR_P4_IQ_PERFCTR4 0x00000310 333 #define MSR_P4_IQ_PERFCTR5 0x00000311 334 #define MSR_P4_BPU_CCCR0 0x00000360 335 #define MSR_P4_BPU_CCCR1 0x00000361 336 #define MSR_P4_BPU_CCCR2 0x00000362 337 #define MSR_P4_BPU_CCCR3 0x00000363 338 #define MSR_P4_MS_CCCR0 0x00000364 339 #define MSR_P4_MS_CCCR1 0x00000365 340 #define MSR_P4_MS_CCCR2 0x00000366 341 #define MSR_P4_MS_CCCR3 0x00000367 342 #define MSR_P4_FLAME_CCCR0 0x00000368 343 #define MSR_P4_FLAME_CCCR1 0x00000369 344 #define MSR_P4_FLAME_CCCR2 0x0000036a 345 #define MSR_P4_FLAME_CCCR3 0x0000036b 346 #define MSR_P4_IQ_CCCR0 0x0000036c 347 #define MSR_P4_IQ_CCCR1 0x0000036d 348 #define MSR_P4_IQ_CCCR2 0x0000036e 349 #define MSR_P4_IQ_CCCR3 0x0000036f 350 #define MSR_P4_IQ_CCCR4 0x00000370 351 #define MSR_P4_IQ_CCCR5 0x00000371 352 #define MSR_P4_ALF_ESCR0 0x000003ca 353 #define MSR_P4_ALF_ESCR1 0x000003cb 354 #define MSR_P4_BPU_ESCR0 0x000003b2 355 #define MSR_P4_BPU_ESCR1 0x000003b3 356 #define MSR_P4_BSU_ESCR0 0x000003a0 357 #define MSR_P4_BSU_ESCR1 0x000003a1 358 #define MSR_P4_CRU_ESCR0 0x000003b8 359 #define MSR_P4_CRU_ESCR1 0x000003b9 360 #define MSR_P4_CRU_ESCR2 0x000003cc 361 #define MSR_P4_CRU_ESCR3 0x000003cd 362 #define MSR_P4_CRU_ESCR4 0x000003e0 363 #define MSR_P4_CRU_ESCR5 0x000003e1 364 #define MSR_P4_DAC_ESCR0 0x000003a8 365 #define MSR_P4_DAC_ESCR1 0x000003a9 366 #define MSR_P4_FIRM_ESCR0 0x000003a4 367 #define MSR_P4_FIRM_ESCR1 0x000003a5 368 #define MSR_P4_FLAME_ESCR0 0x000003a6 369 #define MSR_P4_FLAME_ESCR1 0x000003a7 370 #define MSR_P4_FSB_ESCR0 0x000003a2 371 #define MSR_P4_FSB_ESCR1 0x000003a3 372 #define MSR_P4_IQ_ESCR0 0x000003ba 373 #define MSR_P4_IQ_ESCR1 0x000003bb 374 #define MSR_P4_IS_ESCR0 0x000003b4 375 #define MSR_P4_IS_ESCR1 0x000003b5 376 #define MSR_P4_ITLB_ESCR0 0x000003b6 377 #define MSR_P4_ITLB_ESCR1 0x000003b7 378 #define MSR_P4_IX_ESCR0 0x000003c8 379 #define MSR_P4_IX_ESCR1 0x000003c9 380 #define MSR_P4_MOB_ESCR0 0x000003aa 381 #define MSR_P4_MOB_ESCR1 0x000003ab 382 #define MSR_P4_MS_ESCR0 0x000003c0 383 #define MSR_P4_MS_ESCR1 0x000003c1 384 #define MSR_P4_PMH_ESCR0 0x000003ac 385 #define MSR_P4_PMH_ESCR1 0x000003ad 386 #define MSR_P4_RAT_ESCR0 0x000003bc 387 #define MSR_P4_RAT_ESCR1 0x000003bd 388 #define MSR_P4_SAAT_ESCR0 0x000003ae 389 #define MSR_P4_SAAT_ESCR1 0x000003af 390 #define MSR_P4_SSU_ESCR0 0x000003be 391 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 392 393 #define MSR_P4_TBPU_ESCR0 0x000003c2 394 #define MSR_P4_TBPU_ESCR1 0x000003c3 395 #define MSR_P4_TC_ESCR0 0x000003c4 396 #define MSR_P4_TC_ESCR1 0x000003c5 397 #define MSR_P4_U2L_ESCR0 0x000003b0 398 #define MSR_P4_U2L_ESCR1 0x000003b1 399 400 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 401 402 /* Intel Core-based CPU performance counters */ 403 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 404 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 405 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 406 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 407 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 408 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 409 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 410 411 /* Geode defined MSRs */ 412 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 413 414 /* Intel VT MSRs */ 415 #define MSR_IA32_VMX_BASIC 0x00000480 416 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 417 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 418 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 419 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 420 #define MSR_IA32_VMX_MISC 0x00000485 421 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 422 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 423 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 424 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 425 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 426 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 427 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 428 #define MSR_IA32_VMX_TRUE_PIN 0x0000048d 429 #define MSR_IA32_VMX_TRUE_PROC 0x0000048e 430 #define MSR_IA32_VMX_TRUE_EXIT 0x0000048f 431 #define MSR_IA32_VMX_TRUE_ENTRY 0x00000490 432 433 /* MSR_IA32_VMX_MISC bits */ 434 #define MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) 435 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 436 437 #define MSR_IA32_TSCDEADLINE 0x000006e0 438 439 /* AMD-V MSRs */ 440 441 #define MSR_AMD64_TSC_RATIO 0xc0000104 442 #define MSR_VM_CR 0xc0010114 443 #define MSR_VM_IGNNE 0xc0010115 444 #define MSR_VM_HSAVE_PA 0xc0010117 445 446 #endif /* _X86_MSR_H_ */ 447