1 #ifndef _ASM_X86_MSR_INDEX_H 2 #define _ASM_X86_MSR_INDEX_H 3 4 /* CPU model specific register (MSR) numbers */ 5 6 /* x86-64 specific MSRs */ 7 #define MSR_EFER 0xc0000080 /* extended feature register */ 8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17 /* EFER bits: */ 18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19 #define _EFER_LME 8 /* Long mode enable */ 20 #define _EFER_LMA 10 /* Long mode active (read-only) */ 21 #define _EFER_NX 11 /* No execute enable */ 22 #define _EFER_SVME 12 /* Enable virtualization */ 23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26 #define EFER_SCE (1<<_EFER_SCE) 27 #define EFER_LME (1<<_EFER_LME) 28 #define EFER_LMA (1<<_EFER_LMA) 29 #define EFER_NX (1<<_EFER_NX) 30 #define EFER_SVME (1<<_EFER_SVME) 31 #define EFER_LMSLE (1<<_EFER_LMSLE) 32 #define EFER_FFXSR (1<<_EFER_FFXSR) 33 34 /* Intel MSRs. Some also available on other CPUs */ 35 #define MSR_IA32_PERFCTR0 0x000000c1 36 #define MSR_IA32_PERFCTR1 0x000000c2 37 #define MSR_FSB_FREQ 0x000000cd 38 39 #define MSR_MTRRcap 0x000000fe 40 #define MSR_IA32_BBL_CR_CTL 0x00000119 41 42 #define MSR_IA32_SYSENTER_CS 0x00000174 43 #define MSR_IA32_SYSENTER_ESP 0x00000175 44 #define MSR_IA32_SYSENTER_EIP 0x00000176 45 46 #define MSR_IA32_MCG_CAP 0x00000179 47 #define MSR_IA32_MCG_STATUS 0x0000017a 48 #define MSR_IA32_MCG_CTL 0x0000017b 49 50 #define MSR_IA32_PEBS_ENABLE 0x000003f1 51 #define MSR_IA32_DS_AREA 0x00000600 52 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 53 54 #define MSR_MTRRfix64K_00000 0x00000250 55 #define MSR_MTRRfix16K_80000 0x00000258 56 #define MSR_MTRRfix16K_A0000 0x00000259 57 #define MSR_MTRRfix4K_C0000 0x00000268 58 #define MSR_MTRRfix4K_C8000 0x00000269 59 #define MSR_MTRRfix4K_D0000 0x0000026a 60 #define MSR_MTRRfix4K_D8000 0x0000026b 61 #define MSR_MTRRfix4K_E0000 0x0000026c 62 #define MSR_MTRRfix4K_E8000 0x0000026d 63 #define MSR_MTRRfix4K_F0000 0x0000026e 64 #define MSR_MTRRfix4K_F8000 0x0000026f 65 #define MSR_MTRRdefType 0x000002ff 66 67 #define MSR_IA32_CR_PAT 0x00000277 68 69 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 70 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 71 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 72 #define MSR_IA32_LASTINTFROMIP 0x000001dd 73 #define MSR_IA32_LASTINTTOIP 0x000001de 74 75 /* DEBUGCTLMSR bits (others vary by model): */ 76 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 77 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 78 #define DEBUGCTLMSR_TR (1UL << 6) 79 #define DEBUGCTLMSR_BTS (1UL << 7) 80 #define DEBUGCTLMSR_BTINT (1UL << 8) 81 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 82 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 83 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 84 85 #define MSR_IA32_MC0_CTL 0x00000400 86 #define MSR_IA32_MC0_STATUS 0x00000401 87 #define MSR_IA32_MC0_ADDR 0x00000402 88 #define MSR_IA32_MC0_MISC 0x00000403 89 90 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 91 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 92 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 93 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 94 95 /* These are consecutive and not in the normal 4er MCE bank block */ 96 #define MSR_IA32_MC0_CTL2 0x00000280 97 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 98 99 #define CMCI_EN (1ULL << 30) 100 #define CMCI_THRESHOLD_MASK 0xffffULL 101 102 #define MSR_P6_PERFCTR0 0x000000c1 103 #define MSR_P6_PERFCTR1 0x000000c2 104 #define MSR_P6_EVNTSEL0 0x00000186 105 #define MSR_P6_EVNTSEL1 0x00000187 106 107 /* AMD64 MSRs. Not complete. See the architecture manual for a more 108 complete list. */ 109 110 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 111 #define MSR_AMD64_NB_CFG 0xc001001f 112 #define MSR_AMD64_PATCH_LOADER 0xc0010020 113 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 114 #define MSR_AMD64_OSVW_STATUS 0xc0010141 115 #define MSR_AMD64_DC_CFG 0xc0011022 116 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 117 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 118 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 119 #define MSR_AMD64_IBSOPCTL 0xc0011033 120 #define MSR_AMD64_IBSOPRIP 0xc0011034 121 #define MSR_AMD64_IBSOPDATA 0xc0011035 122 #define MSR_AMD64_IBSOPDATA2 0xc0011036 123 #define MSR_AMD64_IBSOPDATA3 0xc0011037 124 #define MSR_AMD64_IBSDCLINAD 0xc0011038 125 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 126 #define MSR_AMD64_IBSCTL 0xc001103a 127 128 /* Fam 10h MSRs */ 129 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 130 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 131 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 132 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 133 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff 134 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 135 #define MSR_FAM10H_NODE_ID 0xc001100c 136 137 /* K8 MSRs */ 138 #define MSR_K8_TOP_MEM1 0xc001001a 139 #define MSR_K8_TOP_MEM2 0xc001001d 140 #define MSR_K8_SYSCFG 0xc0010010 141 #define MSR_K8_INT_PENDING_MSG 0xc0010055 142 /* C1E active bits in int pending message */ 143 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 144 #define MSR_K8_TSEG_ADDR 0xc0010112 145 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 146 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 147 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 148 149 /* K7 MSRs */ 150 #define MSR_K7_EVNTSEL0 0xc0010000 151 #define MSR_K7_PERFCTR0 0xc0010004 152 #define MSR_K7_EVNTSEL1 0xc0010001 153 #define MSR_K7_PERFCTR1 0xc0010005 154 #define MSR_K7_EVNTSEL2 0xc0010002 155 #define MSR_K7_PERFCTR2 0xc0010006 156 #define MSR_K7_EVNTSEL3 0xc0010003 157 #define MSR_K7_PERFCTR3 0xc0010007 158 #define MSR_K7_CLK_CTL 0xc001001b 159 #define MSR_K7_HWCR 0xc0010015 160 #define MSR_K7_FID_VID_CTL 0xc0010041 161 #define MSR_K7_FID_VID_STATUS 0xc0010042 162 163 /* K6 MSRs */ 164 #define MSR_K6_EFER 0xc0000080 165 #define MSR_K6_STAR 0xc0000081 166 #define MSR_K6_WHCR 0xc0000082 167 #define MSR_K6_UWCCR 0xc0000085 168 #define MSR_K6_EPMR 0xc0000086 169 #define MSR_K6_PSOR 0xc0000087 170 #define MSR_K6_PFIR 0xc0000088 171 172 /* Centaur-Hauls/IDT defined MSRs. */ 173 #define MSR_IDT_FCR1 0x00000107 174 #define MSR_IDT_FCR2 0x00000108 175 #define MSR_IDT_FCR3 0x00000109 176 #define MSR_IDT_FCR4 0x0000010a 177 178 #define MSR_IDT_MCR0 0x00000110 179 #define MSR_IDT_MCR1 0x00000111 180 #define MSR_IDT_MCR2 0x00000112 181 #define MSR_IDT_MCR3 0x00000113 182 #define MSR_IDT_MCR4 0x00000114 183 #define MSR_IDT_MCR5 0x00000115 184 #define MSR_IDT_MCR6 0x00000116 185 #define MSR_IDT_MCR7 0x00000117 186 #define MSR_IDT_MCR_CTRL 0x00000120 187 188 /* VIA Cyrix defined MSRs*/ 189 #define MSR_VIA_FCR 0x00001107 190 #define MSR_VIA_LONGHAUL 0x0000110a 191 #define MSR_VIA_RNG 0x0000110b 192 #define MSR_VIA_BCR2 0x00001147 193 194 /* Transmeta defined MSRs */ 195 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 196 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 197 #define MSR_TMTA_LRTI_READOUT 0x80868018 198 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 199 200 /* Intel defined MSRs. */ 201 #define MSR_IA32_P5_MC_ADDR 0x00000000 202 #define MSR_IA32_P5_MC_TYPE 0x00000001 203 #define MSR_IA32_TSC 0x00000010 204 #define MSR_IA32_PLATFORM_ID 0x00000017 205 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 206 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 207 208 #define FEATURE_CONTROL_LOCKED (1<<0) 209 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 210 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 211 212 #define MSR_IA32_APICBASE 0x0000001b 213 #define MSR_IA32_APICBASE_BSP (1<<8) 214 #define MSR_IA32_APICBASE_ENABLE (1<<11) 215 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 216 217 #define MSR_IA32_UCODE_WRITE 0x00000079 218 #define MSR_IA32_UCODE_REV 0x0000008b 219 220 #define MSR_IA32_PERF_STATUS 0x00000198 221 #define MSR_IA32_PERF_CTL 0x00000199 222 223 #define MSR_IA32_MPERF 0x000000e7 224 #define MSR_IA32_APERF 0x000000e8 225 226 #define MSR_IA32_THERM_CONTROL 0x0000019a 227 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 228 229 #define THERM_INT_LOW_ENABLE (1 << 0) 230 #define THERM_INT_HIGH_ENABLE (1 << 1) 231 232 #define MSR_IA32_THERM_STATUS 0x0000019c 233 234 #define THERM_STATUS_PROCHOT (1 << 0) 235 236 #define MSR_THERM2_CTL 0x0000019d 237 238 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 239 240 #define MSR_IA32_MISC_ENABLE 0x000001a0 241 242 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 243 244 /* MISC_ENABLE bits: architectural */ 245 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 246 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 247 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 248 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 249 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 250 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 251 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 252 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 253 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 254 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 255 256 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 257 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 258 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 259 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 260 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 261 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 262 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 263 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 264 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 265 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 266 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 267 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 268 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 269 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 270 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 271 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 272 273 /* P4/Xeon+ specific */ 274 #define MSR_IA32_MCG_EAX 0x00000180 275 #define MSR_IA32_MCG_EBX 0x00000181 276 #define MSR_IA32_MCG_ECX 0x00000182 277 #define MSR_IA32_MCG_EDX 0x00000183 278 #define MSR_IA32_MCG_ESI 0x00000184 279 #define MSR_IA32_MCG_EDI 0x00000185 280 #define MSR_IA32_MCG_EBP 0x00000186 281 #define MSR_IA32_MCG_ESP 0x00000187 282 #define MSR_IA32_MCG_EFLAGS 0x00000188 283 #define MSR_IA32_MCG_EIP 0x00000189 284 #define MSR_IA32_MCG_RESERVED 0x0000018a 285 286 /* Pentium IV performance counter MSRs */ 287 #define MSR_P4_BPU_PERFCTR0 0x00000300 288 #define MSR_P4_BPU_PERFCTR1 0x00000301 289 #define MSR_P4_BPU_PERFCTR2 0x00000302 290 #define MSR_P4_BPU_PERFCTR3 0x00000303 291 #define MSR_P4_MS_PERFCTR0 0x00000304 292 #define MSR_P4_MS_PERFCTR1 0x00000305 293 #define MSR_P4_MS_PERFCTR2 0x00000306 294 #define MSR_P4_MS_PERFCTR3 0x00000307 295 #define MSR_P4_FLAME_PERFCTR0 0x00000308 296 #define MSR_P4_FLAME_PERFCTR1 0x00000309 297 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 298 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 299 #define MSR_P4_IQ_PERFCTR0 0x0000030c 300 #define MSR_P4_IQ_PERFCTR1 0x0000030d 301 #define MSR_P4_IQ_PERFCTR2 0x0000030e 302 #define MSR_P4_IQ_PERFCTR3 0x0000030f 303 #define MSR_P4_IQ_PERFCTR4 0x00000310 304 #define MSR_P4_IQ_PERFCTR5 0x00000311 305 #define MSR_P4_BPU_CCCR0 0x00000360 306 #define MSR_P4_BPU_CCCR1 0x00000361 307 #define MSR_P4_BPU_CCCR2 0x00000362 308 #define MSR_P4_BPU_CCCR3 0x00000363 309 #define MSR_P4_MS_CCCR0 0x00000364 310 #define MSR_P4_MS_CCCR1 0x00000365 311 #define MSR_P4_MS_CCCR2 0x00000366 312 #define MSR_P4_MS_CCCR3 0x00000367 313 #define MSR_P4_FLAME_CCCR0 0x00000368 314 #define MSR_P4_FLAME_CCCR1 0x00000369 315 #define MSR_P4_FLAME_CCCR2 0x0000036a 316 #define MSR_P4_FLAME_CCCR3 0x0000036b 317 #define MSR_P4_IQ_CCCR0 0x0000036c 318 #define MSR_P4_IQ_CCCR1 0x0000036d 319 #define MSR_P4_IQ_CCCR2 0x0000036e 320 #define MSR_P4_IQ_CCCR3 0x0000036f 321 #define MSR_P4_IQ_CCCR4 0x00000370 322 #define MSR_P4_IQ_CCCR5 0x00000371 323 #define MSR_P4_ALF_ESCR0 0x000003ca 324 #define MSR_P4_ALF_ESCR1 0x000003cb 325 #define MSR_P4_BPU_ESCR0 0x000003b2 326 #define MSR_P4_BPU_ESCR1 0x000003b3 327 #define MSR_P4_BSU_ESCR0 0x000003a0 328 #define MSR_P4_BSU_ESCR1 0x000003a1 329 #define MSR_P4_CRU_ESCR0 0x000003b8 330 #define MSR_P4_CRU_ESCR1 0x000003b9 331 #define MSR_P4_CRU_ESCR2 0x000003cc 332 #define MSR_P4_CRU_ESCR3 0x000003cd 333 #define MSR_P4_CRU_ESCR4 0x000003e0 334 #define MSR_P4_CRU_ESCR5 0x000003e1 335 #define MSR_P4_DAC_ESCR0 0x000003a8 336 #define MSR_P4_DAC_ESCR1 0x000003a9 337 #define MSR_P4_FIRM_ESCR0 0x000003a4 338 #define MSR_P4_FIRM_ESCR1 0x000003a5 339 #define MSR_P4_FLAME_ESCR0 0x000003a6 340 #define MSR_P4_FLAME_ESCR1 0x000003a7 341 #define MSR_P4_FSB_ESCR0 0x000003a2 342 #define MSR_P4_FSB_ESCR1 0x000003a3 343 #define MSR_P4_IQ_ESCR0 0x000003ba 344 #define MSR_P4_IQ_ESCR1 0x000003bb 345 #define MSR_P4_IS_ESCR0 0x000003b4 346 #define MSR_P4_IS_ESCR1 0x000003b5 347 #define MSR_P4_ITLB_ESCR0 0x000003b6 348 #define MSR_P4_ITLB_ESCR1 0x000003b7 349 #define MSR_P4_IX_ESCR0 0x000003c8 350 #define MSR_P4_IX_ESCR1 0x000003c9 351 #define MSR_P4_MOB_ESCR0 0x000003aa 352 #define MSR_P4_MOB_ESCR1 0x000003ab 353 #define MSR_P4_MS_ESCR0 0x000003c0 354 #define MSR_P4_MS_ESCR1 0x000003c1 355 #define MSR_P4_PMH_ESCR0 0x000003ac 356 #define MSR_P4_PMH_ESCR1 0x000003ad 357 #define MSR_P4_RAT_ESCR0 0x000003bc 358 #define MSR_P4_RAT_ESCR1 0x000003bd 359 #define MSR_P4_SAAT_ESCR0 0x000003ae 360 #define MSR_P4_SAAT_ESCR1 0x000003af 361 #define MSR_P4_SSU_ESCR0 0x000003be 362 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 363 364 #define MSR_P4_TBPU_ESCR0 0x000003c2 365 #define MSR_P4_TBPU_ESCR1 0x000003c3 366 #define MSR_P4_TC_ESCR0 0x000003c4 367 #define MSR_P4_TC_ESCR1 0x000003c5 368 #define MSR_P4_U2L_ESCR0 0x000003b0 369 #define MSR_P4_U2L_ESCR1 0x000003b1 370 371 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 372 373 /* Intel Core-based CPU performance counters */ 374 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 375 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 376 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 377 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 378 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 379 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 380 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 381 382 /* Geode defined MSRs */ 383 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 384 385 /* Intel VT MSRs */ 386 #define MSR_IA32_VMX_BASIC 0x00000480 387 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 388 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 389 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 390 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 391 #define MSR_IA32_VMX_MISC 0x00000485 392 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 393 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 394 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 395 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 396 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 397 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 398 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 399 #define MSR_IA32_VMX_TRUE_PIN 0x0000048d 400 #define MSR_IA32_VMX_TRUE_PROC 0x0000048e 401 #define MSR_IA32_VMX_TRUE_EXIT 0x0000048f 402 #define MSR_IA32_VMX_TRUE_ENTRY 0x00000490 403 404 405 /* AMD-V MSRs */ 406 407 #define MSR_VM_CR 0xc0010114 408 #define MSR_VM_IGNNE 0xc0010115 409 #define MSR_VM_HSAVE_PA 0xc0010117 410 411 /* Define synthetic interrupt controller model specific registers. */ 412 #define HV_X64_MSR_SCONTROL 0x40000080 413 #define HV_X64_MSR_SVERSION 0x40000081 414 #define HV_X64_MSR_SIEFP 0x40000082 415 #define HV_X64_MSR_SIMP 0x40000083 416 #define HV_X64_MSR_EOM 0x40000084 417 #define HV_X64_MSR_SINT0 0x40000090 418 #define HV_X64_MSR_SINT1 0x40000091 419 #define HV_X64_MSR_SINT2 0x40000092 420 #define HV_X64_MSR_SINT3 0x40000093 421 #define HV_X64_MSR_SINT4 0x40000094 422 #define HV_X64_MSR_SINT5 0x40000095 423 #define HV_X64_MSR_SINT6 0x40000096 424 #define HV_X64_MSR_SINT7 0x40000097 425 #define HV_X64_MSR_SINT8 0x40000098 426 #define HV_X64_MSR_SINT9 0x40000099 427 #define HV_X64_MSR_SINT10 0x4000009A 428 #define HV_X64_MSR_SINT11 0x4000009B 429 #define HV_X64_MSR_SINT12 0x4000009C 430 #define HV_X64_MSR_SINT13 0x4000009D 431 #define HV_X64_MSR_SINT14 0x4000009E 432 #define HV_X64_MSR_SINT15 0x4000009F 433 434 #endif /* _ASM_X86_MSR_INDEX_H */ 435