1 #ifndef _X86_APIC_DEFS_H_ 2 #define _X86_APIC_DEFS_H_ 3 4 /* 5 * Abuse this header file to hold the number of max-cpus and the size of the 6 * per-CPU stack/data area, making them available both in C and ASM. One page 7 * for per-CPU, and two pages for the stack (plus some buffer in-between). 8 */ 9 #define MAX_TEST_CPUS (255) 10 #define PER_CPU_SIZE (3 * 4096) 11 12 /* 13 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 14 * 15 * Alan Cox <Alan.Cox@linux.org>, 1995. 16 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 17 */ 18 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 19 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 20 21 #define APIC_BSP (1UL << 8) 22 #define APIC_EXTD (1UL << 10) 23 #define APIC_EN (1UL << 11) 24 25 #define APIC_ID 0x20 26 27 #define APIC_LVR 0x30 28 #define APIC_LVR_MASK 0xFF00FF 29 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 30 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 31 #ifdef CONFIG_X86_32 32 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 33 #else 34 # define APIC_INTEGRATED(x) (1) 35 #endif 36 #define APIC_XAPIC(x) ((x) >= 0x14) 37 #define APIC_TASKPRI 0x80 38 #define APIC_TPRI_MASK 0xFFu 39 #define APIC_ARBPRI 0x90 40 #define APIC_ARBPRI_MASK 0xFFu 41 #define APIC_PROCPRI 0xA0 42 #define APIC_EOI 0xB0 43 #define APIC_EIO_ACK 0x0 44 #define APIC_RRR 0xC0 45 #define APIC_LDR 0xD0 46 #define APIC_LDR_MASK (0xFFu << 24) 47 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 48 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 49 #define APIC_ALL_CPUS 0xFFu 50 #define APIC_DFR 0xE0 51 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 52 #define APIC_DFR_FLAT 0xFFFFFFFFul 53 #define APIC_SPIV 0xF0 54 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 55 #define APIC_SPIV_APIC_ENABLED (1 << 8) 56 #define APIC_ISR 0x100 57 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 58 #define APIC_TMR 0x180 59 #define APIC_IRR 0x200 60 #define APIC_ESR 0x280 61 #define APIC_ESR_SEND_CS 0x00001 62 #define APIC_ESR_RECV_CS 0x00002 63 #define APIC_ESR_SEND_ACC 0x00004 64 #define APIC_ESR_RECV_ACC 0x00008 65 #define APIC_ESR_SENDILL 0x00020 66 #define APIC_ESR_RECVILL 0x00040 67 #define APIC_ESR_ILLREGA 0x00080 68 #define APIC_CMCI 0x2F0 69 #define APIC_ICR 0x300 70 #define APIC_DEST_SELF 0x40000 71 #define APIC_DEST_ALLINC 0x80000 72 #define APIC_DEST_ALLBUT 0xC0000 73 #define APIC_ICR_RR_MASK 0x30000 74 #define APIC_ICR_RR_INVALID 0x00000 75 #define APIC_ICR_RR_INPROG 0x10000 76 #define APIC_ICR_RR_VALID 0x20000 77 #define APIC_INT_LEVELTRIG 0x08000 78 #define APIC_INT_ASSERT 0x04000 79 #define APIC_ICR_BUSY 0x01000 80 #define APIC_DEST_LOGICAL 0x00800 81 #define APIC_DEST_PHYSICAL 0x00000 82 #define APIC_DM_FIXED 0x00000 83 #define APIC_DM_LOWEST 0x00100 84 #define APIC_DM_SMI 0x00200 85 #define APIC_DM_REMRD 0x00300 86 #define APIC_DM_NMI 0x00400 87 #define APIC_DM_INIT 0x00500 88 #define APIC_DM_STARTUP 0x00600 89 #define APIC_DM_EXTINT 0x00700 90 #define APIC_VECTOR_MASK 0x000FF 91 #define APIC_ICR2 0x310 92 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 93 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 94 #define APIC_LVTT 0x320 95 #define APIC_LVTTHMR 0x330 96 #define APIC_LVTPC 0x340 97 #define APIC_LVT0 0x350 98 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 99 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 100 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) 101 #define APIC_TIMER_BASE_CLKIN 0x0 102 #define APIC_TIMER_BASE_TMBASE 0x1 103 #define APIC_TIMER_BASE_DIV 0x2 104 #define APIC_LVT_TIMER_MASK (3 << 17) 105 #define APIC_LVT_TIMER_ONESHOT (0 << 17) 106 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 107 #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 108 #define APIC_LVT_MASKED (1 << 16) 109 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) 110 #define APIC_LVT_REMOTE_IRR (1 << 14) 111 #define APIC_INPUT_POLARITY (1 << 13) 112 #define APIC_SEND_PENDING (1 << 12) 113 #define APIC_MODE_MASK 0x700 114 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 115 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 116 #define APIC_MODE_FIXED 0x0 117 #define APIC_MODE_NMI 0x4 118 #define APIC_MODE_EXTINT 0x7 119 #define APIC_LVT1 0x360 120 #define APIC_LVTERR 0x370 121 #define APIC_TMICT 0x380 122 #define APIC_TMCCT 0x390 123 #define APIC_TDCR 0x3E0 124 #define APIC_SELF_IPI 0x3F0 125 #define APIC_TDR_DIV_TMBASE (1 << 2) 126 #define APIC_TDR_DIV_1 0xB 127 #define APIC_TDR_DIV_2 0x0 128 #define APIC_TDR_DIV_4 0x1 129 #define APIC_TDR_DIV_8 0x2 130 #define APIC_TDR_DIV_16 0x3 131 #define APIC_TDR_DIV_32 0x8 132 #define APIC_TDR_DIV_64 0x9 133 #define APIC_TDR_DIV_128 0xA 134 #define APIC_EILVT0 0x500 135 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 136 #define APIC_EILVT_NR_AMD_10H 4 137 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 138 #define APIC_EILVT_MSG_FIX 0x0 139 #define APIC_EILVT_MSG_SMI 0x2 140 #define APIC_EILVT_MSG_NMI 0x4 141 #define APIC_EILVT_MSG_EXT 0x7 142 #define APIC_EILVT_MASKED (1 << 16) 143 #define APIC_EILVT1 0x510 144 #define APIC_EILVT2 0x520 145 #define APIC_EILVT3 0x530 146 147 #define APIC_BASE_MSR 0x800 148 149 #endif /* _X86_APIC_DEFS_H_ */ 150