1 #ifndef _ASM_X86_APICDEF_H 2 #define _ASM_X86_APICDEF_H 3 4 /* 5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 6 * 7 * Alan Cox <Alan.Cox@linux.org>, 1995. 8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 9 */ 10 11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 12 13 #define APIC_ID 0x20 14 15 #define APIC_LVR 0x30 16 #define APIC_LVR_MASK 0xFF00FF 17 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 18 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 19 #ifdef CONFIG_X86_32 20 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 21 #else 22 # define APIC_INTEGRATED(x) (1) 23 #endif 24 #define APIC_XAPIC(x) ((x) >= 0x14) 25 #define APIC_TASKPRI 0x80 26 #define APIC_TPRI_MASK 0xFFu 27 #define APIC_ARBPRI 0x90 28 #define APIC_ARBPRI_MASK 0xFFu 29 #define APIC_PROCPRI 0xA0 30 #define APIC_EOI 0xB0 31 #define APIC_EIO_ACK 0x0 32 #define APIC_RRR 0xC0 33 #define APIC_LDR 0xD0 34 #define APIC_LDR_MASK (0xFFu << 24) 35 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 36 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 37 #define APIC_ALL_CPUS 0xFFu 38 #define APIC_DFR 0xE0 39 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 40 #define APIC_DFR_FLAT 0xFFFFFFFFul 41 #define APIC_SPIV 0xF0 42 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 43 #define APIC_SPIV_APIC_ENABLED (1 << 8) 44 #define APIC_ISR 0x100 45 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 46 #define APIC_TMR 0x180 47 #define APIC_IRR 0x200 48 #define APIC_ESR 0x280 49 #define APIC_ESR_SEND_CS 0x00001 50 #define APIC_ESR_RECV_CS 0x00002 51 #define APIC_ESR_SEND_ACC 0x00004 52 #define APIC_ESR_RECV_ACC 0x00008 53 #define APIC_ESR_SENDILL 0x00020 54 #define APIC_ESR_RECVILL 0x00040 55 #define APIC_ESR_ILLREGA 0x00080 56 #define APIC_ICR 0x300 57 #define APIC_DEST_SELF 0x40000 58 #define APIC_DEST_ALLINC 0x80000 59 #define APIC_DEST_ALLBUT 0xC0000 60 #define APIC_ICR_RR_MASK 0x30000 61 #define APIC_ICR_RR_INVALID 0x00000 62 #define APIC_ICR_RR_INPROG 0x10000 63 #define APIC_ICR_RR_VALID 0x20000 64 #define APIC_INT_LEVELTRIG 0x08000 65 #define APIC_INT_ASSERT 0x04000 66 #define APIC_ICR_BUSY 0x01000 67 #define APIC_DEST_LOGICAL 0x00800 68 #define APIC_DEST_PHYSICAL 0x00000 69 #define APIC_DM_FIXED 0x00000 70 #define APIC_DM_LOWEST 0x00100 71 #define APIC_DM_SMI 0x00200 72 #define APIC_DM_REMRD 0x00300 73 #define APIC_DM_NMI 0x00400 74 #define APIC_DM_INIT 0x00500 75 #define APIC_DM_STARTUP 0x00600 76 #define APIC_DM_EXTINT 0x00700 77 #define APIC_VECTOR_MASK 0x000FF 78 #define APIC_ICR2 0x310 79 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 80 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 81 #define APIC_LVTT 0x320 82 #define APIC_LVTTHMR 0x330 83 #define APIC_LVTPC 0x340 84 #define APIC_LVT0 0x350 85 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 86 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 87 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) 88 #define APIC_TIMER_BASE_CLKIN 0x0 89 #define APIC_TIMER_BASE_TMBASE 0x1 90 #define APIC_TIMER_BASE_DIV 0x2 91 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 92 #define APIC_LVT_MASKED (1 << 16) 93 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) 94 #define APIC_LVT_REMOTE_IRR (1 << 14) 95 #define APIC_INPUT_POLARITY (1 << 13) 96 #define APIC_SEND_PENDING (1 << 12) 97 #define APIC_MODE_MASK 0x700 98 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 99 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 100 #define APIC_MODE_FIXED 0x0 101 #define APIC_MODE_NMI 0x4 102 #define APIC_MODE_EXTINT 0x7 103 #define APIC_LVT1 0x360 104 #define APIC_LVTERR 0x370 105 #define APIC_TMICT 0x380 106 #define APIC_TMCCT 0x390 107 #define APIC_TDCR 0x3E0 108 #define APIC_SELF_IPI 0x3F0 109 #define APIC_TDR_DIV_TMBASE (1 << 2) 110 #define APIC_TDR_DIV_1 0xB 111 #define APIC_TDR_DIV_2 0x0 112 #define APIC_TDR_DIV_4 0x1 113 #define APIC_TDR_DIV_8 0x2 114 #define APIC_TDR_DIV_16 0x3 115 #define APIC_TDR_DIV_32 0x8 116 #define APIC_TDR_DIV_64 0x9 117 #define APIC_TDR_DIV_128 0xA 118 #define APIC_EILVT0 0x500 119 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 120 #define APIC_EILVT_NR_AMD_10H 4 121 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 122 #define APIC_EILVT_MSG_FIX 0x0 123 #define APIC_EILVT_MSG_SMI 0x2 124 #define APIC_EILVT_MSG_NMI 0x4 125 #define APIC_EILVT_MSG_EXT 0x7 126 #define APIC_EILVT_MASKED (1 << 16) 127 #define APIC_EILVT1 0x510 128 #define APIC_EILVT2 0x520 129 #define APIC_EILVT3 0x530 130 131 #define APIC_BASE_MSR 0x800 132 133 #endif /* _ASM_X86_APICDEF_H */ 134