1 #ifndef _X86_APIC_DEFS_H_ 2 #define _X86_APIC_DEFS_H_ 3 4 /* 5 * Abuse this header file to hold the number of max-cpus, making it available 6 * both in C and ASM 7 */ 8 9 #define MAX_TEST_CPUS (255) 10 11 /* 12 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 13 * 14 * Alan Cox <Alan.Cox@linux.org>, 1995. 15 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 16 */ 17 18 #define APIC_DEFAULT_PHYS_BASE 0xfee00000 19 #define APIC_BSP (1UL << 8) 20 #define APIC_EXTD (1UL << 10) 21 #define APIC_EN (1UL << 11) 22 23 #define APIC_ID 0x20 24 25 #define APIC_LVR 0x30 26 #define APIC_LVR_MASK 0xFF00FF 27 #define GET_APIC_VERSION(x) ((x) & 0xFFu) 28 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 29 #ifdef CONFIG_X86_32 30 # define APIC_INTEGRATED(x) ((x) & 0xF0u) 31 #else 32 # define APIC_INTEGRATED(x) (1) 33 #endif 34 #define APIC_XAPIC(x) ((x) >= 0x14) 35 #define APIC_TASKPRI 0x80 36 #define APIC_TPRI_MASK 0xFFu 37 #define APIC_ARBPRI 0x90 38 #define APIC_ARBPRI_MASK 0xFFu 39 #define APIC_PROCPRI 0xA0 40 #define APIC_EOI 0xB0 41 #define APIC_EIO_ACK 0x0 42 #define APIC_RRR 0xC0 43 #define APIC_LDR 0xD0 44 #define APIC_LDR_MASK (0xFFu << 24) 45 #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 46 #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 47 #define APIC_ALL_CPUS 0xFFu 48 #define APIC_DFR 0xE0 49 #define APIC_DFR_CLUSTER 0x0FFFFFFFul 50 #define APIC_DFR_FLAT 0xFFFFFFFFul 51 #define APIC_SPIV 0xF0 52 #define APIC_SPIV_FOCUS_DISABLED (1 << 9) 53 #define APIC_SPIV_APIC_ENABLED (1 << 8) 54 #define APIC_ISR 0x100 55 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 56 #define APIC_TMR 0x180 57 #define APIC_IRR 0x200 58 #define APIC_ESR 0x280 59 #define APIC_ESR_SEND_CS 0x00001 60 #define APIC_ESR_RECV_CS 0x00002 61 #define APIC_ESR_SEND_ACC 0x00004 62 #define APIC_ESR_RECV_ACC 0x00008 63 #define APIC_ESR_SENDILL 0x00020 64 #define APIC_ESR_RECVILL 0x00040 65 #define APIC_ESR_ILLREGA 0x00080 66 #define APIC_CMCI 0x2F0 67 #define APIC_ICR 0x300 68 #define APIC_DEST_SELF 0x40000 69 #define APIC_DEST_ALLINC 0x80000 70 #define APIC_DEST_ALLBUT 0xC0000 71 #define APIC_ICR_RR_MASK 0x30000 72 #define APIC_ICR_RR_INVALID 0x00000 73 #define APIC_ICR_RR_INPROG 0x10000 74 #define APIC_ICR_RR_VALID 0x20000 75 #define APIC_INT_LEVELTRIG 0x08000 76 #define APIC_INT_ASSERT 0x04000 77 #define APIC_ICR_BUSY 0x01000 78 #define APIC_DEST_LOGICAL 0x00800 79 #define APIC_DEST_PHYSICAL 0x00000 80 #define APIC_DM_FIXED 0x00000 81 #define APIC_DM_LOWEST 0x00100 82 #define APIC_DM_SMI 0x00200 83 #define APIC_DM_REMRD 0x00300 84 #define APIC_DM_NMI 0x00400 85 #define APIC_DM_INIT 0x00500 86 #define APIC_DM_STARTUP 0x00600 87 #define APIC_DM_EXTINT 0x00700 88 #define APIC_VECTOR_MASK 0x000FF 89 #define APIC_ICR2 0x310 90 #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 91 #define SET_APIC_DEST_FIELD(x) ((x) << 24) 92 #define APIC_LVTT 0x320 93 #define APIC_LVTTHMR 0x330 94 #define APIC_LVTPC 0x340 95 #define APIC_LVT0 0x350 96 #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 97 #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 98 #define SET_APIC_TIMER_BASE(x) (((x) << 18)) 99 #define APIC_TIMER_BASE_CLKIN 0x0 100 #define APIC_TIMER_BASE_TMBASE 0x1 101 #define APIC_TIMER_BASE_DIV 0x2 102 #define APIC_LVT_TIMER_MASK (3 << 17) 103 #define APIC_LVT_TIMER_ONESHOT (0 << 17) 104 #define APIC_LVT_TIMER_PERIODIC (1 << 17) 105 #define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 106 #define APIC_LVT_MASKED (1 << 16) 107 #define APIC_LVT_LEVEL_TRIGGER (1 << 15) 108 #define APIC_LVT_REMOTE_IRR (1 << 14) 109 #define APIC_INPUT_POLARITY (1 << 13) 110 #define APIC_SEND_PENDING (1 << 12) 111 #define APIC_MODE_MASK 0x700 112 #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 113 #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 114 #define APIC_MODE_FIXED 0x0 115 #define APIC_MODE_NMI 0x4 116 #define APIC_MODE_EXTINT 0x7 117 #define APIC_LVT1 0x360 118 #define APIC_LVTERR 0x370 119 #define APIC_TMICT 0x380 120 #define APIC_TMCCT 0x390 121 #define APIC_TDCR 0x3E0 122 #define APIC_SELF_IPI 0x3F0 123 #define APIC_TDR_DIV_TMBASE (1 << 2) 124 #define APIC_TDR_DIV_1 0xB 125 #define APIC_TDR_DIV_2 0x0 126 #define APIC_TDR_DIV_4 0x1 127 #define APIC_TDR_DIV_8 0x2 128 #define APIC_TDR_DIV_16 0x3 129 #define APIC_TDR_DIV_32 0x8 130 #define APIC_TDR_DIV_64 0x9 131 #define APIC_TDR_DIV_128 0xA 132 #define APIC_EILVT0 0x500 133 #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 134 #define APIC_EILVT_NR_AMD_10H 4 135 #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 136 #define APIC_EILVT_MSG_FIX 0x0 137 #define APIC_EILVT_MSG_SMI 0x2 138 #define APIC_EILVT_MSG_NMI 0x4 139 #define APIC_EILVT_MSG_EXT 0x7 140 #define APIC_EILVT_MASKED (1 << 16) 141 #define APIC_EILVT1 0x510 142 #define APIC_EILVT2 0x520 143 #define APIC_EILVT3 0x530 144 145 #define APIC_BASE_MSR 0x800 146 147 #endif /* _X86_APIC_DEFS_H_ */ 148