1fcdc04e0SPierre Morel /* SPDX-License-Identifier: GPL-2.0-only */ 2fcdc04e0SPierre Morel /* 3fcdc04e0SPierre Morel * Structures used to Store System Information 4fcdc04e0SPierre Morel * 5fcdc04e0SPierre Morel * Copyright IBM Corp. 2022 6fcdc04e0SPierre Morel */ 7fcdc04e0SPierre Morel 8fcdc04e0SPierre Morel #ifndef _S390X_STSI_H_ 9fcdc04e0SPierre Morel #define _S390X_STSI_H_ 10fcdc04e0SPierre Morel 11fcdc04e0SPierre Morel struct sysinfo_3_2_2 { 12fcdc04e0SPierre Morel uint8_t reserved[31]; 13fcdc04e0SPierre Morel uint8_t count; 14fcdc04e0SPierre Morel struct { 15fcdc04e0SPierre Morel uint8_t reserved2[4]; 16fcdc04e0SPierre Morel uint16_t total_cpus; 17fcdc04e0SPierre Morel uint16_t conf_cpus; 18fcdc04e0SPierre Morel uint16_t standby_cpus; 19fcdc04e0SPierre Morel uint16_t reserved_cpus; 20fcdc04e0SPierre Morel uint8_t name[8]; 21fcdc04e0SPierre Morel uint32_t caf; 22fcdc04e0SPierre Morel uint8_t cpi[16]; 23fcdc04e0SPierre Morel uint8_t reserved5[3]; 24fcdc04e0SPierre Morel uint8_t ext_name_encoding; 25fcdc04e0SPierre Morel uint32_t reserved3; 26fcdc04e0SPierre Morel uint8_t uuid[16]; 27fcdc04e0SPierre Morel } vm[8]; 28fcdc04e0SPierre Morel uint8_t reserved4[1504]; 29fcdc04e0SPierre Morel uint8_t ext_names[8][256]; 30fcdc04e0SPierre Morel }; 31fcdc04e0SPierre Morel 326f33f0b7SPierre Morel #define CPUS_TLE_RES_BITS 0x00fffffff8000000UL 336f33f0b7SPierre Morel struct topology_core { 346f33f0b7SPierre Morel uint8_t nl; 356f33f0b7SPierre Morel uint8_t reserved1[3]; 366f33f0b7SPierre Morel uint8_t reserved4:5; 376f33f0b7SPierre Morel uint8_t d:1; 386f33f0b7SPierre Morel uint8_t pp:2; 396f33f0b7SPierre Morel uint8_t type; 406f33f0b7SPierre Morel uint16_t origin; 416f33f0b7SPierre Morel uint64_t mask; 426f33f0b7SPierre Morel }; 436f33f0b7SPierre Morel 44*31ebf55bSNina Schoetterl-Glausch enum topology_polarization { 45*31ebf55bSNina Schoetterl-Glausch POLARIZATION_HORIZONTAL = 0, 46*31ebf55bSNina Schoetterl-Glausch POLARIZATION_VERTICAL_LOW = 1, 47*31ebf55bSNina Schoetterl-Glausch POLARIZATION_VERTICAL_MEDIUM = 2, 48*31ebf55bSNina Schoetterl-Glausch POLARIZATION_VERTICAL_HIGH = 3, 49*31ebf55bSNina Schoetterl-Glausch }; 50*31ebf55bSNina Schoetterl-Glausch 51*31ebf55bSNina Schoetterl-Glausch enum cpu_type { 52*31ebf55bSNina Schoetterl-Glausch CPU_TYPE_IFL = 3, 53*31ebf55bSNina Schoetterl-Glausch }; 54*31ebf55bSNina Schoetterl-Glausch 556f33f0b7SPierre Morel #define CONTAINER_TLE_RES_BITS 0x00ffffffffffff00UL 566f33f0b7SPierre Morel struct topology_container { 576f33f0b7SPierre Morel uint8_t nl; 586f33f0b7SPierre Morel uint8_t reserved[6]; 596f33f0b7SPierre Morel uint8_t id; 606f33f0b7SPierre Morel }; 616f33f0b7SPierre Morel 626f33f0b7SPierre Morel union topology_entry { 636f33f0b7SPierre Morel uint8_t nl; 646f33f0b7SPierre Morel struct topology_core cpu; 656f33f0b7SPierre Morel struct topology_container container; 666f33f0b7SPierre Morel }; 676f33f0b7SPierre Morel 686f33f0b7SPierre Morel #define CPU_TOPOLOGY_MAX_LEVEL 6 696f33f0b7SPierre Morel struct sysinfo_15_1_x { 706f33f0b7SPierre Morel uint8_t reserved0[2]; 716f33f0b7SPierre Morel uint16_t length; 726f33f0b7SPierre Morel uint8_t mag[CPU_TOPOLOGY_MAX_LEVEL]; 736f33f0b7SPierre Morel uint8_t reserved0a; 746f33f0b7SPierre Morel uint8_t mnest; 756f33f0b7SPierre Morel uint8_t reserved0c[4]; 766f33f0b7SPierre Morel union topology_entry tle[]; 776f33f0b7SPierre Morel }; 786f33f0b7SPierre Morel 79fcdc04e0SPierre Morel #endif /* _S390X_STSI_H_ */ 80