1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * s390x interrupt handling 4 * 5 * Copyright (c) 2017 Red Hat Inc 6 * 7 * Authors: 8 * David Hildenbrand <david@redhat.com> 9 */ 10 #include <libcflat.h> 11 #include <asm/barrier.h> 12 #include <sclp.h> 13 #include <interrupt.h> 14 #include <sie.h> 15 #include <fault.h> 16 #include <asm/page.h> 17 #include "smp.h" 18 19 /** 20 * expect_pgm_int - Expect a program interrupt on the current CPU. 21 */ 22 void expect_pgm_int(void) 23 { 24 THIS_CPU->pgm_int_expected = true; 25 lowcore.pgm_int_code = 0; 26 lowcore.trans_exc_id = 0; 27 mb(); 28 } 29 30 /** 31 * expect_ext_int - Expect an external interrupt on the current CPU. 32 */ 33 void expect_ext_int(void) 34 { 35 THIS_CPU->ext_int_expected = true; 36 lowcore.ext_int_code = 0; 37 mb(); 38 } 39 40 /** 41 * clear_pgm_int - Clear program interrupt information 42 * 43 * Clear program interrupt information, including the expected program 44 * interrupt flag. 45 * No program interrupts are expected after calling this function. 46 * 47 * Return: the program interrupt code before clearing 48 */ 49 uint16_t clear_pgm_int(void) 50 { 51 uint16_t code; 52 53 mb(); 54 code = lowcore.pgm_int_code; 55 lowcore.pgm_int_code = 0; 56 lowcore.trans_exc_id = 0; 57 THIS_CPU->pgm_int_expected = false; 58 return code; 59 } 60 61 /** 62 * check_pgm_int_code - Check the program interrupt code on the current CPU. 63 * @code the expected program interrupt code on the current CPU 64 * 65 * Check and report if the program interrupt on the current CPU matches the 66 * expected one. 67 */ 68 void check_pgm_int_code(uint16_t code) 69 { 70 mb(); 71 report(code == lowcore.pgm_int_code, 72 "Program interrupt: expected(%d) == received(%d)", code, 73 lowcore.pgm_int_code); 74 } 75 76 /** 77 * register_pgm_cleanup_func - Register a cleanup function for progam 78 * interrupts for the current CPU. 79 * @f the cleanup function to be registered on the current CPU 80 * 81 * Register a cleanup function to be called at the end of the normal 82 * interrupt handling for program interrupts for this CPU. 83 * 84 * Pass NULL to unregister a previously registered cleanup function. 85 */ 86 void register_pgm_cleanup_func(void (*f)(struct stack_frame_int *)) 87 { 88 THIS_CPU->pgm_cleanup_func = f; 89 } 90 91 /** 92 * register_ext_cleanup_func - Register a cleanup function for external 93 * interrupts for the current CPU. 94 * @f the cleanup function to be registered on the current CPU 95 * 96 * Register a cleanup function to be called at the end of the normal 97 * interrupt handling for external interrupts for this CPU. 98 * 99 * Pass NULL to unregister a previously registered cleanup function. 100 */ 101 void register_ext_cleanup_func(void (*f)(struct stack_frame_int *)) 102 { 103 THIS_CPU->ext_cleanup_func = f; 104 } 105 106 static void fixup_pgm_int(struct stack_frame_int *stack) 107 { 108 /* If we have an error on SIE we directly move to sie_exit */ 109 if (lowcore.pgm_old_psw.addr >= (uint64_t)&sie_entry && 110 lowcore.pgm_old_psw.addr <= (uint64_t)&sie_exit) { 111 lowcore.pgm_old_psw.addr = (uint64_t)&sie_exit; 112 } 113 114 switch (lowcore.pgm_int_code) { 115 case PGM_INT_CODE_PRIVILEGED_OPERATION: 116 /* Normal operation is in supervisor state, so this exception 117 * was produced intentionally and we should return to the 118 * supervisor state. 119 */ 120 lowcore.pgm_old_psw.mask &= ~PSW_MASK_PSTATE; 121 break; 122 case PGM_INT_CODE_PROTECTION: 123 /* Handling for iep.c test case. */ 124 if (prot_is_iep((union teid) { .val = lowcore.trans_exc_id })) 125 /* 126 * We branched to the instruction that caused 127 * the exception so we can use the return 128 * address in GR14 to jump back and continue 129 * executing test code. 130 */ 131 lowcore.pgm_old_psw.addr = stack->grs0[12]; 132 break; 133 case PGM_INT_CODE_SEGMENT_TRANSLATION: 134 case PGM_INT_CODE_PAGE_TRANSLATION: 135 case PGM_INT_CODE_TRACE_TABLE: 136 case PGM_INT_CODE_AFX_TRANSLATION: 137 case PGM_INT_CODE_ASX_TRANSLATION: 138 case PGM_INT_CODE_LX_TRANSLATION: 139 case PGM_INT_CODE_EX_TRANSLATION: 140 case PGM_INT_CODE_PRIMARY_AUTHORITY: 141 case PGM_INT_CODE_SECONDARY_AUTHORITY: 142 case PGM_INT_CODE_LFX_TRANSLATION: 143 case PGM_INT_CODE_LSX_TRANSLATION: 144 case PGM_INT_CODE_ALEN_TRANSLATION: 145 case PGM_INT_CODE_ALE_SEQUENCE: 146 case PGM_INT_CODE_ASTE_VALIDITY: 147 case PGM_INT_CODE_ASTE_SEQUENCE: 148 case PGM_INT_CODE_EXTENDED_AUTHORITY: 149 case PGM_INT_CODE_LSTE_SEQUENCE: 150 case PGM_INT_CODE_ASTE_INSTANCE: 151 case PGM_INT_CODE_STACK_FULL: 152 case PGM_INT_CODE_STACK_EMPTY: 153 case PGM_INT_CODE_STACK_SPECIFICATION: 154 case PGM_INT_CODE_STACK_TYPE: 155 case PGM_INT_CODE_STACK_OPERATION: 156 case PGM_INT_CODE_ASCE_TYPE: 157 case PGM_INT_CODE_REGION_FIRST_TRANS: 158 case PGM_INT_CODE_REGION_SECOND_TRANS: 159 case PGM_INT_CODE_REGION_THIRD_TRANS: 160 case PGM_INT_CODE_PER: 161 case PGM_INT_CODE_CRYPTO_OPERATION: 162 case PGM_INT_CODE_SECURE_STOR_ACCESS: 163 case PGM_INT_CODE_NON_SECURE_STOR_ACCESS: 164 case PGM_INT_CODE_SECURE_STOR_VIOLATION: 165 /* The interrupt was nullified, the old PSW points at the 166 * responsible instruction. Forward the PSW so we don't loop. 167 */ 168 lowcore.pgm_old_psw.addr += lowcore.pgm_int_id; 169 } 170 /* suppressed/terminated/completed point already at the next address */ 171 } 172 173 static void print_storage_exception_information(void) 174 { 175 switch (lowcore.pgm_int_code) { 176 case PGM_INT_CODE_PROTECTION: 177 case PGM_INT_CODE_PAGE_TRANSLATION: 178 case PGM_INT_CODE_SEGMENT_TRANSLATION: 179 case PGM_INT_CODE_ASCE_TYPE: 180 case PGM_INT_CODE_REGION_FIRST_TRANS: 181 case PGM_INT_CODE_REGION_SECOND_TRANS: 182 case PGM_INT_CODE_REGION_THIRD_TRANS: 183 case PGM_INT_CODE_SECURE_STOR_ACCESS: 184 case PGM_INT_CODE_NON_SECURE_STOR_ACCESS: 185 case PGM_INT_CODE_SECURE_STOR_VIOLATION: 186 print_decode_teid(lowcore.trans_exc_id); 187 break; 188 } 189 } 190 191 static void print_int_regs(struct stack_frame_int *stack) 192 { 193 printf("\n"); 194 printf("GPRS:\n"); 195 printf("%016lx %016lx %016lx %016lx\n", 196 stack->grs1[0], stack->grs1[1], stack->grs0[0], stack->grs0[1]); 197 printf("%016lx %016lx %016lx %016lx\n", 198 stack->grs0[2], stack->grs0[3], stack->grs0[4], stack->grs0[5]); 199 printf("%016lx %016lx %016lx %016lx\n", 200 stack->grs0[6], stack->grs0[7], stack->grs0[8], stack->grs0[9]); 201 printf("%016lx %016lx %016lx %016lx\n", 202 stack->grs0[10], stack->grs0[11], stack->grs0[12], stack->grs0[13]); 203 printf("\n"); 204 } 205 206 static void print_pgm_info(struct stack_frame_int *stack) 207 208 { 209 bool in_sie; 210 211 in_sie = (lowcore.pgm_old_psw.addr >= (uintptr_t)sie_entry && 212 lowcore.pgm_old_psw.addr <= (uintptr_t)sie_exit); 213 214 printf("\n"); 215 printf("Unexpected program interrupt %s: %#x on cpu %d at %#lx, ilen %d\n", 216 in_sie ? "in SIE" : "", 217 lowcore.pgm_int_code, stap(), lowcore.pgm_old_psw.addr, lowcore.pgm_int_id); 218 print_int_regs(stack); 219 dump_stack(); 220 221 /* Dump stack doesn't end with a \n so we add it here instead */ 222 printf("\n"); 223 print_storage_exception_information(); 224 report_summary(); 225 abort(); 226 } 227 228 void handle_pgm_int(struct stack_frame_int *stack) 229 { 230 if (THIS_CPU->in_interrupt_handler) { 231 /* Something went very wrong, stop everything now without printing anything */ 232 smp_teardown(); 233 disabled_wait(0xfa12edbad21); 234 } 235 if (!THIS_CPU->pgm_int_expected) { 236 /* Force sclp_busy to false, otherwise we will loop forever */ 237 sclp_handle_ext(); 238 print_pgm_info(stack); 239 } 240 241 THIS_CPU->pgm_int_expected = false; 242 THIS_CPU->in_interrupt_handler = true; 243 244 if (THIS_CPU->pgm_cleanup_func) 245 THIS_CPU->pgm_cleanup_func(stack); 246 else 247 fixup_pgm_int(stack); 248 THIS_CPU->in_interrupt_handler = false; 249 } 250 251 void handle_ext_int(struct stack_frame_int *stack) 252 { 253 THIS_CPU->in_interrupt_handler = true; 254 if (!THIS_CPU->ext_int_expected && lowcore.ext_int_code != EXT_IRQ_SERVICE_SIG) { 255 report_abort("Unexpected external call interrupt (code %#x): on cpu %d at %#lx", 256 lowcore.ext_int_code, stap(), lowcore.ext_old_psw.addr); 257 return; 258 } 259 260 if (lowcore.ext_int_code == EXT_IRQ_SERVICE_SIG) { 261 stack->crs[0] &= ~(1UL << 9); 262 sclp_handle_ext(); 263 } else { 264 THIS_CPU->ext_int_expected = false; 265 } 266 267 if (!(stack->crs[0] & CR0_EXTM_MASK)) 268 lowcore.ext_old_psw.mask &= ~PSW_MASK_EXT; 269 270 if (THIS_CPU->ext_cleanup_func) 271 THIS_CPU->ext_cleanup_func(stack); 272 THIS_CPU->in_interrupt_handler = false; 273 } 274 275 void handle_mcck_int(void) 276 { 277 report_abort("Unexpected machine check interrupt: on cpu %d at %#lx", 278 stap(), lowcore.mcck_old_psw.addr); 279 } 280 281 static void (*io_int_func)(void); 282 283 void handle_io_int(void) 284 { 285 THIS_CPU->in_interrupt_handler = true; 286 if (io_int_func) 287 io_int_func(); 288 else 289 report_abort("Unexpected io interrupt: on cpu %d at %#lx", 290 stap(), lowcore.io_old_psw.addr); 291 THIS_CPU->in_interrupt_handler = false; 292 } 293 294 int register_io_int_func(void (*f)(void)) 295 { 296 if (io_int_func) 297 return -1; 298 io_int_func = f; 299 return 0; 300 } 301 302 int unregister_io_int_func(void (*f)(void)) 303 { 304 if (io_int_func != f) 305 return -1; 306 io_int_func = NULL; 307 return 0; 308 } 309 310 void handle_svc_int(void) 311 { 312 uint16_t code = lowcore.svc_int_code; 313 314 switch (code) { 315 case SVC_LEAVE_PSTATE: 316 lowcore.svc_old_psw.mask &= ~PSW_MASK_PSTATE; 317 break; 318 default: 319 report_abort("Unexpected supervisor call interrupt: code %#x on cpu %d at %#lx", 320 code, stap(), lowcore.svc_old_psw.addr); 321 } 322 } 323