1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASM_S390X_ARCH_DEF_H_ 9 #define _ASM_S390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 #define PSW_MASK_EXT 0x0100000000000000UL 45 #define PSW_MASK_IO 0x0200000000000000UL 46 #define PSW_MASK_DAT 0x0400000000000000UL 47 #define PSW_MASK_WAIT 0x0002000000000000UL 48 #define PSW_MASK_PSTATE 0x0001000000000000UL 49 50 #define CR0_EXTM_SCLP 0x0000000000000200UL 51 #define CR0_EXTM_EXTC 0x0000000000002000UL 52 #define CR0_EXTM_EMGC 0x0000000000004000UL 53 #define CR0_EXTM_MASK 0x0000000000006200UL 54 55 struct lowcore { 56 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 57 uint32_t ext_int_param; /* 0x0080 */ 58 uint16_t cpu_addr; /* 0x0084 */ 59 uint16_t ext_int_code; /* 0x0086 */ 60 uint16_t svc_int_id; /* 0x0088 */ 61 uint16_t svc_int_code; /* 0x008a */ 62 uint16_t pgm_int_id; /* 0x008c */ 63 uint16_t pgm_int_code; /* 0x008e */ 64 uint32_t dxc_vxc; /* 0x0090 */ 65 uint16_t mon_class_nb; /* 0x0094 */ 66 uint8_t per_code; /* 0x0096 */ 67 uint8_t per_atmid; /* 0x0097 */ 68 uint64_t per_addr; /* 0x0098 */ 69 uint8_t exc_acc_id; /* 0x00a0 */ 70 uint8_t per_acc_id; /* 0x00a1 */ 71 uint8_t op_acc_id; /* 0x00a2 */ 72 uint8_t arch_mode_id; /* 0x00a3 */ 73 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 74 uint64_t trans_exc_id; /* 0x00a8 */ 75 uint64_t mon_code; /* 0x00b0 */ 76 uint32_t subsys_id_word; /* 0x00b8 */ 77 uint32_t io_int_param; /* 0x00bc */ 78 uint32_t io_int_word; /* 0x00c0 */ 79 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 80 uint32_t stfl; /* 0x00c8 */ 81 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 82 uint64_t mcck_int_code; /* 0x00e8 */ 83 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 84 uint32_t ext_damage_code; /* 0x00f4 */ 85 uint64_t failing_storage_addr; /* 0x00f8 */ 86 uint64_t emon_ca_origin; /* 0x0100 */ 87 uint32_t emon_ca_size; /* 0x0108 */ 88 uint32_t emon_exc_count; /* 0x010c */ 89 uint64_t breaking_event_addr; /* 0x0110 */ 90 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 91 struct psw restart_old_psw; /* 0x0120 */ 92 struct psw ext_old_psw; /* 0x0130 */ 93 struct psw svc_old_psw; /* 0x0140 */ 94 struct psw pgm_old_psw; /* 0x0150 */ 95 struct psw mcck_old_psw; /* 0x0160 */ 96 struct psw io_old_psw; /* 0x0170 */ 97 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 98 struct psw restart_new_psw; /* 0x01a0 */ 99 struct psw ext_new_psw; /* 0x01b0 */ 100 struct psw svc_new_psw; /* 0x01c0 */ 101 struct psw pgm_new_psw; /* 0x01d0 */ 102 struct psw mcck_new_psw; /* 0x01e0 */ 103 struct psw io_new_psw; /* 0x01f0 */ 104 /* sw definition: save area for registers in interrupt handlers */ 105 uint64_t sw_int_grs[16]; /* 0x0200 */ 106 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 107 uint64_t sw_int_crs[16]; /* 0x0308 */ 108 struct psw sw_int_psw; /* 0x0388 */ 109 uint8_t pad_0x0310[0x11b0 - 0x0398]; /* 0x0398 */ 110 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 111 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 112 uint64_t fprs_sa[16]; /* 0x1200 */ 113 uint64_t grs_sa[16]; /* 0x1280 */ 114 struct psw psw_sa; /* 0x1300 */ 115 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 116 uint32_t prefix_sa; /* 0x1318 */ 117 uint32_t fpc_sa; /* 0x131c */ 118 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 119 uint32_t tod_pr_sa; /* 0x1324 */ 120 uint64_t cputm_sa; /* 0x1328 */ 121 uint64_t cc_sa; /* 0x1330 */ 122 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 123 uint32_t ars_sa[16]; /* 0x1340 */ 124 uint64_t crs_sa[16]; /* 0x1380 */ 125 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 126 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 127 } __attribute__ ((__packed__)); 128 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 129 130 #define PGM_INT_CODE_OPERATION 0x01 131 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 132 #define PGM_INT_CODE_EXECUTE 0x03 133 #define PGM_INT_CODE_PROTECTION 0x04 134 #define PGM_INT_CODE_ADDRESSING 0x05 135 #define PGM_INT_CODE_SPECIFICATION 0x06 136 #define PGM_INT_CODE_DATA 0x07 137 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 138 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 139 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 140 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 141 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 142 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 143 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 144 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 145 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 146 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 147 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 148 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 149 #define PGM_INT_CODE_OPERAND 0x15 150 #define PGM_INT_CODE_TRACE_TABLE 0x16 151 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 152 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 153 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 154 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 155 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 156 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 157 #define PGM_INT_CODE_LX_TRANSLATION 0x22 158 #define PGM_INT_CODE_EX_TRANSLATION 0x23 159 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 160 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 161 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 162 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 163 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 164 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 165 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 166 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 167 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 168 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 169 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 170 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 171 #define PGM_INT_CODE_STACK_FULL 0x30 172 #define PGM_INT_CODE_STACK_EMPTY 0x31 173 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 174 #define PGM_INT_CODE_STACK_TYPE 0x33 175 #define PGM_INT_CODE_STACK_OPERATION 0x34 176 #define PGM_INT_CODE_ASCE_TYPE 0x38 177 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 178 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 179 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 180 #define PGM_INT_CODE_MONITOR_EVENT 0x40 181 #define PGM_INT_CODE_PER 0x80 182 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 183 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 184 185 struct cpuid { 186 uint64_t version : 8; 187 uint64_t id : 24; 188 uint64_t type : 16; 189 uint64_t format : 1; 190 uint64_t reserved : 15; 191 }; 192 193 #define SVC_LEAVE_PSTATE 1 194 195 static inline unsigned short stap(void) 196 { 197 unsigned short cpu_address; 198 199 asm volatile("stap %0" : "=Q" (cpu_address)); 200 return cpu_address; 201 } 202 203 static inline int tprot(unsigned long addr) 204 { 205 int cc; 206 207 asm volatile( 208 " tprot 0(%1),0\n" 209 " ipm %0\n" 210 " srl %0,28\n" 211 : "=d" (cc) : "a" (addr) : "cc"); 212 return cc; 213 } 214 215 static inline void lctlg(int cr, uint64_t value) 216 { 217 asm volatile( 218 " lctlg %1,%1,%0\n" 219 : : "Q" (value), "i" (cr)); 220 } 221 222 static inline uint64_t stctg(int cr) 223 { 224 uint64_t value; 225 226 asm volatile( 227 " stctg %1,%1,%0\n" 228 : "=Q" (value) : "i" (cr) : "memory"); 229 return value; 230 } 231 232 static inline void ctl_set_bit(int cr, unsigned int bit) 233 { 234 uint64_t reg; 235 236 reg = stctg(cr); 237 reg |= 1UL << bit; 238 lctlg(cr, reg); 239 } 240 241 static inline void ctl_clear_bit(int cr, unsigned int bit) 242 { 243 uint64_t reg; 244 245 reg = stctg(cr); 246 reg &= ~(1UL << bit); 247 lctlg(cr, reg); 248 } 249 250 static inline uint64_t extract_psw_mask(void) 251 { 252 uint32_t mask_upper = 0, mask_lower = 0; 253 254 asm volatile( 255 " epsw %0,%1\n" 256 : "+r" (mask_upper), "+r" (mask_lower) : : ); 257 258 return (uint64_t) mask_upper << 32 | mask_lower; 259 } 260 261 static inline void load_psw_mask(uint64_t mask) 262 { 263 struct psw psw = { 264 .mask = mask, 265 .addr = 0, 266 }; 267 uint64_t tmp = 0; 268 269 asm volatile( 270 " larl %0,0f\n" 271 " stg %0,8(%1)\n" 272 " lpswe 0(%1)\n" 273 "0:\n" 274 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 275 } 276 277 static inline void wait_for_interrupt(uint64_t irq_mask) 278 { 279 uint64_t psw_mask = extract_psw_mask(); 280 281 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 282 /* 283 * After being woken and having processed the interrupt, let's restore 284 * the PSW mask. 285 */ 286 load_psw_mask(psw_mask); 287 } 288 289 static inline void enter_pstate(void) 290 { 291 uint64_t mask; 292 293 mask = extract_psw_mask(); 294 mask |= PSW_MASK_PSTATE; 295 load_psw_mask(mask); 296 } 297 298 static inline void leave_pstate(void) 299 { 300 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 301 } 302 303 static inline int stsi(void *addr, int fc, int sel1, int sel2) 304 { 305 register int r0 asm("0") = (fc << 28) | sel1; 306 register int r1 asm("1") = sel2; 307 int cc; 308 309 asm volatile( 310 "stsi 0(%3)\n" 311 "ipm %[cc]\n" 312 "srl %[cc],28\n" 313 : "+d" (r0), [cc] "=d" (cc) 314 : "d" (r1), "a" (addr) 315 : "cc", "memory"); 316 return cc; 317 } 318 319 static inline int servc(uint32_t command, unsigned long sccb) 320 { 321 int cc; 322 323 asm volatile( 324 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 325 " ipm %0\n" 326 " srl %0,28" 327 : "=&d" (cc) : "d" (command), "a" (sccb) 328 : "cc", "memory"); 329 return cc; 330 } 331 332 static inline void set_prefix(uint32_t new_prefix) 333 { 334 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 335 } 336 337 static inline uint32_t get_prefix(void) 338 { 339 uint32_t current_prefix; 340 341 asm volatile(" stpx %0" : "=Q" (current_prefix)); 342 return current_prefix; 343 } 344 345 #endif 346