1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 struct short_psw { 45 uint32_t mask; 46 uint32_t addr; 47 }; 48 49 struct cpu { 50 struct lowcore *lowcore; 51 uint64_t *stack; 52 void (*pgm_cleanup_func)(struct stack_frame_int *); 53 void (*ext_cleanup_func)(struct stack_frame_int *); 54 uint16_t addr; 55 uint16_t idx; 56 bool active; 57 bool pgm_int_expected; 58 bool ext_int_expected; 59 }; 60 61 #define AS_PRIM 0 62 #define AS_ACCR 1 63 #define AS_SECN 2 64 #define AS_HOME 3 65 66 #define PSW_MASK_DAT 0x0400000000000000UL 67 #define PSW_MASK_IO 0x0200000000000000UL 68 #define PSW_MASK_EXT 0x0100000000000000UL 69 #define PSW_MASK_KEY 0x00F0000000000000UL 70 #define PSW_MASK_WAIT 0x0002000000000000UL 71 #define PSW_MASK_PSTATE 0x0001000000000000UL 72 #define PSW_MASK_EA 0x0000000100000000UL 73 #define PSW_MASK_BA 0x0000000080000000UL 74 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 75 76 #define CTL0_TRANSACT_EX_CTL (63 - 8) 77 #define CTL0_LOW_ADDR_PROT (63 - 35) 78 #define CTL0_EDAT (63 - 40) 79 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 80 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 81 #define CTL0_IEP (63 - 43) 82 #define CTL0_AFP (63 - 45) 83 #define CTL0_VECTOR (63 - 46) 84 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 85 #define CTL0_EXTERNAL_CALL (63 - 50) 86 #define CTL0_CLOCK_COMPARATOR (63 - 52) 87 #define CTL0_CPU_TIMER (63 - 53) 88 #define CTL0_SERVICE_SIGNAL (63 - 54) 89 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 90 91 #define CTL2_GUARDED_STORAGE (63 - 59) 92 93 struct lowcore { 94 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 95 uint32_t ext_int_param; /* 0x0080 */ 96 uint16_t cpu_addr; /* 0x0084 */ 97 uint16_t ext_int_code; /* 0x0086 */ 98 uint16_t svc_int_id; /* 0x0088 */ 99 uint16_t svc_int_code; /* 0x008a */ 100 uint16_t pgm_int_id; /* 0x008c */ 101 uint16_t pgm_int_code; /* 0x008e */ 102 uint32_t dxc_vxc; /* 0x0090 */ 103 uint16_t mon_class_nb; /* 0x0094 */ 104 uint8_t per_code; /* 0x0096 */ 105 uint8_t per_atmid; /* 0x0097 */ 106 uint64_t per_addr; /* 0x0098 */ 107 uint8_t exc_acc_id; /* 0x00a0 */ 108 uint8_t per_acc_id; /* 0x00a1 */ 109 uint8_t op_acc_id; /* 0x00a2 */ 110 uint8_t arch_mode_id; /* 0x00a3 */ 111 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 112 uint64_t trans_exc_id; /* 0x00a8 */ 113 uint64_t mon_code; /* 0x00b0 */ 114 uint32_t subsys_id_word; /* 0x00b8 */ 115 uint32_t io_int_param; /* 0x00bc */ 116 uint32_t io_int_word; /* 0x00c0 */ 117 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 118 uint32_t stfl; /* 0x00c8 */ 119 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 120 uint64_t mcck_int_code; /* 0x00e8 */ 121 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 122 uint32_t ext_damage_code; /* 0x00f4 */ 123 uint64_t failing_storage_addr; /* 0x00f8 */ 124 uint64_t emon_ca_origin; /* 0x0100 */ 125 uint32_t emon_ca_size; /* 0x0108 */ 126 uint32_t emon_exc_count; /* 0x010c */ 127 uint64_t breaking_event_addr; /* 0x0110 */ 128 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 129 struct psw restart_old_psw; /* 0x0120 */ 130 struct psw ext_old_psw; /* 0x0130 */ 131 struct psw svc_old_psw; /* 0x0140 */ 132 struct psw pgm_old_psw; /* 0x0150 */ 133 struct psw mcck_old_psw; /* 0x0160 */ 134 struct psw io_old_psw; /* 0x0170 */ 135 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 136 struct psw restart_new_psw; /* 0x01a0 */ 137 struct psw ext_new_psw; /* 0x01b0 */ 138 struct psw svc_new_psw; /* 0x01c0 */ 139 struct psw pgm_new_psw; /* 0x01d0 */ 140 struct psw mcck_new_psw; /* 0x01e0 */ 141 struct psw io_new_psw; /* 0x01f0 */ 142 /* sw definition: save area for registers in interrupt handlers */ 143 uint64_t sw_int_grs[16]; /* 0x0200 */ 144 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 145 uint64_t sw_int_crs[16]; /* 0x0308 */ 146 struct psw sw_int_psw; /* 0x0388 */ 147 struct cpu *this_cpu; /* 0x0398 */ 148 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 149 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 150 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 151 uint64_t fprs_sa[16]; /* 0x1200 */ 152 uint64_t grs_sa[16]; /* 0x1280 */ 153 struct psw psw_sa; /* 0x1300 */ 154 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 155 uint32_t prefix_sa; /* 0x1318 */ 156 uint32_t fpc_sa; /* 0x131c */ 157 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 158 uint32_t tod_pr_sa; /* 0x1324 */ 159 uint64_t cputm_sa; /* 0x1328 */ 160 uint64_t cc_sa; /* 0x1330 */ 161 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 162 uint32_t ars_sa[16]; /* 0x1340 */ 163 uint64_t crs_sa[16]; /* 0x1380 */ 164 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 165 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 166 } __attribute__ ((__packed__)); 167 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 168 169 extern struct lowcore lowcore; 170 171 #define THIS_CPU (lowcore.this_cpu) 172 173 #define PGM_INT_CODE_OPERATION 0x01 174 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 175 #define PGM_INT_CODE_EXECUTE 0x03 176 #define PGM_INT_CODE_PROTECTION 0x04 177 #define PGM_INT_CODE_ADDRESSING 0x05 178 #define PGM_INT_CODE_SPECIFICATION 0x06 179 #define PGM_INT_CODE_DATA 0x07 180 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 181 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 182 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 183 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 184 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 185 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 186 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 187 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 188 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 189 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 190 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 191 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 192 #define PGM_INT_CODE_OPERAND 0x15 193 #define PGM_INT_CODE_TRACE_TABLE 0x16 194 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 195 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 196 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 197 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 198 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 199 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 200 #define PGM_INT_CODE_LX_TRANSLATION 0x22 201 #define PGM_INT_CODE_EX_TRANSLATION 0x23 202 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 203 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 204 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 205 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 206 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 207 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 208 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 209 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 210 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 211 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 212 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 213 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 214 #define PGM_INT_CODE_STACK_FULL 0x30 215 #define PGM_INT_CODE_STACK_EMPTY 0x31 216 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 217 #define PGM_INT_CODE_STACK_TYPE 0x33 218 #define PGM_INT_CODE_STACK_OPERATION 0x34 219 #define PGM_INT_CODE_ASCE_TYPE 0x38 220 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 221 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 222 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 223 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 224 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 225 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 226 #define PGM_INT_CODE_MONITOR_EVENT 0x40 227 #define PGM_INT_CODE_PER 0x80 228 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 229 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 230 231 struct cpuid { 232 uint64_t version : 8; 233 uint64_t id : 24; 234 uint64_t type : 16; 235 uint64_t format : 1; 236 uint64_t reserved : 15; 237 }; 238 239 #define SVC_LEAVE_PSTATE 1 240 241 static inline unsigned short stap(void) 242 { 243 unsigned short cpu_address; 244 245 asm volatile("stap %0" : "=Q" (cpu_address)); 246 return cpu_address; 247 } 248 249 static inline uint64_t stidp(void) 250 { 251 uint64_t cpuid; 252 253 asm volatile("stidp %0" : "=Q" (cpuid)); 254 255 return cpuid; 256 } 257 258 enum tprot_permission { 259 TPROT_READ_WRITE = 0, 260 TPROT_READ = 1, 261 TPROT_RW_PROTECTED = 2, 262 TPROT_TRANSL_UNAVAIL = 3, 263 }; 264 265 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 266 { 267 int cc; 268 269 asm volatile( 270 " tprot 0(%1),0(%2)\n" 271 " ipm %0\n" 272 " srl %0,28\n" 273 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 274 return (enum tprot_permission)cc; 275 } 276 277 static inline void lctlg(int cr, uint64_t value) 278 { 279 asm volatile( 280 " lctlg %1,%1,%0\n" 281 : : "Q" (value), "i" (cr)); 282 } 283 284 static inline uint64_t stctg(int cr) 285 { 286 uint64_t value; 287 288 asm volatile( 289 " stctg %1,%1,%0\n" 290 : "=Q" (value) : "i" (cr) : "memory"); 291 return value; 292 } 293 294 static inline void ctl_set_bit(int cr, unsigned int bit) 295 { 296 uint64_t reg; 297 298 reg = stctg(cr); 299 reg |= 1UL << bit; 300 lctlg(cr, reg); 301 } 302 303 static inline void ctl_clear_bit(int cr, unsigned int bit) 304 { 305 uint64_t reg; 306 307 reg = stctg(cr); 308 reg &= ~(1UL << bit); 309 lctlg(cr, reg); 310 } 311 312 static inline uint64_t extract_psw_mask(void) 313 { 314 uint32_t mask_upper = 0, mask_lower = 0; 315 316 asm volatile( 317 " epsw %0,%1\n" 318 : "=r" (mask_upper), "=a" (mask_lower)); 319 320 return (uint64_t) mask_upper << 32 | mask_lower; 321 } 322 323 static inline void load_psw_mask(uint64_t mask) 324 { 325 struct psw psw = { 326 .mask = mask, 327 .addr = 0, 328 }; 329 uint64_t tmp = 0; 330 331 asm volatile( 332 " larl %0,0f\n" 333 " stg %0,8(%1)\n" 334 " lpswe 0(%1)\n" 335 "0:\n" 336 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 337 } 338 339 /** 340 * psw_mask_clear_bits - clears bits from the current PSW mask 341 * @clear: bitmask of bits that will be cleared 342 */ 343 static inline void psw_mask_clear_bits(uint64_t clear) 344 { 345 load_psw_mask(extract_psw_mask() & ~clear); 346 } 347 348 /** 349 * psw_mask_set_bits - sets bits on the current PSW mask 350 * @set: bitmask of bits that will be set 351 */ 352 static inline void psw_mask_set_bits(uint64_t set) 353 { 354 load_psw_mask(extract_psw_mask() | set); 355 } 356 357 /** 358 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 359 * @clear: bitmask of bits that will be cleared 360 * @set: bitmask of bits that will be set 361 * 362 * The bits in the @clear mask will be cleared, then the bits in the @set mask 363 * will be set. 364 */ 365 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 366 { 367 load_psw_mask((extract_psw_mask() & ~clear) | set); 368 } 369 370 /** 371 * enable_dat - enable the DAT bit in the current PSW 372 */ 373 static inline void enable_dat(void) 374 { 375 psw_mask_set_bits(PSW_MASK_DAT); 376 } 377 378 /** 379 * disable_dat - disable the DAT bit in the current PSW 380 */ 381 static inline void disable_dat(void) 382 { 383 psw_mask_clear_bits(PSW_MASK_DAT); 384 } 385 386 static inline void wait_for_interrupt(uint64_t irq_mask) 387 { 388 uint64_t psw_mask = extract_psw_mask(); 389 390 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 391 /* 392 * After being woken and having processed the interrupt, let's restore 393 * the PSW mask. 394 */ 395 load_psw_mask(psw_mask); 396 } 397 398 static inline void enter_pstate(void) 399 { 400 psw_mask_set_bits(PSW_MASK_PSTATE); 401 } 402 403 static inline void leave_pstate(void) 404 { 405 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 406 } 407 408 static inline int stsi(void *addr, int fc, int sel1, int sel2) 409 { 410 register int r0 asm("0") = (fc << 28) | sel1; 411 register int r1 asm("1") = sel2; 412 int cc; 413 414 asm volatile( 415 "stsi 0(%3)\n" 416 "ipm %[cc]\n" 417 "srl %[cc],28\n" 418 : "+d" (r0), [cc] "=d" (cc) 419 : "d" (r1), "a" (addr) 420 : "cc", "memory"); 421 return cc; 422 } 423 424 static inline unsigned long stsi_get_fc(void) 425 { 426 register unsigned long r0 asm("0") = 0; 427 register unsigned long r1 asm("1") = 0; 428 int cc; 429 430 asm volatile("stsi 0\n" 431 "ipm %[cc]\n" 432 "srl %[cc],28\n" 433 : "+d" (r0), [cc] "=d" (cc) 434 : "d" (r1) 435 : "cc", "memory"); 436 assert(!cc); 437 return r0 >> 28; 438 } 439 440 static inline int servc(uint32_t command, unsigned long sccb) 441 { 442 int cc; 443 444 asm volatile( 445 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 446 " ipm %0\n" 447 " srl %0,28" 448 : "=&d" (cc) : "d" (command), "a" (sccb) 449 : "cc", "memory"); 450 return cc; 451 } 452 453 static inline void set_prefix(uint32_t new_prefix) 454 { 455 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 456 } 457 458 static inline uint32_t get_prefix(void) 459 { 460 uint32_t current_prefix; 461 462 asm volatile(" stpx %0" : "=Q" (current_prefix)); 463 return current_prefix; 464 } 465 466 #endif 467