1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 union { 41 uint64_t mask; 42 struct { 43 uint64_t reserved00:1; 44 uint64_t per:1; 45 uint64_t reserved02:3; 46 uint64_t dat:1; 47 uint64_t io:1; 48 uint64_t ext:1; 49 uint64_t key:4; 50 uint64_t reserved12:1; 51 uint64_t mchk:1; 52 uint64_t wait:1; 53 uint64_t pstate:1; 54 uint64_t as:2; 55 uint64_t cc:2; 56 uint64_t prg_mask:4; 57 uint64_t reserved24:7; 58 uint64_t ea:1; 59 uint64_t ba:1; 60 uint64_t reserved33:31; 61 }; 62 }; 63 uint64_t addr; 64 }; 65 _Static_assert(sizeof(struct psw) == 16, "PSW size"); 66 67 #define PSW(m, a) ((struct psw){ .mask = (m), .addr = (uint64_t)(a) }) 68 69 struct short_psw { 70 uint32_t mask; 71 uint32_t addr; 72 }; 73 74 struct cpu { 75 struct lowcore *lowcore; 76 uint64_t *stack; 77 void (*pgm_cleanup_func)(struct stack_frame_int *); 78 void (*ext_cleanup_func)(struct stack_frame_int *); 79 uint16_t addr; 80 uint16_t idx; 81 bool active; 82 bool pgm_int_expected; 83 bool ext_int_expected; 84 bool in_interrupt_handler; 85 }; 86 87 #define AS_PRIM 0 88 #define AS_ACCR 1 89 #define AS_SECN 2 90 #define AS_HOME 3 91 92 #define PSW_MASK_DAT 0x0400000000000000UL 93 #define PSW_MASK_IO 0x0200000000000000UL 94 #define PSW_MASK_EXT 0x0100000000000000UL 95 #define PSW_MASK_KEY 0x00F0000000000000UL 96 #define PSW_MASK_WAIT 0x0002000000000000UL 97 #define PSW_MASK_PSTATE 0x0001000000000000UL 98 #define PSW_MASK_EA 0x0000000100000000UL 99 #define PSW_MASK_BA 0x0000000080000000UL 100 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 101 102 #define CTL0_TRANSACT_EX_CTL (63 - 8) 103 #define CTL0_LOW_ADDR_PROT (63 - 35) 104 #define CTL0_EDAT (63 - 40) 105 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 106 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 107 #define CTL0_IEP (63 - 43) 108 #define CTL0_AFP (63 - 45) 109 #define CTL0_VECTOR (63 - 46) 110 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 111 #define CTL0_EXTERNAL_CALL (63 - 50) 112 #define CTL0_CLOCK_COMPARATOR (63 - 52) 113 #define CTL0_CPU_TIMER (63 - 53) 114 #define CTL0_SERVICE_SIGNAL (63 - 54) 115 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 116 117 #define CTL2_GUARDED_STORAGE (63 - 59) 118 119 struct lowcore { 120 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 121 uint32_t ext_int_param; /* 0x0080 */ 122 uint16_t cpu_addr; /* 0x0084 */ 123 uint16_t ext_int_code; /* 0x0086 */ 124 uint16_t svc_int_id; /* 0x0088 */ 125 uint16_t svc_int_code; /* 0x008a */ 126 uint16_t pgm_int_id; /* 0x008c */ 127 uint16_t pgm_int_code; /* 0x008e */ 128 uint32_t dxc_vxc; /* 0x0090 */ 129 uint16_t mon_class_nb; /* 0x0094 */ 130 uint8_t per_code; /* 0x0096 */ 131 uint8_t per_atmid; /* 0x0097 */ 132 uint64_t per_addr; /* 0x0098 */ 133 uint8_t exc_acc_id; /* 0x00a0 */ 134 uint8_t per_acc_id; /* 0x00a1 */ 135 uint8_t op_acc_id; /* 0x00a2 */ 136 uint8_t arch_mode_id; /* 0x00a3 */ 137 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 138 uint64_t trans_exc_id; /* 0x00a8 */ 139 uint64_t mon_code; /* 0x00b0 */ 140 uint32_t subsys_id_word; /* 0x00b8 */ 141 uint32_t io_int_param; /* 0x00bc */ 142 uint32_t io_int_word; /* 0x00c0 */ 143 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 144 uint32_t stfl; /* 0x00c8 */ 145 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 146 uint64_t mcck_int_code; /* 0x00e8 */ 147 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 148 uint32_t ext_damage_code; /* 0x00f4 */ 149 uint64_t failing_storage_addr; /* 0x00f8 */ 150 uint64_t emon_ca_origin; /* 0x0100 */ 151 uint32_t emon_ca_size; /* 0x0108 */ 152 uint32_t emon_exc_count; /* 0x010c */ 153 uint64_t breaking_event_addr; /* 0x0110 */ 154 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 155 struct psw restart_old_psw; /* 0x0120 */ 156 struct psw ext_old_psw; /* 0x0130 */ 157 struct psw svc_old_psw; /* 0x0140 */ 158 struct psw pgm_old_psw; /* 0x0150 */ 159 struct psw mcck_old_psw; /* 0x0160 */ 160 struct psw io_old_psw; /* 0x0170 */ 161 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 162 struct psw restart_new_psw; /* 0x01a0 */ 163 struct psw ext_new_psw; /* 0x01b0 */ 164 struct psw svc_new_psw; /* 0x01c0 */ 165 struct psw pgm_new_psw; /* 0x01d0 */ 166 struct psw mcck_new_psw; /* 0x01e0 */ 167 struct psw io_new_psw; /* 0x01f0 */ 168 /* sw definition: save area for registers in interrupt handlers */ 169 uint64_t sw_int_grs[16]; /* 0x0200 */ 170 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 171 uint64_t sw_int_crs[16]; /* 0x0308 */ 172 struct psw sw_int_psw; /* 0x0388 */ 173 struct cpu *this_cpu; /* 0x0398 */ 174 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 175 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 176 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 177 uint64_t fprs_sa[16]; /* 0x1200 */ 178 uint64_t grs_sa[16]; /* 0x1280 */ 179 struct psw psw_sa; /* 0x1300 */ 180 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 181 uint32_t prefix_sa; /* 0x1318 */ 182 uint32_t fpc_sa; /* 0x131c */ 183 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 184 uint32_t tod_pr_sa; /* 0x1324 */ 185 uint64_t cputm_sa; /* 0x1328 */ 186 uint64_t cc_sa; /* 0x1330 */ 187 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 188 uint32_t ars_sa[16]; /* 0x1340 */ 189 uint64_t crs_sa[16]; /* 0x1380 */ 190 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 191 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 192 } __attribute__ ((__packed__)); 193 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 194 195 extern struct lowcore lowcore; 196 197 #define THIS_CPU (lowcore.this_cpu) 198 199 #define PGM_INT_CODE_OPERATION 0x01 200 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 201 #define PGM_INT_CODE_EXECUTE 0x03 202 #define PGM_INT_CODE_PROTECTION 0x04 203 #define PGM_INT_CODE_ADDRESSING 0x05 204 #define PGM_INT_CODE_SPECIFICATION 0x06 205 #define PGM_INT_CODE_DATA 0x07 206 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 207 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 208 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 209 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 210 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 211 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 212 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 213 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 214 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 215 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 216 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 217 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 218 #define PGM_INT_CODE_OPERAND 0x15 219 #define PGM_INT_CODE_TRACE_TABLE 0x16 220 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 221 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 222 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 223 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 224 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 225 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 226 #define PGM_INT_CODE_LX_TRANSLATION 0x22 227 #define PGM_INT_CODE_EX_TRANSLATION 0x23 228 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 229 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 230 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 231 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 232 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 233 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 234 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 235 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 236 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 237 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 238 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 239 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 240 #define PGM_INT_CODE_STACK_FULL 0x30 241 #define PGM_INT_CODE_STACK_EMPTY 0x31 242 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 243 #define PGM_INT_CODE_STACK_TYPE 0x33 244 #define PGM_INT_CODE_STACK_OPERATION 0x34 245 #define PGM_INT_CODE_ASCE_TYPE 0x38 246 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 247 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 248 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 249 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 250 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 251 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 252 #define PGM_INT_CODE_MONITOR_EVENT 0x40 253 #define PGM_INT_CODE_PER 0x80 254 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 255 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 256 257 struct cpuid { 258 uint64_t version : 8; 259 uint64_t id : 24; 260 uint64_t type : 16; 261 uint64_t format : 1; 262 uint64_t reserved : 15; 263 }; 264 265 #define SVC_LEAVE_PSTATE 1 266 267 static inline unsigned short stap(void) 268 { 269 unsigned short cpu_address; 270 271 asm volatile("stap %0" : "=Q" (cpu_address)); 272 return cpu_address; 273 } 274 275 static inline uint64_t stidp(void) 276 { 277 uint64_t cpuid; 278 279 asm volatile("stidp %0" : "=Q" (cpuid)); 280 281 return cpuid; 282 } 283 284 enum tprot_permission { 285 TPROT_READ_WRITE = 0, 286 TPROT_READ = 1, 287 TPROT_RW_PROTECTED = 2, 288 TPROT_TRANSL_UNAVAIL = 3, 289 }; 290 291 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 292 { 293 int cc; 294 295 asm volatile( 296 " tprot 0(%1),0(%2)\n" 297 " ipm %0\n" 298 " srl %0,28\n" 299 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 300 return (enum tprot_permission)cc; 301 } 302 303 static inline void lctlg(int cr, uint64_t value) 304 { 305 asm volatile( 306 " lctlg %1,%1,%0\n" 307 : : "Q" (value), "i" (cr)); 308 } 309 310 static inline uint64_t stctg(int cr) 311 { 312 uint64_t value; 313 314 asm volatile( 315 " stctg %1,%1,%0\n" 316 : "=Q" (value) : "i" (cr) : "memory"); 317 return value; 318 } 319 320 static inline void ctl_set_bit(int cr, unsigned int bit) 321 { 322 uint64_t reg; 323 324 reg = stctg(cr); 325 reg |= 1UL << bit; 326 lctlg(cr, reg); 327 } 328 329 static inline void ctl_clear_bit(int cr, unsigned int bit) 330 { 331 uint64_t reg; 332 333 reg = stctg(cr); 334 reg &= ~(1UL << bit); 335 lctlg(cr, reg); 336 } 337 338 static inline uint64_t extract_psw_mask(void) 339 { 340 uint32_t mask_upper = 0, mask_lower = 0; 341 342 asm volatile( 343 " epsw %0,%1\n" 344 : "=r" (mask_upper), "=a" (mask_lower)); 345 346 return (uint64_t) mask_upper << 32 | mask_lower; 347 } 348 349 #define PSW_WITH_CUR_MASK(addr) PSW(extract_psw_mask(), (addr)) 350 351 static inline void load_psw_mask(uint64_t mask) 352 { 353 struct psw psw = { 354 .mask = mask, 355 .addr = 0, 356 }; 357 uint64_t tmp = 0; 358 359 asm volatile( 360 " larl %0,0f\n" 361 " stg %0,8(%1)\n" 362 " lpswe 0(%1)\n" 363 "0:\n" 364 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 365 } 366 367 static inline void disabled_wait(uint64_t message) 368 { 369 struct psw psw = { 370 .mask = PSW_MASK_WAIT, /* Disabled wait */ 371 .addr = message, 372 }; 373 374 asm volatile(" lpswe 0(%0)\n" : : "a" (&psw) : "memory", "cc"); 375 } 376 377 /** 378 * psw_mask_clear_bits - clears bits from the current PSW mask 379 * @clear: bitmask of bits that will be cleared 380 */ 381 static inline void psw_mask_clear_bits(uint64_t clear) 382 { 383 load_psw_mask(extract_psw_mask() & ~clear); 384 } 385 386 /** 387 * psw_mask_set_bits - sets bits on the current PSW mask 388 * @set: bitmask of bits that will be set 389 */ 390 static inline void psw_mask_set_bits(uint64_t set) 391 { 392 load_psw_mask(extract_psw_mask() | set); 393 } 394 395 /** 396 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 397 * @clear: bitmask of bits that will be cleared 398 * @set: bitmask of bits that will be set 399 * 400 * The bits in the @clear mask will be cleared, then the bits in the @set mask 401 * will be set. 402 */ 403 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 404 { 405 load_psw_mask((extract_psw_mask() & ~clear) | set); 406 } 407 408 /** 409 * enable_dat - enable the DAT bit in the current PSW 410 */ 411 static inline void enable_dat(void) 412 { 413 psw_mask_set_bits(PSW_MASK_DAT); 414 } 415 416 /** 417 * disable_dat - disable the DAT bit in the current PSW 418 */ 419 static inline void disable_dat(void) 420 { 421 psw_mask_clear_bits(PSW_MASK_DAT); 422 } 423 424 static inline void wait_for_interrupt(uint64_t irq_mask) 425 { 426 uint64_t psw_mask = extract_psw_mask(); 427 428 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 429 /* 430 * After being woken and having processed the interrupt, let's restore 431 * the PSW mask. 432 */ 433 load_psw_mask(psw_mask); 434 } 435 436 static inline void enter_pstate(void) 437 { 438 psw_mask_set_bits(PSW_MASK_PSTATE); 439 } 440 441 static inline void leave_pstate(void) 442 { 443 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 444 } 445 446 static inline int stsi(void *addr, int fc, int sel1, int sel2) 447 { 448 register int r0 asm("0") = (fc << 28) | sel1; 449 register int r1 asm("1") = sel2; 450 int cc; 451 452 asm volatile( 453 "stsi 0(%3)\n" 454 "ipm %[cc]\n" 455 "srl %[cc],28\n" 456 : "+d" (r0), [cc] "=d" (cc) 457 : "d" (r1), "a" (addr) 458 : "cc", "memory"); 459 return cc; 460 } 461 462 static inline unsigned long stsi_get_fc(void) 463 { 464 register unsigned long r0 asm("0") = 0; 465 register unsigned long r1 asm("1") = 0; 466 int cc; 467 468 asm volatile("stsi 0\n" 469 "ipm %[cc]\n" 470 "srl %[cc],28\n" 471 : "+d" (r0), [cc] "=d" (cc) 472 : "d" (r1) 473 : "cc", "memory"); 474 assert(!cc); 475 return r0 >> 28; 476 } 477 478 static inline int servc(uint32_t command, unsigned long sccb) 479 { 480 int cc; 481 482 asm volatile( 483 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 484 " ipm %0\n" 485 " srl %0,28" 486 : "=&d" (cc) : "d" (command), "a" (sccb) 487 : "cc", "memory"); 488 return cc; 489 } 490 491 static inline void set_prefix(uint32_t new_prefix) 492 { 493 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 494 } 495 496 static inline uint32_t get_prefix(void) 497 { 498 uint32_t current_prefix; 499 500 asm volatile(" stpx %0" : "=Q" (current_prefix)); 501 return current_prefix; 502 } 503 504 #endif 505