1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 struct short_psw { 45 uint32_t mask; 46 uint32_t addr; 47 }; 48 49 struct cpu { 50 struct lowcore *lowcore; 51 uint64_t *stack; 52 void (*pgm_cleanup_func)(struct stack_frame_int *); 53 void (*ext_cleanup_func)(struct stack_frame_int *); 54 uint16_t addr; 55 uint16_t idx; 56 bool active; 57 bool pgm_int_expected; 58 bool ext_int_expected; 59 }; 60 61 #define AS_PRIM 0 62 #define AS_ACCR 1 63 #define AS_SECN 2 64 #define AS_HOME 3 65 66 #define PSW_MASK_DAT 0x0400000000000000UL 67 #define PSW_MASK_IO 0x0200000000000000UL 68 #define PSW_MASK_EXT 0x0100000000000000UL 69 #define PSW_MASK_KEY 0x00F0000000000000UL 70 #define PSW_MASK_WAIT 0x0002000000000000UL 71 #define PSW_MASK_PSTATE 0x0001000000000000UL 72 #define PSW_MASK_EA 0x0000000100000000UL 73 #define PSW_MASK_BA 0x0000000080000000UL 74 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 75 76 #define CTL0_LOW_ADDR_PROT (63 - 35) 77 #define CTL0_EDAT (63 - 40) 78 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 79 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 80 #define CTL0_IEP (63 - 43) 81 #define CTL0_AFP (63 - 45) 82 #define CTL0_VECTOR (63 - 46) 83 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 84 #define CTL0_EXTERNAL_CALL (63 - 50) 85 #define CTL0_CLOCK_COMPARATOR (63 - 52) 86 #define CTL0_CPU_TIMER (63 - 53) 87 #define CTL0_SERVICE_SIGNAL (63 - 54) 88 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 89 90 #define CTL2_GUARDED_STORAGE (63 - 59) 91 92 struct lowcore { 93 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 94 uint32_t ext_int_param; /* 0x0080 */ 95 uint16_t cpu_addr; /* 0x0084 */ 96 uint16_t ext_int_code; /* 0x0086 */ 97 uint16_t svc_int_id; /* 0x0088 */ 98 uint16_t svc_int_code; /* 0x008a */ 99 uint16_t pgm_int_id; /* 0x008c */ 100 uint16_t pgm_int_code; /* 0x008e */ 101 uint32_t dxc_vxc; /* 0x0090 */ 102 uint16_t mon_class_nb; /* 0x0094 */ 103 uint8_t per_code; /* 0x0096 */ 104 uint8_t per_atmid; /* 0x0097 */ 105 uint64_t per_addr; /* 0x0098 */ 106 uint8_t exc_acc_id; /* 0x00a0 */ 107 uint8_t per_acc_id; /* 0x00a1 */ 108 uint8_t op_acc_id; /* 0x00a2 */ 109 uint8_t arch_mode_id; /* 0x00a3 */ 110 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 111 uint64_t trans_exc_id; /* 0x00a8 */ 112 uint64_t mon_code; /* 0x00b0 */ 113 uint32_t subsys_id_word; /* 0x00b8 */ 114 uint32_t io_int_param; /* 0x00bc */ 115 uint32_t io_int_word; /* 0x00c0 */ 116 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 117 uint32_t stfl; /* 0x00c8 */ 118 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 119 uint64_t mcck_int_code; /* 0x00e8 */ 120 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 121 uint32_t ext_damage_code; /* 0x00f4 */ 122 uint64_t failing_storage_addr; /* 0x00f8 */ 123 uint64_t emon_ca_origin; /* 0x0100 */ 124 uint32_t emon_ca_size; /* 0x0108 */ 125 uint32_t emon_exc_count; /* 0x010c */ 126 uint64_t breaking_event_addr; /* 0x0110 */ 127 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 128 struct psw restart_old_psw; /* 0x0120 */ 129 struct psw ext_old_psw; /* 0x0130 */ 130 struct psw svc_old_psw; /* 0x0140 */ 131 struct psw pgm_old_psw; /* 0x0150 */ 132 struct psw mcck_old_psw; /* 0x0160 */ 133 struct psw io_old_psw; /* 0x0170 */ 134 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 135 struct psw restart_new_psw; /* 0x01a0 */ 136 struct psw ext_new_psw; /* 0x01b0 */ 137 struct psw svc_new_psw; /* 0x01c0 */ 138 struct psw pgm_new_psw; /* 0x01d0 */ 139 struct psw mcck_new_psw; /* 0x01e0 */ 140 struct psw io_new_psw; /* 0x01f0 */ 141 /* sw definition: save area for registers in interrupt handlers */ 142 uint64_t sw_int_grs[16]; /* 0x0200 */ 143 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 144 uint64_t sw_int_crs[16]; /* 0x0308 */ 145 struct psw sw_int_psw; /* 0x0388 */ 146 struct cpu *this_cpu; /* 0x0398 */ 147 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 148 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 149 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 150 uint64_t fprs_sa[16]; /* 0x1200 */ 151 uint64_t grs_sa[16]; /* 0x1280 */ 152 struct psw psw_sa; /* 0x1300 */ 153 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 154 uint32_t prefix_sa; /* 0x1318 */ 155 uint32_t fpc_sa; /* 0x131c */ 156 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 157 uint32_t tod_pr_sa; /* 0x1324 */ 158 uint64_t cputm_sa; /* 0x1328 */ 159 uint64_t cc_sa; /* 0x1330 */ 160 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 161 uint32_t ars_sa[16]; /* 0x1340 */ 162 uint64_t crs_sa[16]; /* 0x1380 */ 163 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 164 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 165 } __attribute__ ((__packed__)); 166 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 167 168 extern struct lowcore lowcore; 169 170 #define THIS_CPU (lowcore.this_cpu) 171 172 #define PGM_INT_CODE_OPERATION 0x01 173 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 174 #define PGM_INT_CODE_EXECUTE 0x03 175 #define PGM_INT_CODE_PROTECTION 0x04 176 #define PGM_INT_CODE_ADDRESSING 0x05 177 #define PGM_INT_CODE_SPECIFICATION 0x06 178 #define PGM_INT_CODE_DATA 0x07 179 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 180 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 181 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 182 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 183 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 184 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 185 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 186 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 187 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 188 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 189 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 190 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 191 #define PGM_INT_CODE_OPERAND 0x15 192 #define PGM_INT_CODE_TRACE_TABLE 0x16 193 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 194 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 195 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 196 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 197 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 198 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 199 #define PGM_INT_CODE_LX_TRANSLATION 0x22 200 #define PGM_INT_CODE_EX_TRANSLATION 0x23 201 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 202 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 203 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 204 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 205 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 206 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 207 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 208 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 209 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 210 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 211 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 212 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 213 #define PGM_INT_CODE_STACK_FULL 0x30 214 #define PGM_INT_CODE_STACK_EMPTY 0x31 215 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 216 #define PGM_INT_CODE_STACK_TYPE 0x33 217 #define PGM_INT_CODE_STACK_OPERATION 0x34 218 #define PGM_INT_CODE_ASCE_TYPE 0x38 219 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 220 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 221 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 222 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 223 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 224 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 225 #define PGM_INT_CODE_MONITOR_EVENT 0x40 226 #define PGM_INT_CODE_PER 0x80 227 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 228 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 229 230 struct cpuid { 231 uint64_t version : 8; 232 uint64_t id : 24; 233 uint64_t type : 16; 234 uint64_t format : 1; 235 uint64_t reserved : 15; 236 }; 237 238 #define SVC_LEAVE_PSTATE 1 239 240 static inline unsigned short stap(void) 241 { 242 unsigned short cpu_address; 243 244 asm volatile("stap %0" : "=Q" (cpu_address)); 245 return cpu_address; 246 } 247 248 static inline uint64_t stidp(void) 249 { 250 uint64_t cpuid; 251 252 asm volatile("stidp %0" : "=Q" (cpuid)); 253 254 return cpuid; 255 } 256 257 enum tprot_permission { 258 TPROT_READ_WRITE = 0, 259 TPROT_READ = 1, 260 TPROT_RW_PROTECTED = 2, 261 TPROT_TRANSL_UNAVAIL = 3, 262 }; 263 264 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 265 { 266 int cc; 267 268 asm volatile( 269 " tprot 0(%1),0(%2)\n" 270 " ipm %0\n" 271 " srl %0,28\n" 272 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 273 return (enum tprot_permission)cc; 274 } 275 276 static inline void lctlg(int cr, uint64_t value) 277 { 278 asm volatile( 279 " lctlg %1,%1,%0\n" 280 : : "Q" (value), "i" (cr)); 281 } 282 283 static inline uint64_t stctg(int cr) 284 { 285 uint64_t value; 286 287 asm volatile( 288 " stctg %1,%1,%0\n" 289 : "=Q" (value) : "i" (cr) : "memory"); 290 return value; 291 } 292 293 static inline void ctl_set_bit(int cr, unsigned int bit) 294 { 295 uint64_t reg; 296 297 reg = stctg(cr); 298 reg |= 1UL << bit; 299 lctlg(cr, reg); 300 } 301 302 static inline void ctl_clear_bit(int cr, unsigned int bit) 303 { 304 uint64_t reg; 305 306 reg = stctg(cr); 307 reg &= ~(1UL << bit); 308 lctlg(cr, reg); 309 } 310 311 static inline uint64_t extract_psw_mask(void) 312 { 313 uint32_t mask_upper = 0, mask_lower = 0; 314 315 asm volatile( 316 " epsw %0,%1\n" 317 : "=r" (mask_upper), "=a" (mask_lower)); 318 319 return (uint64_t) mask_upper << 32 | mask_lower; 320 } 321 322 static inline void load_psw_mask(uint64_t mask) 323 { 324 struct psw psw = { 325 .mask = mask, 326 .addr = 0, 327 }; 328 uint64_t tmp = 0; 329 330 asm volatile( 331 " larl %0,0f\n" 332 " stg %0,8(%1)\n" 333 " lpswe 0(%1)\n" 334 "0:\n" 335 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 336 } 337 338 /** 339 * psw_mask_clear_bits - clears bits from the current PSW mask 340 * @clear: bitmask of bits that will be cleared 341 */ 342 static inline void psw_mask_clear_bits(uint64_t clear) 343 { 344 load_psw_mask(extract_psw_mask() & ~clear); 345 } 346 347 /** 348 * psw_mask_set_bits - sets bits on the current PSW mask 349 * @set: bitmask of bits that will be set 350 */ 351 static inline void psw_mask_set_bits(uint64_t set) 352 { 353 load_psw_mask(extract_psw_mask() | set); 354 } 355 356 /** 357 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 358 * @clear: bitmask of bits that will be cleared 359 * @set: bitmask of bits that will be set 360 * 361 * The bits in the @clear mask will be cleared, then the bits in the @set mask 362 * will be set. 363 */ 364 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 365 { 366 load_psw_mask((extract_psw_mask() & ~clear) | set); 367 } 368 369 /** 370 * enable_dat - enable the DAT bit in the current PSW 371 */ 372 static inline void enable_dat(void) 373 { 374 psw_mask_set_bits(PSW_MASK_DAT); 375 } 376 377 /** 378 * disable_dat - disable the DAT bit in the current PSW 379 */ 380 static inline void disable_dat(void) 381 { 382 psw_mask_clear_bits(PSW_MASK_DAT); 383 } 384 385 static inline void wait_for_interrupt(uint64_t irq_mask) 386 { 387 uint64_t psw_mask = extract_psw_mask(); 388 389 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 390 /* 391 * After being woken and having processed the interrupt, let's restore 392 * the PSW mask. 393 */ 394 load_psw_mask(psw_mask); 395 } 396 397 static inline void enter_pstate(void) 398 { 399 psw_mask_set_bits(PSW_MASK_PSTATE); 400 } 401 402 static inline void leave_pstate(void) 403 { 404 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 405 } 406 407 static inline int stsi(void *addr, int fc, int sel1, int sel2) 408 { 409 register int r0 asm("0") = (fc << 28) | sel1; 410 register int r1 asm("1") = sel2; 411 int cc; 412 413 asm volatile( 414 "stsi 0(%3)\n" 415 "ipm %[cc]\n" 416 "srl %[cc],28\n" 417 : "+d" (r0), [cc] "=d" (cc) 418 : "d" (r1), "a" (addr) 419 : "cc", "memory"); 420 return cc; 421 } 422 423 static inline unsigned long stsi_get_fc(void) 424 { 425 register unsigned long r0 asm("0") = 0; 426 register unsigned long r1 asm("1") = 0; 427 int cc; 428 429 asm volatile("stsi 0\n" 430 "ipm %[cc]\n" 431 "srl %[cc],28\n" 432 : "+d" (r0), [cc] "=d" (cc) 433 : "d" (r1) 434 : "cc", "memory"); 435 assert(!cc); 436 return r0 >> 28; 437 } 438 439 static inline int servc(uint32_t command, unsigned long sccb) 440 { 441 int cc; 442 443 asm volatile( 444 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 445 " ipm %0\n" 446 " srl %0,28" 447 : "=&d" (cc) : "d" (command), "a" (sccb) 448 : "cc", "memory"); 449 return cc; 450 } 451 452 static inline void set_prefix(uint32_t new_prefix) 453 { 454 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 455 } 456 457 static inline uint32_t get_prefix(void) 458 { 459 uint32_t current_prefix; 460 461 asm volatile(" stpx %0" : "=Q" (current_prefix)); 462 return current_prefix; 463 } 464 465 #endif 466