1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 #define AS_PRIM 0 45 #define AS_ACCR 1 46 #define AS_SECN 2 47 #define AS_HOME 3 48 49 #define PSW_MASK_EXT 0x0100000000000000UL 50 #define PSW_MASK_IO 0x0200000000000000UL 51 #define PSW_MASK_DAT 0x0400000000000000UL 52 #define PSW_MASK_WAIT 0x0002000000000000UL 53 #define PSW_MASK_PSTATE 0x0001000000000000UL 54 #define PSW_MASK_EA 0x0000000100000000UL 55 #define PSW_MASK_BA 0x0000000080000000UL 56 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 57 58 #define CTL0_LOW_ADDR_PROT (63 - 35) 59 #define CTL0_EDAT (63 - 40) 60 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 61 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 62 #define CTL0_IEP (63 - 43) 63 #define CTL0_AFP (63 - 45) 64 #define CTL0_VECTOR (63 - 46) 65 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 66 #define CTL0_EXTERNAL_CALL (63 - 50) 67 #define CTL0_CLOCK_COMPARATOR (63 - 52) 68 #define CTL0_SERVICE_SIGNAL (63 - 54) 69 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 70 71 #define CTL2_GUARDED_STORAGE (63 - 59) 72 73 struct lowcore { 74 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 75 uint32_t ext_int_param; /* 0x0080 */ 76 uint16_t cpu_addr; /* 0x0084 */ 77 uint16_t ext_int_code; /* 0x0086 */ 78 uint16_t svc_int_id; /* 0x0088 */ 79 uint16_t svc_int_code; /* 0x008a */ 80 uint16_t pgm_int_id; /* 0x008c */ 81 uint16_t pgm_int_code; /* 0x008e */ 82 uint32_t dxc_vxc; /* 0x0090 */ 83 uint16_t mon_class_nb; /* 0x0094 */ 84 uint8_t per_code; /* 0x0096 */ 85 uint8_t per_atmid; /* 0x0097 */ 86 uint64_t per_addr; /* 0x0098 */ 87 uint8_t exc_acc_id; /* 0x00a0 */ 88 uint8_t per_acc_id; /* 0x00a1 */ 89 uint8_t op_acc_id; /* 0x00a2 */ 90 uint8_t arch_mode_id; /* 0x00a3 */ 91 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 92 uint64_t trans_exc_id; /* 0x00a8 */ 93 uint64_t mon_code; /* 0x00b0 */ 94 uint32_t subsys_id_word; /* 0x00b8 */ 95 uint32_t io_int_param; /* 0x00bc */ 96 uint32_t io_int_word; /* 0x00c0 */ 97 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 98 uint32_t stfl; /* 0x00c8 */ 99 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 100 uint64_t mcck_int_code; /* 0x00e8 */ 101 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 102 uint32_t ext_damage_code; /* 0x00f4 */ 103 uint64_t failing_storage_addr; /* 0x00f8 */ 104 uint64_t emon_ca_origin; /* 0x0100 */ 105 uint32_t emon_ca_size; /* 0x0108 */ 106 uint32_t emon_exc_count; /* 0x010c */ 107 uint64_t breaking_event_addr; /* 0x0110 */ 108 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 109 struct psw restart_old_psw; /* 0x0120 */ 110 struct psw ext_old_psw; /* 0x0130 */ 111 struct psw svc_old_psw; /* 0x0140 */ 112 struct psw pgm_old_psw; /* 0x0150 */ 113 struct psw mcck_old_psw; /* 0x0160 */ 114 struct psw io_old_psw; /* 0x0170 */ 115 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 116 struct psw restart_new_psw; /* 0x01a0 */ 117 struct psw ext_new_psw; /* 0x01b0 */ 118 struct psw svc_new_psw; /* 0x01c0 */ 119 struct psw pgm_new_psw; /* 0x01d0 */ 120 struct psw mcck_new_psw; /* 0x01e0 */ 121 struct psw io_new_psw; /* 0x01f0 */ 122 /* sw definition: save area for registers in interrupt handlers */ 123 uint64_t sw_int_grs[16]; /* 0x0200 */ 124 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 125 uint64_t sw_int_crs[16]; /* 0x0308 */ 126 struct psw sw_int_psw; /* 0x0388 */ 127 uint8_t pad_0x0310[0x11b0 - 0x0398]; /* 0x0398 */ 128 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 129 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 130 uint64_t fprs_sa[16]; /* 0x1200 */ 131 uint64_t grs_sa[16]; /* 0x1280 */ 132 struct psw psw_sa; /* 0x1300 */ 133 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 134 uint32_t prefix_sa; /* 0x1318 */ 135 uint32_t fpc_sa; /* 0x131c */ 136 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 137 uint32_t tod_pr_sa; /* 0x1324 */ 138 uint64_t cputm_sa; /* 0x1328 */ 139 uint64_t cc_sa; /* 0x1330 */ 140 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 141 uint32_t ars_sa[16]; /* 0x1340 */ 142 uint64_t crs_sa[16]; /* 0x1380 */ 143 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 144 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 145 } __attribute__ ((__packed__)); 146 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 147 148 extern struct lowcore lowcore; 149 150 #define PGM_INT_CODE_OPERATION 0x01 151 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 152 #define PGM_INT_CODE_EXECUTE 0x03 153 #define PGM_INT_CODE_PROTECTION 0x04 154 #define PGM_INT_CODE_ADDRESSING 0x05 155 #define PGM_INT_CODE_SPECIFICATION 0x06 156 #define PGM_INT_CODE_DATA 0x07 157 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 158 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 159 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 160 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 161 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 162 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 163 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 164 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 165 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 166 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 167 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 168 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 169 #define PGM_INT_CODE_OPERAND 0x15 170 #define PGM_INT_CODE_TRACE_TABLE 0x16 171 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 172 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 173 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 174 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 175 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 176 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 177 #define PGM_INT_CODE_LX_TRANSLATION 0x22 178 #define PGM_INT_CODE_EX_TRANSLATION 0x23 179 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 180 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 181 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 182 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 183 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 184 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 185 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 186 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 187 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 188 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 189 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 190 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 191 #define PGM_INT_CODE_STACK_FULL 0x30 192 #define PGM_INT_CODE_STACK_EMPTY 0x31 193 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 194 #define PGM_INT_CODE_STACK_TYPE 0x33 195 #define PGM_INT_CODE_STACK_OPERATION 0x34 196 #define PGM_INT_CODE_ASCE_TYPE 0x38 197 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 198 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 199 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 200 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 201 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 202 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 203 #define PGM_INT_CODE_MONITOR_EVENT 0x40 204 #define PGM_INT_CODE_PER 0x80 205 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 206 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 207 208 struct cpuid { 209 uint64_t version : 8; 210 uint64_t id : 24; 211 uint64_t type : 16; 212 uint64_t format : 1; 213 uint64_t reserved : 15; 214 }; 215 216 #define SVC_LEAVE_PSTATE 1 217 218 static inline unsigned short stap(void) 219 { 220 unsigned short cpu_address; 221 222 asm volatile("stap %0" : "=Q" (cpu_address)); 223 return cpu_address; 224 } 225 226 static inline uint64_t stidp(void) 227 { 228 uint64_t cpuid; 229 230 asm volatile("stidp %0" : "=Q" (cpuid)); 231 232 return cpuid; 233 } 234 235 enum tprot_permission { 236 TPROT_READ_WRITE = 0, 237 TPROT_READ = 1, 238 TPROT_RW_PROTECTED = 2, 239 TPROT_TRANSL_UNAVAIL = 3, 240 }; 241 242 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 243 { 244 int cc; 245 246 asm volatile( 247 " tprot 0(%1),0(%2)\n" 248 " ipm %0\n" 249 " srl %0,28\n" 250 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 251 return (enum tprot_permission)cc; 252 } 253 254 static inline void lctlg(int cr, uint64_t value) 255 { 256 asm volatile( 257 " lctlg %1,%1,%0\n" 258 : : "Q" (value), "i" (cr)); 259 } 260 261 static inline uint64_t stctg(int cr) 262 { 263 uint64_t value; 264 265 asm volatile( 266 " stctg %1,%1,%0\n" 267 : "=Q" (value) : "i" (cr) : "memory"); 268 return value; 269 } 270 271 static inline void ctl_set_bit(int cr, unsigned int bit) 272 { 273 uint64_t reg; 274 275 reg = stctg(cr); 276 reg |= 1UL << bit; 277 lctlg(cr, reg); 278 } 279 280 static inline void ctl_clear_bit(int cr, unsigned int bit) 281 { 282 uint64_t reg; 283 284 reg = stctg(cr); 285 reg &= ~(1UL << bit); 286 lctlg(cr, reg); 287 } 288 289 static inline uint64_t extract_psw_mask(void) 290 { 291 uint32_t mask_upper = 0, mask_lower = 0; 292 293 asm volatile( 294 " epsw %0,%1\n" 295 : "=r" (mask_upper), "=a" (mask_lower)); 296 297 return (uint64_t) mask_upper << 32 | mask_lower; 298 } 299 300 static inline void load_psw_mask(uint64_t mask) 301 { 302 struct psw psw = { 303 .mask = mask, 304 .addr = 0, 305 }; 306 uint64_t tmp = 0; 307 308 asm volatile( 309 " larl %0,0f\n" 310 " stg %0,8(%1)\n" 311 " lpswe 0(%1)\n" 312 "0:\n" 313 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 314 } 315 316 static inline void wait_for_interrupt(uint64_t irq_mask) 317 { 318 uint64_t psw_mask = extract_psw_mask(); 319 320 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 321 /* 322 * After being woken and having processed the interrupt, let's restore 323 * the PSW mask. 324 */ 325 load_psw_mask(psw_mask); 326 } 327 328 static inline void enter_pstate(void) 329 { 330 uint64_t mask; 331 332 mask = extract_psw_mask(); 333 mask |= PSW_MASK_PSTATE; 334 load_psw_mask(mask); 335 } 336 337 static inline void leave_pstate(void) 338 { 339 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 340 } 341 342 static inline int stsi(void *addr, int fc, int sel1, int sel2) 343 { 344 register int r0 asm("0") = (fc << 28) | sel1; 345 register int r1 asm("1") = sel2; 346 int cc; 347 348 asm volatile( 349 "stsi 0(%3)\n" 350 "ipm %[cc]\n" 351 "srl %[cc],28\n" 352 : "+d" (r0), [cc] "=d" (cc) 353 : "d" (r1), "a" (addr) 354 : "cc", "memory"); 355 return cc; 356 } 357 358 static inline unsigned long stsi_get_fc(void) 359 { 360 register unsigned long r0 asm("0") = 0; 361 register unsigned long r1 asm("1") = 0; 362 int cc; 363 364 asm volatile("stsi 0\n" 365 "ipm %[cc]\n" 366 "srl %[cc],28\n" 367 : "+d" (r0), [cc] "=d" (cc) 368 : "d" (r1) 369 : "cc", "memory"); 370 assert(!cc); 371 return r0 >> 28; 372 } 373 374 static inline int servc(uint32_t command, unsigned long sccb) 375 { 376 int cc; 377 378 asm volatile( 379 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 380 " ipm %0\n" 381 " srl %0,28" 382 : "=&d" (cc) : "d" (command), "a" (sccb) 383 : "cc", "memory"); 384 return cc; 385 } 386 387 static inline void set_prefix(uint32_t new_prefix) 388 { 389 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 390 } 391 392 static inline uint32_t get_prefix(void) 393 { 394 uint32_t current_prefix; 395 396 asm volatile(" stpx %0" : "=Q" (current_prefix)); 397 return current_prefix; 398 } 399 400 #endif 401