1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 #define PSW(m, a) ((struct psw){ .mask = (m), .addr = (uint64_t)(a) }) 45 46 struct short_psw { 47 uint32_t mask; 48 uint32_t addr; 49 }; 50 51 struct cpu { 52 struct lowcore *lowcore; 53 uint64_t *stack; 54 void (*pgm_cleanup_func)(struct stack_frame_int *); 55 void (*ext_cleanup_func)(struct stack_frame_int *); 56 uint16_t addr; 57 uint16_t idx; 58 bool active; 59 bool pgm_int_expected; 60 bool ext_int_expected; 61 bool in_interrupt_handler; 62 }; 63 64 #define AS_PRIM 0 65 #define AS_ACCR 1 66 #define AS_SECN 2 67 #define AS_HOME 3 68 69 #define PSW_MASK_DAT 0x0400000000000000UL 70 #define PSW_MASK_IO 0x0200000000000000UL 71 #define PSW_MASK_EXT 0x0100000000000000UL 72 #define PSW_MASK_KEY 0x00F0000000000000UL 73 #define PSW_MASK_WAIT 0x0002000000000000UL 74 #define PSW_MASK_PSTATE 0x0001000000000000UL 75 #define PSW_MASK_EA 0x0000000100000000UL 76 #define PSW_MASK_BA 0x0000000080000000UL 77 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 78 79 #define CTL0_TRANSACT_EX_CTL (63 - 8) 80 #define CTL0_LOW_ADDR_PROT (63 - 35) 81 #define CTL0_EDAT (63 - 40) 82 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 83 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 84 #define CTL0_IEP (63 - 43) 85 #define CTL0_AFP (63 - 45) 86 #define CTL0_VECTOR (63 - 46) 87 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 88 #define CTL0_EXTERNAL_CALL (63 - 50) 89 #define CTL0_CLOCK_COMPARATOR (63 - 52) 90 #define CTL0_CPU_TIMER (63 - 53) 91 #define CTL0_SERVICE_SIGNAL (63 - 54) 92 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 93 94 #define CTL2_GUARDED_STORAGE (63 - 59) 95 96 struct lowcore { 97 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 98 uint32_t ext_int_param; /* 0x0080 */ 99 uint16_t cpu_addr; /* 0x0084 */ 100 uint16_t ext_int_code; /* 0x0086 */ 101 uint16_t svc_int_id; /* 0x0088 */ 102 uint16_t svc_int_code; /* 0x008a */ 103 uint16_t pgm_int_id; /* 0x008c */ 104 uint16_t pgm_int_code; /* 0x008e */ 105 uint32_t dxc_vxc; /* 0x0090 */ 106 uint16_t mon_class_nb; /* 0x0094 */ 107 uint8_t per_code; /* 0x0096 */ 108 uint8_t per_atmid; /* 0x0097 */ 109 uint64_t per_addr; /* 0x0098 */ 110 uint8_t exc_acc_id; /* 0x00a0 */ 111 uint8_t per_acc_id; /* 0x00a1 */ 112 uint8_t op_acc_id; /* 0x00a2 */ 113 uint8_t arch_mode_id; /* 0x00a3 */ 114 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 115 uint64_t trans_exc_id; /* 0x00a8 */ 116 uint64_t mon_code; /* 0x00b0 */ 117 uint32_t subsys_id_word; /* 0x00b8 */ 118 uint32_t io_int_param; /* 0x00bc */ 119 uint32_t io_int_word; /* 0x00c0 */ 120 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 121 uint32_t stfl; /* 0x00c8 */ 122 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 123 uint64_t mcck_int_code; /* 0x00e8 */ 124 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 125 uint32_t ext_damage_code; /* 0x00f4 */ 126 uint64_t failing_storage_addr; /* 0x00f8 */ 127 uint64_t emon_ca_origin; /* 0x0100 */ 128 uint32_t emon_ca_size; /* 0x0108 */ 129 uint32_t emon_exc_count; /* 0x010c */ 130 uint64_t breaking_event_addr; /* 0x0110 */ 131 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 132 struct psw restart_old_psw; /* 0x0120 */ 133 struct psw ext_old_psw; /* 0x0130 */ 134 struct psw svc_old_psw; /* 0x0140 */ 135 struct psw pgm_old_psw; /* 0x0150 */ 136 struct psw mcck_old_psw; /* 0x0160 */ 137 struct psw io_old_psw; /* 0x0170 */ 138 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 139 struct psw restart_new_psw; /* 0x01a0 */ 140 struct psw ext_new_psw; /* 0x01b0 */ 141 struct psw svc_new_psw; /* 0x01c0 */ 142 struct psw pgm_new_psw; /* 0x01d0 */ 143 struct psw mcck_new_psw; /* 0x01e0 */ 144 struct psw io_new_psw; /* 0x01f0 */ 145 /* sw definition: save area for registers in interrupt handlers */ 146 uint64_t sw_int_grs[16]; /* 0x0200 */ 147 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 148 uint64_t sw_int_crs[16]; /* 0x0308 */ 149 struct psw sw_int_psw; /* 0x0388 */ 150 struct cpu *this_cpu; /* 0x0398 */ 151 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 152 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 153 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 154 uint64_t fprs_sa[16]; /* 0x1200 */ 155 uint64_t grs_sa[16]; /* 0x1280 */ 156 struct psw psw_sa; /* 0x1300 */ 157 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 158 uint32_t prefix_sa; /* 0x1318 */ 159 uint32_t fpc_sa; /* 0x131c */ 160 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 161 uint32_t tod_pr_sa; /* 0x1324 */ 162 uint64_t cputm_sa; /* 0x1328 */ 163 uint64_t cc_sa; /* 0x1330 */ 164 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 165 uint32_t ars_sa[16]; /* 0x1340 */ 166 uint64_t crs_sa[16]; /* 0x1380 */ 167 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 168 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 169 } __attribute__ ((__packed__)); 170 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 171 172 extern struct lowcore lowcore; 173 174 #define THIS_CPU (lowcore.this_cpu) 175 176 #define PGM_INT_CODE_OPERATION 0x01 177 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 178 #define PGM_INT_CODE_EXECUTE 0x03 179 #define PGM_INT_CODE_PROTECTION 0x04 180 #define PGM_INT_CODE_ADDRESSING 0x05 181 #define PGM_INT_CODE_SPECIFICATION 0x06 182 #define PGM_INT_CODE_DATA 0x07 183 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 184 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 185 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 186 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 187 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 188 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 189 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 190 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 191 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 192 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 193 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 194 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 195 #define PGM_INT_CODE_OPERAND 0x15 196 #define PGM_INT_CODE_TRACE_TABLE 0x16 197 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 198 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 199 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 200 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 201 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 202 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 203 #define PGM_INT_CODE_LX_TRANSLATION 0x22 204 #define PGM_INT_CODE_EX_TRANSLATION 0x23 205 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 206 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 207 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 208 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 209 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 210 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 211 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 212 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 213 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 214 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 215 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 216 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 217 #define PGM_INT_CODE_STACK_FULL 0x30 218 #define PGM_INT_CODE_STACK_EMPTY 0x31 219 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 220 #define PGM_INT_CODE_STACK_TYPE 0x33 221 #define PGM_INT_CODE_STACK_OPERATION 0x34 222 #define PGM_INT_CODE_ASCE_TYPE 0x38 223 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 224 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 225 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 226 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 227 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 228 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 229 #define PGM_INT_CODE_MONITOR_EVENT 0x40 230 #define PGM_INT_CODE_PER 0x80 231 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 232 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 233 234 struct cpuid { 235 uint64_t version : 8; 236 uint64_t id : 24; 237 uint64_t type : 16; 238 uint64_t format : 1; 239 uint64_t reserved : 15; 240 }; 241 242 #define SVC_LEAVE_PSTATE 1 243 244 static inline unsigned short stap(void) 245 { 246 unsigned short cpu_address; 247 248 asm volatile("stap %0" : "=Q" (cpu_address)); 249 return cpu_address; 250 } 251 252 static inline uint64_t stidp(void) 253 { 254 uint64_t cpuid; 255 256 asm volatile("stidp %0" : "=Q" (cpuid)); 257 258 return cpuid; 259 } 260 261 enum tprot_permission { 262 TPROT_READ_WRITE = 0, 263 TPROT_READ = 1, 264 TPROT_RW_PROTECTED = 2, 265 TPROT_TRANSL_UNAVAIL = 3, 266 }; 267 268 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 269 { 270 int cc; 271 272 asm volatile( 273 " tprot 0(%1),0(%2)\n" 274 " ipm %0\n" 275 " srl %0,28\n" 276 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 277 return (enum tprot_permission)cc; 278 } 279 280 static inline void lctlg(int cr, uint64_t value) 281 { 282 asm volatile( 283 " lctlg %1,%1,%0\n" 284 : : "Q" (value), "i" (cr)); 285 } 286 287 static inline uint64_t stctg(int cr) 288 { 289 uint64_t value; 290 291 asm volatile( 292 " stctg %1,%1,%0\n" 293 : "=Q" (value) : "i" (cr) : "memory"); 294 return value; 295 } 296 297 static inline void ctl_set_bit(int cr, unsigned int bit) 298 { 299 uint64_t reg; 300 301 reg = stctg(cr); 302 reg |= 1UL << bit; 303 lctlg(cr, reg); 304 } 305 306 static inline void ctl_clear_bit(int cr, unsigned int bit) 307 { 308 uint64_t reg; 309 310 reg = stctg(cr); 311 reg &= ~(1UL << bit); 312 lctlg(cr, reg); 313 } 314 315 static inline uint64_t extract_psw_mask(void) 316 { 317 uint32_t mask_upper = 0, mask_lower = 0; 318 319 asm volatile( 320 " epsw %0,%1\n" 321 : "=r" (mask_upper), "=a" (mask_lower)); 322 323 return (uint64_t) mask_upper << 32 | mask_lower; 324 } 325 326 #define PSW_WITH_CUR_MASK(addr) PSW(extract_psw_mask(), (addr)) 327 328 static inline void load_psw_mask(uint64_t mask) 329 { 330 struct psw psw = { 331 .mask = mask, 332 .addr = 0, 333 }; 334 uint64_t tmp = 0; 335 336 asm volatile( 337 " larl %0,0f\n" 338 " stg %0,8(%1)\n" 339 " lpswe 0(%1)\n" 340 "0:\n" 341 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 342 } 343 344 static inline void disabled_wait(uint64_t message) 345 { 346 struct psw psw = { 347 .mask = PSW_MASK_WAIT, /* Disabled wait */ 348 .addr = message, 349 }; 350 351 asm volatile(" lpswe 0(%0)\n" : : "a" (&psw) : "memory", "cc"); 352 } 353 354 /** 355 * psw_mask_clear_bits - clears bits from the current PSW mask 356 * @clear: bitmask of bits that will be cleared 357 */ 358 static inline void psw_mask_clear_bits(uint64_t clear) 359 { 360 load_psw_mask(extract_psw_mask() & ~clear); 361 } 362 363 /** 364 * psw_mask_set_bits - sets bits on the current PSW mask 365 * @set: bitmask of bits that will be set 366 */ 367 static inline void psw_mask_set_bits(uint64_t set) 368 { 369 load_psw_mask(extract_psw_mask() | set); 370 } 371 372 /** 373 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 374 * @clear: bitmask of bits that will be cleared 375 * @set: bitmask of bits that will be set 376 * 377 * The bits in the @clear mask will be cleared, then the bits in the @set mask 378 * will be set. 379 */ 380 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 381 { 382 load_psw_mask((extract_psw_mask() & ~clear) | set); 383 } 384 385 /** 386 * enable_dat - enable the DAT bit in the current PSW 387 */ 388 static inline void enable_dat(void) 389 { 390 psw_mask_set_bits(PSW_MASK_DAT); 391 } 392 393 /** 394 * disable_dat - disable the DAT bit in the current PSW 395 */ 396 static inline void disable_dat(void) 397 { 398 psw_mask_clear_bits(PSW_MASK_DAT); 399 } 400 401 static inline void wait_for_interrupt(uint64_t irq_mask) 402 { 403 uint64_t psw_mask = extract_psw_mask(); 404 405 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 406 /* 407 * After being woken and having processed the interrupt, let's restore 408 * the PSW mask. 409 */ 410 load_psw_mask(psw_mask); 411 } 412 413 static inline void enter_pstate(void) 414 { 415 psw_mask_set_bits(PSW_MASK_PSTATE); 416 } 417 418 static inline void leave_pstate(void) 419 { 420 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 421 } 422 423 static inline int stsi(void *addr, int fc, int sel1, int sel2) 424 { 425 register int r0 asm("0") = (fc << 28) | sel1; 426 register int r1 asm("1") = sel2; 427 int cc; 428 429 asm volatile( 430 "stsi 0(%3)\n" 431 "ipm %[cc]\n" 432 "srl %[cc],28\n" 433 : "+d" (r0), [cc] "=d" (cc) 434 : "d" (r1), "a" (addr) 435 : "cc", "memory"); 436 return cc; 437 } 438 439 static inline unsigned long stsi_get_fc(void) 440 { 441 register unsigned long r0 asm("0") = 0; 442 register unsigned long r1 asm("1") = 0; 443 int cc; 444 445 asm volatile("stsi 0\n" 446 "ipm %[cc]\n" 447 "srl %[cc],28\n" 448 : "+d" (r0), [cc] "=d" (cc) 449 : "d" (r1) 450 : "cc", "memory"); 451 assert(!cc); 452 return r0 >> 28; 453 } 454 455 static inline int servc(uint32_t command, unsigned long sccb) 456 { 457 int cc; 458 459 asm volatile( 460 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 461 " ipm %0\n" 462 " srl %0,28" 463 : "=&d" (cc) : "d" (command), "a" (sccb) 464 : "cc", "memory"); 465 return cc; 466 } 467 468 static inline void set_prefix(uint32_t new_prefix) 469 { 470 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 471 } 472 473 static inline uint32_t get_prefix(void) 474 { 475 uint32_t current_prefix; 476 477 asm volatile(" stpx %0" : "=Q" (current_prefix)); 478 return current_prefix; 479 } 480 481 #endif 482