1 /* 2 * Copyright (c) 2017 Red Hat Inc 3 * 4 * Authors: 5 * David Hildenbrand <david@redhat.com> 6 * 7 * This code is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU Library General Public License version 2. 9 */ 10 #ifndef _ASM_S390X_ARCH_DEF_H_ 11 #define _ASM_S390X_ARCH_DEF_H_ 12 13 struct psw { 14 uint64_t mask; 15 uint64_t addr; 16 }; 17 18 #define PSW_MASK_EXT 0x0100000000000000UL 19 #define PSW_MASK_IO 0x0200000000000000UL 20 #define PSW_MASK_DAT 0x0400000000000000UL 21 #define PSW_MASK_WAIT 0x0002000000000000UL 22 #define PSW_MASK_PSTATE 0x0001000000000000UL 23 24 #define CR0_EXTM_SCLP 0x0000000000000200UL 25 #define CR0_EXTM_EXTC 0x0000000000002000UL 26 #define CR0_EXTM_EMGC 0x0000000000004000UL 27 #define CR0_EXTM_MASK 0x0000000000006200UL 28 29 struct lowcore { 30 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 31 uint32_t ext_int_param; /* 0x0080 */ 32 uint16_t cpu_addr; /* 0x0084 */ 33 uint16_t ext_int_code; /* 0x0086 */ 34 uint16_t svc_int_id; /* 0x0088 */ 35 uint16_t svc_int_code; /* 0x008a */ 36 uint16_t pgm_int_id; /* 0x008c */ 37 uint16_t pgm_int_code; /* 0x008e */ 38 uint32_t dxc_vxc; /* 0x0090 */ 39 uint16_t mon_class_nb; /* 0x0094 */ 40 uint8_t per_code; /* 0x0096 */ 41 uint8_t per_atmid; /* 0x0097 */ 42 uint64_t per_addr; /* 0x0098 */ 43 uint8_t exc_acc_id; /* 0x00a0 */ 44 uint8_t per_acc_id; /* 0x00a1 */ 45 uint8_t op_acc_id; /* 0x00a2 */ 46 uint8_t arch_mode_id; /* 0x00a3 */ 47 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 48 uint64_t trans_exc_id; /* 0x00a8 */ 49 uint64_t mon_code; /* 0x00b0 */ 50 uint32_t subsys_id_word; /* 0x00b8 */ 51 uint32_t io_int_param; /* 0x00bc */ 52 uint32_t io_int_word; /* 0x00c0 */ 53 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 54 uint32_t stfl; /* 0x00c8 */ 55 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 56 uint64_t mcck_int_code; /* 0x00e8 */ 57 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 58 uint32_t ext_damage_code; /* 0x00f4 */ 59 uint64_t failing_storage_addr; /* 0x00f8 */ 60 uint64_t emon_ca_origin; /* 0x0100 */ 61 uint32_t emon_ca_size; /* 0x0108 */ 62 uint32_t emon_exc_count; /* 0x010c */ 63 uint64_t breaking_event_addr; /* 0x0110 */ 64 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 65 struct psw restart_old_psw; /* 0x0120 */ 66 struct psw ext_old_psw; /* 0x0130 */ 67 struct psw svc_old_psw; /* 0x0140 */ 68 struct psw pgm_old_psw; /* 0x0150 */ 69 struct psw mcck_old_psw; /* 0x0160 */ 70 struct psw io_old_psw; /* 0x0170 */ 71 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 72 struct psw restart_new_psw; /* 0x01a0 */ 73 struct psw ext_new_psw; /* 0x01b0 */ 74 struct psw svc_new_psw; /* 0x01c0 */ 75 struct psw pgm_new_psw; /* 0x01d0 */ 76 struct psw mcck_new_psw; /* 0x01e0 */ 77 struct psw io_new_psw; /* 0x01f0 */ 78 /* sw definition: save area for registers in interrupt handlers */ 79 uint64_t sw_int_grs[16]; /* 0x0200 */ 80 uint64_t sw_int_fprs[16]; /* 0x0280 */ 81 uint32_t sw_int_fpc; /* 0x0300 */ 82 uint8_t pad_0x0304[0x0308 - 0x0304]; /* 0x0304 */ 83 uint64_t sw_int_crs[16]; /* 0x0308 */ 84 struct psw sw_int_psw; /* 0x0388 */ 85 uint8_t pad_0x0310[0x11b0 - 0x0398]; /* 0x0398 */ 86 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 87 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 88 uint64_t fprs_sa[16]; /* 0x1200 */ 89 uint64_t grs_sa[16]; /* 0x1280 */ 90 struct psw psw_sa; /* 0x1300 */ 91 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 92 uint32_t prefix_sa; /* 0x1318 */ 93 uint32_t fpc_sa; /* 0x131c */ 94 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 95 uint32_t tod_pr_sa; /* 0x1324 */ 96 uint64_t cputm_sa; /* 0x1328 */ 97 uint64_t cc_sa; /* 0x1330 */ 98 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 99 uint32_t ars_sa[16]; /* 0x1340 */ 100 uint64_t crs_sa[16]; /* 0x1380 */ 101 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 102 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 103 } __attribute__ ((__packed__)); 104 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 105 106 #define PGM_INT_CODE_OPERATION 0x01 107 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 108 #define PGM_INT_CODE_EXECUTE 0x03 109 #define PGM_INT_CODE_PROTECTION 0x04 110 #define PGM_INT_CODE_ADDRESSING 0x05 111 #define PGM_INT_CODE_SPECIFICATION 0x06 112 #define PGM_INT_CODE_DATA 0x07 113 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 114 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 115 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 116 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 117 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 118 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 119 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 120 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 121 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 122 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 123 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 124 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 125 #define PGM_INT_CODE_OPERAND 0x15 126 #define PGM_INT_CODE_TRACE_TABLE 0x16 127 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 128 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 129 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 130 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 131 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 132 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 133 #define PGM_INT_CODE_LX_TRANSLATION 0x22 134 #define PGM_INT_CODE_EX_TRANSLATION 0x23 135 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 136 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 137 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 138 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 139 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 140 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 141 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 142 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 143 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 144 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 145 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 146 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 147 #define PGM_INT_CODE_STACK_FULL 0x30 148 #define PGM_INT_CODE_STACK_EMPTY 0x31 149 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 150 #define PGM_INT_CODE_STACK_TYPE 0x33 151 #define PGM_INT_CODE_STACK_OPERATION 0x34 152 #define PGM_INT_CODE_ASCE_TYPE 0x38 153 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 154 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 155 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 156 #define PGM_INT_CODE_MONITOR_EVENT 0x40 157 #define PGM_INT_CODE_PER 0x80 158 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 159 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 160 161 struct cpuid { 162 uint64_t version : 8; 163 uint64_t id : 24; 164 uint64_t type : 16; 165 uint64_t format : 1; 166 uint64_t reserved : 15; 167 }; 168 169 static inline unsigned short stap(void) 170 { 171 unsigned short cpu_address; 172 173 asm volatile("stap %0" : "=Q" (cpu_address)); 174 return cpu_address; 175 } 176 177 static inline int tprot(unsigned long addr) 178 { 179 int cc; 180 181 asm volatile( 182 " tprot 0(%1),0\n" 183 " ipm %0\n" 184 " srl %0,28\n" 185 : "=d" (cc) : "a" (addr) : "cc"); 186 return cc; 187 } 188 189 static inline void lctlg(int cr, uint64_t value) 190 { 191 asm volatile( 192 " lctlg %1,%1,%0\n" 193 : : "Q" (value), "i" (cr)); 194 } 195 196 static inline uint64_t stctg(int cr) 197 { 198 uint64_t value; 199 200 asm volatile( 201 " stctg %1,%1,%0\n" 202 : "=Q" (value) : "i" (cr) : "memory"); 203 return value; 204 } 205 206 static inline void ctl_set_bit(int cr, unsigned int bit) 207 { 208 uint64_t reg; 209 210 reg = stctg(cr); 211 reg |= 1UL << bit; 212 lctlg(cr, reg); 213 } 214 215 static inline void ctl_clear_bit(int cr, unsigned int bit) 216 { 217 uint64_t reg; 218 219 reg = stctg(cr); 220 reg &= ~(1UL << bit); 221 lctlg(cr, reg); 222 } 223 224 static inline uint64_t extract_psw_mask(void) 225 { 226 uint32_t mask_upper = 0, mask_lower = 0; 227 228 asm volatile( 229 " epsw %0,%1\n" 230 : "+r" (mask_upper), "+r" (mask_lower) : : ); 231 232 return (uint64_t) mask_upper << 32 | mask_lower; 233 } 234 235 static inline void load_psw_mask(uint64_t mask) 236 { 237 struct psw psw = { 238 .mask = mask, 239 .addr = 0, 240 }; 241 uint64_t tmp = 0; 242 243 asm volatile( 244 " larl %0,0f\n" 245 " stg %0,8(%1)\n" 246 " lpswe 0(%1)\n" 247 "0:\n" 248 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 249 } 250 251 static inline void wait_for_interrupt(uint64_t irq_mask) 252 { 253 uint64_t psw_mask = extract_psw_mask(); 254 255 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 256 /* 257 * After being woken and having processed the interrupt, let's restore 258 * the PSW mask. 259 */ 260 load_psw_mask(psw_mask); 261 } 262 263 static inline void enter_pstate(void) 264 { 265 uint64_t mask; 266 267 mask = extract_psw_mask(); 268 mask |= PSW_MASK_PSTATE; 269 load_psw_mask(mask); 270 } 271 272 static inline int stsi(void *addr, int fc, int sel1, int sel2) 273 { 274 register int r0 asm("0") = (fc << 28) | sel1; 275 register int r1 asm("1") = sel2; 276 int cc; 277 278 asm volatile( 279 "stsi 0(%3)\n" 280 "ipm %[cc]\n" 281 "srl %[cc],28\n" 282 : "+d" (r0), [cc] "=d" (cc) 283 : "d" (r1), "a" (addr) 284 : "cc", "memory"); 285 return cc; 286 } 287 288 static inline int servc(uint32_t command, unsigned long sccb) 289 { 290 int cc; 291 292 asm volatile( 293 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 294 " ipm %0\n" 295 " srl %0,28" 296 : "=&d" (cc) : "d" (command), "a" (sccb) 297 : "cc", "memory"); 298 return cc; 299 } 300 301 static inline void set_prefix(uint32_t new_prefix) 302 { 303 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 304 } 305 306 static inline uint32_t get_prefix(void) 307 { 308 uint32_t current_prefix; 309 310 asm volatile(" stpx %0" : "=Q" (current_prefix)); 311 return current_prefix; 312 } 313 314 #endif 315