1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 struct short_psw { 45 uint32_t mask; 46 uint32_t addr; 47 }; 48 49 struct cpu { 50 struct lowcore *lowcore; 51 uint64_t *stack; 52 void (*pgm_cleanup_func)(struct stack_frame_int *); 53 void (*ext_cleanup_func)(struct stack_frame_int *); 54 uint16_t addr; 55 uint16_t idx; 56 bool active; 57 bool pgm_int_expected; 58 bool ext_int_expected; 59 bool in_interrupt_handler; 60 }; 61 62 #define AS_PRIM 0 63 #define AS_ACCR 1 64 #define AS_SECN 2 65 #define AS_HOME 3 66 67 #define PSW_MASK_DAT 0x0400000000000000UL 68 #define PSW_MASK_IO 0x0200000000000000UL 69 #define PSW_MASK_EXT 0x0100000000000000UL 70 #define PSW_MASK_KEY 0x00F0000000000000UL 71 #define PSW_MASK_WAIT 0x0002000000000000UL 72 #define PSW_MASK_PSTATE 0x0001000000000000UL 73 #define PSW_MASK_EA 0x0000000100000000UL 74 #define PSW_MASK_BA 0x0000000080000000UL 75 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 76 77 #define CTL0_TRANSACT_EX_CTL (63 - 8) 78 #define CTL0_LOW_ADDR_PROT (63 - 35) 79 #define CTL0_EDAT (63 - 40) 80 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 81 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 82 #define CTL0_IEP (63 - 43) 83 #define CTL0_AFP (63 - 45) 84 #define CTL0_VECTOR (63 - 46) 85 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 86 #define CTL0_EXTERNAL_CALL (63 - 50) 87 #define CTL0_CLOCK_COMPARATOR (63 - 52) 88 #define CTL0_CPU_TIMER (63 - 53) 89 #define CTL0_SERVICE_SIGNAL (63 - 54) 90 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 91 92 #define CTL2_GUARDED_STORAGE (63 - 59) 93 94 struct lowcore { 95 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 96 uint32_t ext_int_param; /* 0x0080 */ 97 uint16_t cpu_addr; /* 0x0084 */ 98 uint16_t ext_int_code; /* 0x0086 */ 99 uint16_t svc_int_id; /* 0x0088 */ 100 uint16_t svc_int_code; /* 0x008a */ 101 uint16_t pgm_int_id; /* 0x008c */ 102 uint16_t pgm_int_code; /* 0x008e */ 103 uint32_t dxc_vxc; /* 0x0090 */ 104 uint16_t mon_class_nb; /* 0x0094 */ 105 uint8_t per_code; /* 0x0096 */ 106 uint8_t per_atmid; /* 0x0097 */ 107 uint64_t per_addr; /* 0x0098 */ 108 uint8_t exc_acc_id; /* 0x00a0 */ 109 uint8_t per_acc_id; /* 0x00a1 */ 110 uint8_t op_acc_id; /* 0x00a2 */ 111 uint8_t arch_mode_id; /* 0x00a3 */ 112 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 113 uint64_t trans_exc_id; /* 0x00a8 */ 114 uint64_t mon_code; /* 0x00b0 */ 115 uint32_t subsys_id_word; /* 0x00b8 */ 116 uint32_t io_int_param; /* 0x00bc */ 117 uint32_t io_int_word; /* 0x00c0 */ 118 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 119 uint32_t stfl; /* 0x00c8 */ 120 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 121 uint64_t mcck_int_code; /* 0x00e8 */ 122 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 123 uint32_t ext_damage_code; /* 0x00f4 */ 124 uint64_t failing_storage_addr; /* 0x00f8 */ 125 uint64_t emon_ca_origin; /* 0x0100 */ 126 uint32_t emon_ca_size; /* 0x0108 */ 127 uint32_t emon_exc_count; /* 0x010c */ 128 uint64_t breaking_event_addr; /* 0x0110 */ 129 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 130 struct psw restart_old_psw; /* 0x0120 */ 131 struct psw ext_old_psw; /* 0x0130 */ 132 struct psw svc_old_psw; /* 0x0140 */ 133 struct psw pgm_old_psw; /* 0x0150 */ 134 struct psw mcck_old_psw; /* 0x0160 */ 135 struct psw io_old_psw; /* 0x0170 */ 136 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 137 struct psw restart_new_psw; /* 0x01a0 */ 138 struct psw ext_new_psw; /* 0x01b0 */ 139 struct psw svc_new_psw; /* 0x01c0 */ 140 struct psw pgm_new_psw; /* 0x01d0 */ 141 struct psw mcck_new_psw; /* 0x01e0 */ 142 struct psw io_new_psw; /* 0x01f0 */ 143 /* sw definition: save area for registers in interrupt handlers */ 144 uint64_t sw_int_grs[16]; /* 0x0200 */ 145 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 146 uint64_t sw_int_crs[16]; /* 0x0308 */ 147 struct psw sw_int_psw; /* 0x0388 */ 148 struct cpu *this_cpu; /* 0x0398 */ 149 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 150 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 151 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 152 uint64_t fprs_sa[16]; /* 0x1200 */ 153 uint64_t grs_sa[16]; /* 0x1280 */ 154 struct psw psw_sa; /* 0x1300 */ 155 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 156 uint32_t prefix_sa; /* 0x1318 */ 157 uint32_t fpc_sa; /* 0x131c */ 158 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 159 uint32_t tod_pr_sa; /* 0x1324 */ 160 uint64_t cputm_sa; /* 0x1328 */ 161 uint64_t cc_sa; /* 0x1330 */ 162 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 163 uint32_t ars_sa[16]; /* 0x1340 */ 164 uint64_t crs_sa[16]; /* 0x1380 */ 165 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 166 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 167 } __attribute__ ((__packed__)); 168 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 169 170 extern struct lowcore lowcore; 171 172 #define THIS_CPU (lowcore.this_cpu) 173 174 #define PGM_INT_CODE_OPERATION 0x01 175 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 176 #define PGM_INT_CODE_EXECUTE 0x03 177 #define PGM_INT_CODE_PROTECTION 0x04 178 #define PGM_INT_CODE_ADDRESSING 0x05 179 #define PGM_INT_CODE_SPECIFICATION 0x06 180 #define PGM_INT_CODE_DATA 0x07 181 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 182 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 183 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 184 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 185 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 186 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 187 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 188 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 189 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 190 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 191 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 192 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 193 #define PGM_INT_CODE_OPERAND 0x15 194 #define PGM_INT_CODE_TRACE_TABLE 0x16 195 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 196 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 197 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 198 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 199 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 200 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 201 #define PGM_INT_CODE_LX_TRANSLATION 0x22 202 #define PGM_INT_CODE_EX_TRANSLATION 0x23 203 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 204 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 205 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 206 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 207 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 208 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 209 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 210 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 211 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 212 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 213 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 214 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 215 #define PGM_INT_CODE_STACK_FULL 0x30 216 #define PGM_INT_CODE_STACK_EMPTY 0x31 217 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 218 #define PGM_INT_CODE_STACK_TYPE 0x33 219 #define PGM_INT_CODE_STACK_OPERATION 0x34 220 #define PGM_INT_CODE_ASCE_TYPE 0x38 221 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 222 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 223 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 224 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 225 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 226 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 227 #define PGM_INT_CODE_MONITOR_EVENT 0x40 228 #define PGM_INT_CODE_PER 0x80 229 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 230 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 231 232 struct cpuid { 233 uint64_t version : 8; 234 uint64_t id : 24; 235 uint64_t type : 16; 236 uint64_t format : 1; 237 uint64_t reserved : 15; 238 }; 239 240 #define SVC_LEAVE_PSTATE 1 241 242 static inline unsigned short stap(void) 243 { 244 unsigned short cpu_address; 245 246 asm volatile("stap %0" : "=Q" (cpu_address)); 247 return cpu_address; 248 } 249 250 static inline uint64_t stidp(void) 251 { 252 uint64_t cpuid; 253 254 asm volatile("stidp %0" : "=Q" (cpuid)); 255 256 return cpuid; 257 } 258 259 enum tprot_permission { 260 TPROT_READ_WRITE = 0, 261 TPROT_READ = 1, 262 TPROT_RW_PROTECTED = 2, 263 TPROT_TRANSL_UNAVAIL = 3, 264 }; 265 266 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 267 { 268 int cc; 269 270 asm volatile( 271 " tprot 0(%1),0(%2)\n" 272 " ipm %0\n" 273 " srl %0,28\n" 274 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 275 return (enum tprot_permission)cc; 276 } 277 278 static inline void lctlg(int cr, uint64_t value) 279 { 280 asm volatile( 281 " lctlg %1,%1,%0\n" 282 : : "Q" (value), "i" (cr)); 283 } 284 285 static inline uint64_t stctg(int cr) 286 { 287 uint64_t value; 288 289 asm volatile( 290 " stctg %1,%1,%0\n" 291 : "=Q" (value) : "i" (cr) : "memory"); 292 return value; 293 } 294 295 static inline void ctl_set_bit(int cr, unsigned int bit) 296 { 297 uint64_t reg; 298 299 reg = stctg(cr); 300 reg |= 1UL << bit; 301 lctlg(cr, reg); 302 } 303 304 static inline void ctl_clear_bit(int cr, unsigned int bit) 305 { 306 uint64_t reg; 307 308 reg = stctg(cr); 309 reg &= ~(1UL << bit); 310 lctlg(cr, reg); 311 } 312 313 static inline uint64_t extract_psw_mask(void) 314 { 315 uint32_t mask_upper = 0, mask_lower = 0; 316 317 asm volatile( 318 " epsw %0,%1\n" 319 : "=r" (mask_upper), "=a" (mask_lower)); 320 321 return (uint64_t) mask_upper << 32 | mask_lower; 322 } 323 324 static inline void load_psw_mask(uint64_t mask) 325 { 326 struct psw psw = { 327 .mask = mask, 328 .addr = 0, 329 }; 330 uint64_t tmp = 0; 331 332 asm volatile( 333 " larl %0,0f\n" 334 " stg %0,8(%1)\n" 335 " lpswe 0(%1)\n" 336 "0:\n" 337 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 338 } 339 340 static inline void disabled_wait(uint64_t message) 341 { 342 struct psw psw = { 343 .mask = PSW_MASK_WAIT, /* Disabled wait */ 344 .addr = message, 345 }; 346 347 asm volatile(" lpswe 0(%0)\n" : : "a" (&psw) : "memory", "cc"); 348 } 349 350 /** 351 * psw_mask_clear_bits - clears bits from the current PSW mask 352 * @clear: bitmask of bits that will be cleared 353 */ 354 static inline void psw_mask_clear_bits(uint64_t clear) 355 { 356 load_psw_mask(extract_psw_mask() & ~clear); 357 } 358 359 /** 360 * psw_mask_set_bits - sets bits on the current PSW mask 361 * @set: bitmask of bits that will be set 362 */ 363 static inline void psw_mask_set_bits(uint64_t set) 364 { 365 load_psw_mask(extract_psw_mask() | set); 366 } 367 368 /** 369 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 370 * @clear: bitmask of bits that will be cleared 371 * @set: bitmask of bits that will be set 372 * 373 * The bits in the @clear mask will be cleared, then the bits in the @set mask 374 * will be set. 375 */ 376 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 377 { 378 load_psw_mask((extract_psw_mask() & ~clear) | set); 379 } 380 381 /** 382 * enable_dat - enable the DAT bit in the current PSW 383 */ 384 static inline void enable_dat(void) 385 { 386 psw_mask_set_bits(PSW_MASK_DAT); 387 } 388 389 /** 390 * disable_dat - disable the DAT bit in the current PSW 391 */ 392 static inline void disable_dat(void) 393 { 394 psw_mask_clear_bits(PSW_MASK_DAT); 395 } 396 397 static inline void wait_for_interrupt(uint64_t irq_mask) 398 { 399 uint64_t psw_mask = extract_psw_mask(); 400 401 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 402 /* 403 * After being woken and having processed the interrupt, let's restore 404 * the PSW mask. 405 */ 406 load_psw_mask(psw_mask); 407 } 408 409 static inline void enter_pstate(void) 410 { 411 psw_mask_set_bits(PSW_MASK_PSTATE); 412 } 413 414 static inline void leave_pstate(void) 415 { 416 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 417 } 418 419 static inline int stsi(void *addr, int fc, int sel1, int sel2) 420 { 421 register int r0 asm("0") = (fc << 28) | sel1; 422 register int r1 asm("1") = sel2; 423 int cc; 424 425 asm volatile( 426 "stsi 0(%3)\n" 427 "ipm %[cc]\n" 428 "srl %[cc],28\n" 429 : "+d" (r0), [cc] "=d" (cc) 430 : "d" (r1), "a" (addr) 431 : "cc", "memory"); 432 return cc; 433 } 434 435 static inline unsigned long stsi_get_fc(void) 436 { 437 register unsigned long r0 asm("0") = 0; 438 register unsigned long r1 asm("1") = 0; 439 int cc; 440 441 asm volatile("stsi 0\n" 442 "ipm %[cc]\n" 443 "srl %[cc],28\n" 444 : "+d" (r0), [cc] "=d" (cc) 445 : "d" (r1) 446 : "cc", "memory"); 447 assert(!cc); 448 return r0 >> 28; 449 } 450 451 static inline int servc(uint32_t command, unsigned long sccb) 452 { 453 int cc; 454 455 asm volatile( 456 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 457 " ipm %0\n" 458 " srl %0,28" 459 : "=&d" (cc) : "d" (command), "a" (sccb) 460 : "cc", "memory"); 461 return cc; 462 } 463 464 static inline void set_prefix(uint32_t new_prefix) 465 { 466 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 467 } 468 469 static inline uint32_t get_prefix(void) 470 { 471 uint32_t current_prefix; 472 473 asm volatile(" stpx %0" : "=Q" (current_prefix)); 474 return current_prefix; 475 } 476 477 #endif 478