1 /* 2 * Copyright (c) 2017 Red Hat Inc 3 * 4 * Authors: 5 * David Hildenbrand <david@redhat.com> 6 * 7 * This code is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU Library General Public License version 2. 9 */ 10 #ifndef _ASM_S390X_ARCH_DEF_H_ 11 #define _ASM_S390X_ARCH_DEF_H_ 12 13 struct psw { 14 uint64_t mask; 15 uint64_t addr; 16 }; 17 18 struct lowcore { 19 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 20 uint32_t ext_int_param; /* 0x0080 */ 21 uint16_t cpu_addr; /* 0x0084 */ 22 uint16_t ext_int_code; /* 0x0086 */ 23 uint16_t svc_int_id; /* 0x0088 */ 24 uint16_t svc_int_code; /* 0x008a */ 25 uint16_t pgm_int_id; /* 0x008c */ 26 uint16_t pgm_int_code; /* 0x008e */ 27 uint32_t dxc_vxc; /* 0x0090 */ 28 uint16_t mon_class_nb; /* 0x0094 */ 29 uint8_t per_code; /* 0x0096 */ 30 uint8_t per_atmid; /* 0x0097 */ 31 uint64_t per_addr; /* 0x0098 */ 32 uint8_t exc_acc_id; /* 0x00a0 */ 33 uint8_t per_acc_id; /* 0x00a1 */ 34 uint8_t op_acc_id; /* 0x00a2 */ 35 uint8_t arch_mode_id; /* 0x00a3 */ 36 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 37 uint64_t trans_exc_id; /* 0x00a8 */ 38 uint64_t mon_code; /* 0x00b0 */ 39 uint32_t subsys_id_word; /* 0x00b8 */ 40 uint32_t io_int_param; /* 0x00bc */ 41 uint32_t io_int_word; /* 0x00c0 */ 42 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 43 uint32_t stfl; /* 0x00c8 */ 44 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 45 uint64_t mcck_int_code; /* 0x00e8 */ 46 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 47 uint32_t ext_damage_code; /* 0x00f4 */ 48 uint64_t failing_storage_addr; /* 0x00f8 */ 49 uint64_t emon_ca_origin; /* 0x0100 */ 50 uint32_t emon_ca_size; /* 0x0108 */ 51 uint32_t emon_exc_count; /* 0x010c */ 52 uint64_t breaking_event_addr; /* 0x0110 */ 53 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 54 struct psw restart_old_psw; /* 0x0120 */ 55 struct psw ext_old_psw; /* 0x0130 */ 56 struct psw svc_old_psw; /* 0x0140 */ 57 struct psw pgm_old_psw; /* 0x0150 */ 58 struct psw mcck_old_psw; /* 0x0160 */ 59 struct psw io_old_psw; /* 0x0170 */ 60 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 61 struct psw restart_new_psw; /* 0x01a0 */ 62 struct psw ext_new_psw; /* 0x01b0 */ 63 struct psw svc_new_psw; /* 0x01c0 */ 64 struct psw pgm_new_psw; /* 0x01d0 */ 65 struct psw mcck_new_psw; /* 0x01e0 */ 66 struct psw io_new_psw; /* 0x01f0 */ 67 /* sw definition: save area for registers in interrupt handlers */ 68 uint64_t sw_int_grs[16]; /* 0x0200 */ 69 uint64_t sw_int_fprs[16]; /* 0x0280 */ 70 uint32_t sw_int_fpc; /* 0x0300 */ 71 uint8_t pad_0x0304[0x11b0 - 0x0304]; /* 0x0304 */ 72 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 73 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 74 uint64_t fprs_sa[16]; /* 0x1200 */ 75 uint64_t grs_sa[16]; /* 0x1280 */ 76 struct psw psw_sa; /* 0x1300 */ 77 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 78 uint32_t prefix_sa; /* 0x1318 */ 79 uint32_t fpc_sa; /* 0x131c */ 80 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 81 uint32_t tod_pr_sa; /* 0x1324 */ 82 uint64_t cputm_sa; /* 0x1328 */ 83 uint64_t cc_sa; /* 0x1330 */ 84 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 85 uint32_t ars_sa[16]; /* 0x1340 */ 86 uint64_t crs_sa[16]; /* 0x1380 */ 87 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 88 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 89 } __attribute__ ((__packed__)); 90 91 #define PGM_INT_CODE_OPERATION 0x01 92 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 93 #define PGM_INT_CODE_EXECUTE 0x03 94 #define PGM_INT_CODE_PROTECTION 0x04 95 #define PGM_INT_CODE_ADDRESSING 0x05 96 #define PGM_INT_CODE_SPECIFICATION 0x06 97 #define PGM_INT_CODE_DATA 0x07 98 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 99 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 100 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 101 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 102 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 103 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 104 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 105 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 106 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 107 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 108 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 109 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 110 #define PGM_INT_CODE_OPERAND 0x15 111 #define PGM_INT_CODE_TRACE_TABLE 0x16 112 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 113 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 114 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 115 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 116 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 117 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 118 #define PGM_INT_CODE_LX_TRANSLATION 0x22 119 #define PGM_INT_CODE_EX_TRANSLATION 0x23 120 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 121 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 122 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 123 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 124 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 125 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 126 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 127 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 128 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 129 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 130 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 131 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 132 #define PGM_INT_CODE_STACK_FULL 0x30 133 #define PGM_INT_CODE_STACK_EMPTY 0x31 134 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 135 #define PGM_INT_CODE_STACK_TYPE 0x33 136 #define PGM_INT_CODE_STACK_OPERATION 0x34 137 #define PGM_INT_CODE_ASCE_TYPE 0x38 138 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 139 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 140 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 141 #define PGM_INT_CODE_MONITOR_EVENT 0x40 142 #define PGM_INT_CODE_PER 0x80 143 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 144 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 145 146 struct cpuid { 147 uint64_t version : 8; 148 uint64_t id : 24; 149 uint64_t type : 16; 150 uint64_t format : 1; 151 uint64_t reserved : 15; 152 }; 153 154 #endif 155