1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 struct cpu { 45 struct lowcore *lowcore; 46 uint64_t *stack; 47 void (*pgm_cleanup_func)(struct stack_frame_int *); 48 void (*ext_cleanup_func)(struct stack_frame_int *); 49 uint16_t addr; 50 uint16_t idx; 51 bool active; 52 bool pgm_int_expected; 53 bool ext_int_expected; 54 }; 55 56 #define AS_PRIM 0 57 #define AS_ACCR 1 58 #define AS_SECN 2 59 #define AS_HOME 3 60 61 #define PSW_MASK_DAT 0x0400000000000000UL 62 #define PSW_MASK_IO 0x0200000000000000UL 63 #define PSW_MASK_EXT 0x0100000000000000UL 64 #define PSW_MASK_KEY 0x00F0000000000000UL 65 #define PSW_MASK_WAIT 0x0002000000000000UL 66 #define PSW_MASK_PSTATE 0x0001000000000000UL 67 #define PSW_MASK_EA 0x0000000100000000UL 68 #define PSW_MASK_BA 0x0000000080000000UL 69 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 70 71 #define CTL0_LOW_ADDR_PROT (63 - 35) 72 #define CTL0_EDAT (63 - 40) 73 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 74 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 75 #define CTL0_IEP (63 - 43) 76 #define CTL0_AFP (63 - 45) 77 #define CTL0_VECTOR (63 - 46) 78 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 79 #define CTL0_EXTERNAL_CALL (63 - 50) 80 #define CTL0_CLOCK_COMPARATOR (63 - 52) 81 #define CTL0_SERVICE_SIGNAL (63 - 54) 82 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 83 84 #define CTL2_GUARDED_STORAGE (63 - 59) 85 86 struct lowcore { 87 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 88 uint32_t ext_int_param; /* 0x0080 */ 89 uint16_t cpu_addr; /* 0x0084 */ 90 uint16_t ext_int_code; /* 0x0086 */ 91 uint16_t svc_int_id; /* 0x0088 */ 92 uint16_t svc_int_code; /* 0x008a */ 93 uint16_t pgm_int_id; /* 0x008c */ 94 uint16_t pgm_int_code; /* 0x008e */ 95 uint32_t dxc_vxc; /* 0x0090 */ 96 uint16_t mon_class_nb; /* 0x0094 */ 97 uint8_t per_code; /* 0x0096 */ 98 uint8_t per_atmid; /* 0x0097 */ 99 uint64_t per_addr; /* 0x0098 */ 100 uint8_t exc_acc_id; /* 0x00a0 */ 101 uint8_t per_acc_id; /* 0x00a1 */ 102 uint8_t op_acc_id; /* 0x00a2 */ 103 uint8_t arch_mode_id; /* 0x00a3 */ 104 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 105 uint64_t trans_exc_id; /* 0x00a8 */ 106 uint64_t mon_code; /* 0x00b0 */ 107 uint32_t subsys_id_word; /* 0x00b8 */ 108 uint32_t io_int_param; /* 0x00bc */ 109 uint32_t io_int_word; /* 0x00c0 */ 110 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 111 uint32_t stfl; /* 0x00c8 */ 112 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 113 uint64_t mcck_int_code; /* 0x00e8 */ 114 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 115 uint32_t ext_damage_code; /* 0x00f4 */ 116 uint64_t failing_storage_addr; /* 0x00f8 */ 117 uint64_t emon_ca_origin; /* 0x0100 */ 118 uint32_t emon_ca_size; /* 0x0108 */ 119 uint32_t emon_exc_count; /* 0x010c */ 120 uint64_t breaking_event_addr; /* 0x0110 */ 121 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 122 struct psw restart_old_psw; /* 0x0120 */ 123 struct psw ext_old_psw; /* 0x0130 */ 124 struct psw svc_old_psw; /* 0x0140 */ 125 struct psw pgm_old_psw; /* 0x0150 */ 126 struct psw mcck_old_psw; /* 0x0160 */ 127 struct psw io_old_psw; /* 0x0170 */ 128 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 129 struct psw restart_new_psw; /* 0x01a0 */ 130 struct psw ext_new_psw; /* 0x01b0 */ 131 struct psw svc_new_psw; /* 0x01c0 */ 132 struct psw pgm_new_psw; /* 0x01d0 */ 133 struct psw mcck_new_psw; /* 0x01e0 */ 134 struct psw io_new_psw; /* 0x01f0 */ 135 /* sw definition: save area for registers in interrupt handlers */ 136 uint64_t sw_int_grs[16]; /* 0x0200 */ 137 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 138 uint64_t sw_int_crs[16]; /* 0x0308 */ 139 struct psw sw_int_psw; /* 0x0388 */ 140 struct cpu *this_cpu; /* 0x0398 */ 141 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 142 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 143 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 144 uint64_t fprs_sa[16]; /* 0x1200 */ 145 uint64_t grs_sa[16]; /* 0x1280 */ 146 struct psw psw_sa; /* 0x1300 */ 147 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 148 uint32_t prefix_sa; /* 0x1318 */ 149 uint32_t fpc_sa; /* 0x131c */ 150 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 151 uint32_t tod_pr_sa; /* 0x1324 */ 152 uint64_t cputm_sa; /* 0x1328 */ 153 uint64_t cc_sa; /* 0x1330 */ 154 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 155 uint32_t ars_sa[16]; /* 0x1340 */ 156 uint64_t crs_sa[16]; /* 0x1380 */ 157 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 158 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 159 } __attribute__ ((__packed__)); 160 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 161 162 extern struct lowcore lowcore; 163 164 #define THIS_CPU (lowcore.this_cpu) 165 166 #define PGM_INT_CODE_OPERATION 0x01 167 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 168 #define PGM_INT_CODE_EXECUTE 0x03 169 #define PGM_INT_CODE_PROTECTION 0x04 170 #define PGM_INT_CODE_ADDRESSING 0x05 171 #define PGM_INT_CODE_SPECIFICATION 0x06 172 #define PGM_INT_CODE_DATA 0x07 173 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 174 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 175 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 176 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 177 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 178 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 179 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 180 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 181 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 182 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 183 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 184 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 185 #define PGM_INT_CODE_OPERAND 0x15 186 #define PGM_INT_CODE_TRACE_TABLE 0x16 187 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 188 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 189 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 190 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 191 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 192 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 193 #define PGM_INT_CODE_LX_TRANSLATION 0x22 194 #define PGM_INT_CODE_EX_TRANSLATION 0x23 195 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 196 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 197 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 198 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 199 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 200 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 201 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 202 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 203 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 204 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 205 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 206 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 207 #define PGM_INT_CODE_STACK_FULL 0x30 208 #define PGM_INT_CODE_STACK_EMPTY 0x31 209 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 210 #define PGM_INT_CODE_STACK_TYPE 0x33 211 #define PGM_INT_CODE_STACK_OPERATION 0x34 212 #define PGM_INT_CODE_ASCE_TYPE 0x38 213 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 214 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 215 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 216 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 217 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 218 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 219 #define PGM_INT_CODE_MONITOR_EVENT 0x40 220 #define PGM_INT_CODE_PER 0x80 221 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 222 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 223 224 struct cpuid { 225 uint64_t version : 8; 226 uint64_t id : 24; 227 uint64_t type : 16; 228 uint64_t format : 1; 229 uint64_t reserved : 15; 230 }; 231 232 #define SVC_LEAVE_PSTATE 1 233 234 static inline unsigned short stap(void) 235 { 236 unsigned short cpu_address; 237 238 asm volatile("stap %0" : "=Q" (cpu_address)); 239 return cpu_address; 240 } 241 242 static inline uint64_t stidp(void) 243 { 244 uint64_t cpuid; 245 246 asm volatile("stidp %0" : "=Q" (cpuid)); 247 248 return cpuid; 249 } 250 251 enum tprot_permission { 252 TPROT_READ_WRITE = 0, 253 TPROT_READ = 1, 254 TPROT_RW_PROTECTED = 2, 255 TPROT_TRANSL_UNAVAIL = 3, 256 }; 257 258 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 259 { 260 int cc; 261 262 asm volatile( 263 " tprot 0(%1),0(%2)\n" 264 " ipm %0\n" 265 " srl %0,28\n" 266 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 267 return (enum tprot_permission)cc; 268 } 269 270 static inline void lctlg(int cr, uint64_t value) 271 { 272 asm volatile( 273 " lctlg %1,%1,%0\n" 274 : : "Q" (value), "i" (cr)); 275 } 276 277 static inline uint64_t stctg(int cr) 278 { 279 uint64_t value; 280 281 asm volatile( 282 " stctg %1,%1,%0\n" 283 : "=Q" (value) : "i" (cr) : "memory"); 284 return value; 285 } 286 287 static inline void ctl_set_bit(int cr, unsigned int bit) 288 { 289 uint64_t reg; 290 291 reg = stctg(cr); 292 reg |= 1UL << bit; 293 lctlg(cr, reg); 294 } 295 296 static inline void ctl_clear_bit(int cr, unsigned int bit) 297 { 298 uint64_t reg; 299 300 reg = stctg(cr); 301 reg &= ~(1UL << bit); 302 lctlg(cr, reg); 303 } 304 305 static inline uint64_t extract_psw_mask(void) 306 { 307 uint32_t mask_upper = 0, mask_lower = 0; 308 309 asm volatile( 310 " epsw %0,%1\n" 311 : "=r" (mask_upper), "=a" (mask_lower)); 312 313 return (uint64_t) mask_upper << 32 | mask_lower; 314 } 315 316 static inline void load_psw_mask(uint64_t mask) 317 { 318 struct psw psw = { 319 .mask = mask, 320 .addr = 0, 321 }; 322 uint64_t tmp = 0; 323 324 asm volatile( 325 " larl %0,0f\n" 326 " stg %0,8(%1)\n" 327 " lpswe 0(%1)\n" 328 "0:\n" 329 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 330 } 331 332 /** 333 * psw_mask_clear_bits - clears bits from the current PSW mask 334 * @clear: bitmask of bits that will be cleared 335 */ 336 static inline void psw_mask_clear_bits(uint64_t clear) 337 { 338 load_psw_mask(extract_psw_mask() & ~clear); 339 } 340 341 /** 342 * psw_mask_set_bits - sets bits on the current PSW mask 343 * @set: bitmask of bits that will be set 344 */ 345 static inline void psw_mask_set_bits(uint64_t set) 346 { 347 load_psw_mask(extract_psw_mask() | set); 348 } 349 350 /** 351 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 352 * @clear: bitmask of bits that will be cleared 353 * @set: bitmask of bits that will be set 354 * 355 * The bits in the @clear mask will be cleared, then the bits in the @set mask 356 * will be set. 357 */ 358 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 359 { 360 load_psw_mask((extract_psw_mask() & ~clear) | set); 361 } 362 363 /** 364 * enable_dat - enable the DAT bit in the current PSW 365 */ 366 static inline void enable_dat(void) 367 { 368 psw_mask_set_bits(PSW_MASK_DAT); 369 } 370 371 /** 372 * disable_dat - disable the DAT bit in the current PSW 373 */ 374 static inline void disable_dat(void) 375 { 376 psw_mask_clear_bits(PSW_MASK_DAT); 377 } 378 379 static inline void wait_for_interrupt(uint64_t irq_mask) 380 { 381 uint64_t psw_mask = extract_psw_mask(); 382 383 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 384 /* 385 * After being woken and having processed the interrupt, let's restore 386 * the PSW mask. 387 */ 388 load_psw_mask(psw_mask); 389 } 390 391 static inline void enter_pstate(void) 392 { 393 psw_mask_set_bits(PSW_MASK_PSTATE); 394 } 395 396 static inline void leave_pstate(void) 397 { 398 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 399 } 400 401 static inline int stsi(void *addr, int fc, int sel1, int sel2) 402 { 403 register int r0 asm("0") = (fc << 28) | sel1; 404 register int r1 asm("1") = sel2; 405 int cc; 406 407 asm volatile( 408 "stsi 0(%3)\n" 409 "ipm %[cc]\n" 410 "srl %[cc],28\n" 411 : "+d" (r0), [cc] "=d" (cc) 412 : "d" (r1), "a" (addr) 413 : "cc", "memory"); 414 return cc; 415 } 416 417 static inline unsigned long stsi_get_fc(void) 418 { 419 register unsigned long r0 asm("0") = 0; 420 register unsigned long r1 asm("1") = 0; 421 int cc; 422 423 asm volatile("stsi 0\n" 424 "ipm %[cc]\n" 425 "srl %[cc],28\n" 426 : "+d" (r0), [cc] "=d" (cc) 427 : "d" (r1) 428 : "cc", "memory"); 429 assert(!cc); 430 return r0 >> 28; 431 } 432 433 static inline int servc(uint32_t command, unsigned long sccb) 434 { 435 int cc; 436 437 asm volatile( 438 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 439 " ipm %0\n" 440 " srl %0,28" 441 : "=&d" (cc) : "d" (command), "a" (sccb) 442 : "cc", "memory"); 443 return cc; 444 } 445 446 static inline void set_prefix(uint32_t new_prefix) 447 { 448 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 449 } 450 451 static inline uint32_t get_prefix(void) 452 { 453 uint32_t current_prefix; 454 455 asm volatile(" stpx %0" : "=Q" (current_prefix)); 456 return current_prefix; 457 } 458 459 #endif 460