1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2017 Red Hat Inc 4 * 5 * Authors: 6 * David Hildenbrand <david@redhat.com> 7 */ 8 #ifndef _ASMS390X_ARCH_DEF_H_ 9 #define _ASMS390X_ARCH_DEF_H_ 10 11 struct stack_frame { 12 struct stack_frame *back_chain; 13 uint64_t reserved; 14 /* GRs 2 - 5 */ 15 uint64_t argument_area[4]; 16 /* GRs 6 - 15 */ 17 uint64_t grs[10]; 18 /* FPRs 0, 2, 4, 6 */ 19 int64_t fprs[4]; 20 }; 21 22 struct stack_frame_int { 23 struct stack_frame *back_chain; 24 uint64_t reserved; 25 /* 26 * The GRs are offset compatible with struct stack_frame so we 27 * can easily fetch GR14 for backtraces. 28 */ 29 /* GRs 2 - 15 */ 30 uint64_t grs0[14]; 31 /* GRs 0 and 1 */ 32 uint64_t grs1[2]; 33 uint32_t reserved1; 34 uint32_t fpc; 35 uint64_t fprs[16]; 36 uint64_t crs[16]; 37 }; 38 39 struct psw { 40 uint64_t mask; 41 uint64_t addr; 42 }; 43 44 struct cpu { 45 struct lowcore *lowcore; 46 uint64_t *stack; 47 void (*pgm_cleanup_func)(struct stack_frame_int *); 48 void (*ext_cleanup_func)(struct stack_frame_int *); 49 uint16_t addr; 50 uint16_t idx; 51 bool active; 52 bool pgm_int_expected; 53 bool ext_int_expected; 54 }; 55 56 #define AS_PRIM 0 57 #define AS_ACCR 1 58 #define AS_SECN 2 59 #define AS_HOME 3 60 61 #define PSW_MASK_DAT 0x0400000000000000UL 62 #define PSW_MASK_IO 0x0200000000000000UL 63 #define PSW_MASK_EXT 0x0100000000000000UL 64 #define PSW_MASK_KEY 0x00F0000000000000UL 65 #define PSW_MASK_WAIT 0x0002000000000000UL 66 #define PSW_MASK_PSTATE 0x0001000000000000UL 67 #define PSW_MASK_EA 0x0000000100000000UL 68 #define PSW_MASK_BA 0x0000000080000000UL 69 #define PSW_MASK_64 (PSW_MASK_BA | PSW_MASK_EA) 70 71 #define CTL0_LOW_ADDR_PROT (63 - 35) 72 #define CTL0_EDAT (63 - 40) 73 #define CTL0_FETCH_PROTECTION_OVERRIDE (63 - 38) 74 #define CTL0_STORAGE_PROTECTION_OVERRIDE (63 - 39) 75 #define CTL0_IEP (63 - 43) 76 #define CTL0_AFP (63 - 45) 77 #define CTL0_VECTOR (63 - 46) 78 #define CTL0_EMERGENCY_SIGNAL (63 - 49) 79 #define CTL0_EXTERNAL_CALL (63 - 50) 80 #define CTL0_CLOCK_COMPARATOR (63 - 52) 81 #define CTL0_CPU_TIMER (63 - 53) 82 #define CTL0_SERVICE_SIGNAL (63 - 54) 83 #define CR0_EXTM_MASK 0x0000000000006200UL /* Combined external masks */ 84 85 #define CTL2_GUARDED_STORAGE (63 - 59) 86 87 struct lowcore { 88 uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */ 89 uint32_t ext_int_param; /* 0x0080 */ 90 uint16_t cpu_addr; /* 0x0084 */ 91 uint16_t ext_int_code; /* 0x0086 */ 92 uint16_t svc_int_id; /* 0x0088 */ 93 uint16_t svc_int_code; /* 0x008a */ 94 uint16_t pgm_int_id; /* 0x008c */ 95 uint16_t pgm_int_code; /* 0x008e */ 96 uint32_t dxc_vxc; /* 0x0090 */ 97 uint16_t mon_class_nb; /* 0x0094 */ 98 uint8_t per_code; /* 0x0096 */ 99 uint8_t per_atmid; /* 0x0097 */ 100 uint64_t per_addr; /* 0x0098 */ 101 uint8_t exc_acc_id; /* 0x00a0 */ 102 uint8_t per_acc_id; /* 0x00a1 */ 103 uint8_t op_acc_id; /* 0x00a2 */ 104 uint8_t arch_mode_id; /* 0x00a3 */ 105 uint8_t pad_0x00a4[0x00a8 - 0x00a4]; /* 0x00a4 */ 106 uint64_t trans_exc_id; /* 0x00a8 */ 107 uint64_t mon_code; /* 0x00b0 */ 108 uint32_t subsys_id_word; /* 0x00b8 */ 109 uint32_t io_int_param; /* 0x00bc */ 110 uint32_t io_int_word; /* 0x00c0 */ 111 uint8_t pad_0x00c4[0x00c8 - 0x00c4]; /* 0x00c4 */ 112 uint32_t stfl; /* 0x00c8 */ 113 uint8_t pad_0x00cc[0x00e8 - 0x00cc]; /* 0x00cc */ 114 uint64_t mcck_int_code; /* 0x00e8 */ 115 uint8_t pad_0x00f0[0x00f4 - 0x00f0]; /* 0x00f0 */ 116 uint32_t ext_damage_code; /* 0x00f4 */ 117 uint64_t failing_storage_addr; /* 0x00f8 */ 118 uint64_t emon_ca_origin; /* 0x0100 */ 119 uint32_t emon_ca_size; /* 0x0108 */ 120 uint32_t emon_exc_count; /* 0x010c */ 121 uint64_t breaking_event_addr; /* 0x0110 */ 122 uint8_t pad_0x0118[0x0120 - 0x0118]; /* 0x0118 */ 123 struct psw restart_old_psw; /* 0x0120 */ 124 struct psw ext_old_psw; /* 0x0130 */ 125 struct psw svc_old_psw; /* 0x0140 */ 126 struct psw pgm_old_psw; /* 0x0150 */ 127 struct psw mcck_old_psw; /* 0x0160 */ 128 struct psw io_old_psw; /* 0x0170 */ 129 uint8_t pad_0x0180[0x01a0 - 0x0180]; /* 0x0180 */ 130 struct psw restart_new_psw; /* 0x01a0 */ 131 struct psw ext_new_psw; /* 0x01b0 */ 132 struct psw svc_new_psw; /* 0x01c0 */ 133 struct psw pgm_new_psw; /* 0x01d0 */ 134 struct psw mcck_new_psw; /* 0x01e0 */ 135 struct psw io_new_psw; /* 0x01f0 */ 136 /* sw definition: save area for registers in interrupt handlers */ 137 uint64_t sw_int_grs[16]; /* 0x0200 */ 138 uint8_t pad_0x0280[0x0308 - 0x0280]; /* 0x0280 */ 139 uint64_t sw_int_crs[16]; /* 0x0308 */ 140 struct psw sw_int_psw; /* 0x0388 */ 141 struct cpu *this_cpu; /* 0x0398 */ 142 uint8_t pad_0x03a0[0x11b0 - 0x03a0]; /* 0x03a0 */ 143 uint64_t mcck_ext_sa_addr; /* 0x11b0 */ 144 uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ 145 uint64_t fprs_sa[16]; /* 0x1200 */ 146 uint64_t grs_sa[16]; /* 0x1280 */ 147 struct psw psw_sa; /* 0x1300 */ 148 uint8_t pad_0x1310[0x1318 - 0x1310]; /* 0x1310 */ 149 uint32_t prefix_sa; /* 0x1318 */ 150 uint32_t fpc_sa; /* 0x131c */ 151 uint8_t pad_0x1320[0x1324 - 0x1320]; /* 0x1320 */ 152 uint32_t tod_pr_sa; /* 0x1324 */ 153 uint64_t cputm_sa; /* 0x1328 */ 154 uint64_t cc_sa; /* 0x1330 */ 155 uint8_t pad_0x1338[0x1340 - 0x1338]; /* 0x1338 */ 156 uint32_t ars_sa[16]; /* 0x1340 */ 157 uint64_t crs_sa[16]; /* 0x1380 */ 158 uint8_t pad_0x1400[0x1800 - 0x1400]; /* 0x1400 */ 159 uint8_t pgm_int_tdb[0x1900 - 0x1800]; /* 0x1800 */ 160 } __attribute__ ((__packed__)); 161 _Static_assert(sizeof(struct lowcore) == 0x1900, "Lowcore size"); 162 163 extern struct lowcore lowcore; 164 165 #define THIS_CPU (lowcore.this_cpu) 166 167 #define PGM_INT_CODE_OPERATION 0x01 168 #define PGM_INT_CODE_PRIVILEGED_OPERATION 0x02 169 #define PGM_INT_CODE_EXECUTE 0x03 170 #define PGM_INT_CODE_PROTECTION 0x04 171 #define PGM_INT_CODE_ADDRESSING 0x05 172 #define PGM_INT_CODE_SPECIFICATION 0x06 173 #define PGM_INT_CODE_DATA 0x07 174 #define PGM_INT_CODE_FIXED_POINT_OVERFLOW 0x08 175 #define PGM_INT_CODE_FIXED_POINT_DIVIDE 0x09 176 #define PGM_INT_CODE_DECIMAL_OVERFLOW 0x0a 177 #define PGM_INT_CODE_DECIMAL_DIVIDE 0x0b 178 #define PGM_INT_CODE_HFP_EXPONENT_OVERFLOW 0x0c 179 #define PGM_INT_CODE_HFP_EXPONENT_UNDERFLOW 0x0d 180 #define PGM_INT_CODE_HFP_SIGNIFICANCE 0x0e 181 #define PGM_INT_CODE_HFP_DIVIDE 0x0f 182 #define PGM_INT_CODE_SEGMENT_TRANSLATION 0x10 183 #define PGM_INT_CODE_PAGE_TRANSLATION 0x11 184 #define PGM_INT_CODE_TRANSLATION_SPEC 0x12 185 #define PGM_INT_CODE_SPECIAL_OPERATION 0x13 186 #define PGM_INT_CODE_OPERAND 0x15 187 #define PGM_INT_CODE_TRACE_TABLE 0x16 188 #define PGM_INT_CODE_VECTOR_PROCESSING 0x1b 189 #define PGM_INT_CODE_SPACE_SWITCH_EVENT 0x1c 190 #define PGM_INT_CODE_HFP_SQUARE_ROOT 0x1d 191 #define PGM_INT_CODE_PC_TRANSLATION_SPEC 0x1f 192 #define PGM_INT_CODE_AFX_TRANSLATION 0x20 193 #define PGM_INT_CODE_ASX_TRANSLATION 0x21 194 #define PGM_INT_CODE_LX_TRANSLATION 0x22 195 #define PGM_INT_CODE_EX_TRANSLATION 0x23 196 #define PGM_INT_CODE_PRIMARY_AUTHORITY 0x24 197 #define PGM_INT_CODE_SECONDARY_AUTHORITY 0x25 198 #define PGM_INT_CODE_LFX_TRANSLATION 0x26 199 #define PGM_INT_CODE_LSX_TRANSLATION 0x27 200 #define PGM_INT_CODE_ALET_SPECIFICATION 0x28 201 #define PGM_INT_CODE_ALEN_TRANSLATION 0x29 202 #define PGM_INT_CODE_ALE_SEQUENCE 0x2a 203 #define PGM_INT_CODE_ASTE_VALIDITY 0x2b 204 #define PGM_INT_CODE_ASTE_SEQUENCE 0x2c 205 #define PGM_INT_CODE_EXTENDED_AUTHORITY 0x2d 206 #define PGM_INT_CODE_LSTE_SEQUENCE 0x2e 207 #define PGM_INT_CODE_ASTE_INSTANCE 0x2f 208 #define PGM_INT_CODE_STACK_FULL 0x30 209 #define PGM_INT_CODE_STACK_EMPTY 0x31 210 #define PGM_INT_CODE_STACK_SPECIFICATION 0x32 211 #define PGM_INT_CODE_STACK_TYPE 0x33 212 #define PGM_INT_CODE_STACK_OPERATION 0x34 213 #define PGM_INT_CODE_ASCE_TYPE 0x38 214 #define PGM_INT_CODE_REGION_FIRST_TRANS 0x39 215 #define PGM_INT_CODE_REGION_SECOND_TRANS 0x3a 216 #define PGM_INT_CODE_REGION_THIRD_TRANS 0x3b 217 #define PGM_INT_CODE_SECURE_STOR_ACCESS 0x3d 218 #define PGM_INT_CODE_NON_SECURE_STOR_ACCESS 0x3e 219 #define PGM_INT_CODE_SECURE_STOR_VIOLATION 0x3f 220 #define PGM_INT_CODE_MONITOR_EVENT 0x40 221 #define PGM_INT_CODE_PER 0x80 222 #define PGM_INT_CODE_CRYPTO_OPERATION 0x119 223 #define PGM_INT_CODE_TX_ABORTED_EVENT 0x200 224 225 struct cpuid { 226 uint64_t version : 8; 227 uint64_t id : 24; 228 uint64_t type : 16; 229 uint64_t format : 1; 230 uint64_t reserved : 15; 231 }; 232 233 #define SVC_LEAVE_PSTATE 1 234 235 static inline unsigned short stap(void) 236 { 237 unsigned short cpu_address; 238 239 asm volatile("stap %0" : "=Q" (cpu_address)); 240 return cpu_address; 241 } 242 243 static inline uint64_t stidp(void) 244 { 245 uint64_t cpuid; 246 247 asm volatile("stidp %0" : "=Q" (cpuid)); 248 249 return cpuid; 250 } 251 252 enum tprot_permission { 253 TPROT_READ_WRITE = 0, 254 TPROT_READ = 1, 255 TPROT_RW_PROTECTED = 2, 256 TPROT_TRANSL_UNAVAIL = 3, 257 }; 258 259 static inline enum tprot_permission tprot(unsigned long addr, char access_key) 260 { 261 int cc; 262 263 asm volatile( 264 " tprot 0(%1),0(%2)\n" 265 " ipm %0\n" 266 " srl %0,28\n" 267 : "=d" (cc) : "a" (addr), "a" (access_key << 4) : "cc"); 268 return (enum tprot_permission)cc; 269 } 270 271 static inline void lctlg(int cr, uint64_t value) 272 { 273 asm volatile( 274 " lctlg %1,%1,%0\n" 275 : : "Q" (value), "i" (cr)); 276 } 277 278 static inline uint64_t stctg(int cr) 279 { 280 uint64_t value; 281 282 asm volatile( 283 " stctg %1,%1,%0\n" 284 : "=Q" (value) : "i" (cr) : "memory"); 285 return value; 286 } 287 288 static inline void ctl_set_bit(int cr, unsigned int bit) 289 { 290 uint64_t reg; 291 292 reg = stctg(cr); 293 reg |= 1UL << bit; 294 lctlg(cr, reg); 295 } 296 297 static inline void ctl_clear_bit(int cr, unsigned int bit) 298 { 299 uint64_t reg; 300 301 reg = stctg(cr); 302 reg &= ~(1UL << bit); 303 lctlg(cr, reg); 304 } 305 306 static inline uint64_t extract_psw_mask(void) 307 { 308 uint32_t mask_upper = 0, mask_lower = 0; 309 310 asm volatile( 311 " epsw %0,%1\n" 312 : "=r" (mask_upper), "=a" (mask_lower)); 313 314 return (uint64_t) mask_upper << 32 | mask_lower; 315 } 316 317 static inline void load_psw_mask(uint64_t mask) 318 { 319 struct psw psw = { 320 .mask = mask, 321 .addr = 0, 322 }; 323 uint64_t tmp = 0; 324 325 asm volatile( 326 " larl %0,0f\n" 327 " stg %0,8(%1)\n" 328 " lpswe 0(%1)\n" 329 "0:\n" 330 : "+r" (tmp) : "a" (&psw) : "memory", "cc" ); 331 } 332 333 /** 334 * psw_mask_clear_bits - clears bits from the current PSW mask 335 * @clear: bitmask of bits that will be cleared 336 */ 337 static inline void psw_mask_clear_bits(uint64_t clear) 338 { 339 load_psw_mask(extract_psw_mask() & ~clear); 340 } 341 342 /** 343 * psw_mask_set_bits - sets bits on the current PSW mask 344 * @set: bitmask of bits that will be set 345 */ 346 static inline void psw_mask_set_bits(uint64_t set) 347 { 348 load_psw_mask(extract_psw_mask() | set); 349 } 350 351 /** 352 * psw_mask_clear_and_set_bits - clears and sets bits on the current PSW mask 353 * @clear: bitmask of bits that will be cleared 354 * @set: bitmask of bits that will be set 355 * 356 * The bits in the @clear mask will be cleared, then the bits in the @set mask 357 * will be set. 358 */ 359 static inline void psw_mask_clear_and_set_bits(uint64_t clear, uint64_t set) 360 { 361 load_psw_mask((extract_psw_mask() & ~clear) | set); 362 } 363 364 /** 365 * enable_dat - enable the DAT bit in the current PSW 366 */ 367 static inline void enable_dat(void) 368 { 369 psw_mask_set_bits(PSW_MASK_DAT); 370 } 371 372 /** 373 * disable_dat - disable the DAT bit in the current PSW 374 */ 375 static inline void disable_dat(void) 376 { 377 psw_mask_clear_bits(PSW_MASK_DAT); 378 } 379 380 static inline void wait_for_interrupt(uint64_t irq_mask) 381 { 382 uint64_t psw_mask = extract_psw_mask(); 383 384 load_psw_mask(psw_mask | irq_mask | PSW_MASK_WAIT); 385 /* 386 * After being woken and having processed the interrupt, let's restore 387 * the PSW mask. 388 */ 389 load_psw_mask(psw_mask); 390 } 391 392 static inline void enter_pstate(void) 393 { 394 psw_mask_set_bits(PSW_MASK_PSTATE); 395 } 396 397 static inline void leave_pstate(void) 398 { 399 asm volatile(" svc %0\n" : : "i" (SVC_LEAVE_PSTATE)); 400 } 401 402 static inline int stsi(void *addr, int fc, int sel1, int sel2) 403 { 404 register int r0 asm("0") = (fc << 28) | sel1; 405 register int r1 asm("1") = sel2; 406 int cc; 407 408 asm volatile( 409 "stsi 0(%3)\n" 410 "ipm %[cc]\n" 411 "srl %[cc],28\n" 412 : "+d" (r0), [cc] "=d" (cc) 413 : "d" (r1), "a" (addr) 414 : "cc", "memory"); 415 return cc; 416 } 417 418 static inline unsigned long stsi_get_fc(void) 419 { 420 register unsigned long r0 asm("0") = 0; 421 register unsigned long r1 asm("1") = 0; 422 int cc; 423 424 asm volatile("stsi 0\n" 425 "ipm %[cc]\n" 426 "srl %[cc],28\n" 427 : "+d" (r0), [cc] "=d" (cc) 428 : "d" (r1) 429 : "cc", "memory"); 430 assert(!cc); 431 return r0 >> 28; 432 } 433 434 static inline int servc(uint32_t command, unsigned long sccb) 435 { 436 int cc; 437 438 asm volatile( 439 " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */ 440 " ipm %0\n" 441 " srl %0,28" 442 : "=&d" (cc) : "d" (command), "a" (sccb) 443 : "cc", "memory"); 444 return cc; 445 } 446 447 static inline void set_prefix(uint32_t new_prefix) 448 { 449 asm volatile(" spx %0" : : "Q" (new_prefix) : "memory"); 450 } 451 452 static inline uint32_t get_prefix(void) 453 { 454 uint32_t current_prefix; 455 456 asm volatile(" stpx %0" : "=Q" (current_prefix)); 457 return current_prefix; 458 } 459 460 #endif 461