16842bc34SLaurent Vivier #ifndef _ASMPOWERPC_PROCESSOR_H_ 26842bc34SLaurent Vivier #define _ASMPOWERPC_PROCESSOR_H_ 36842bc34SLaurent Vivier 4f4d8d939SSuraj Jitindar Singh #include <libcflat.h> 56842bc34SLaurent Vivier #include <asm/ptrace.h> 66842bc34SLaurent Vivier 76842bc34SLaurent Vivier #ifndef __ASSEMBLY__ 86842bc34SLaurent Vivier void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *); 96842bc34SLaurent Vivier void do_handle_exception(struct pt_regs *regs); 106842bc34SLaurent Vivier #endif /* __ASSEMBLY__ */ 116842bc34SLaurent Vivier 12*875ebbc7SNicholas Piggin #define SPR_TB 0x10c 13*875ebbc7SNicholas Piggin #define SPR_SPRG0 0x110 14*875ebbc7SNicholas Piggin #define SPR_SPRG1 0x111 15*875ebbc7SNicholas Piggin #define SPR_SPRG2 0x112 16*875ebbc7SNicholas Piggin #define SPR_SPRG3 0x113 17*875ebbc7SNicholas Piggin 18*875ebbc7SNicholas Piggin static inline uint64_t mfspr(int nr) 19*875ebbc7SNicholas Piggin { 20*875ebbc7SNicholas Piggin uint64_t ret; 21*875ebbc7SNicholas Piggin 22*875ebbc7SNicholas Piggin asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr) : "memory"); 23*875ebbc7SNicholas Piggin 24*875ebbc7SNicholas Piggin return ret; 25*875ebbc7SNicholas Piggin } 26*875ebbc7SNicholas Piggin 27*875ebbc7SNicholas Piggin static inline void mtspr(int nr, uint64_t val) 28*875ebbc7SNicholas Piggin { 29*875ebbc7SNicholas Piggin asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val) : "memory"); 30*875ebbc7SNicholas Piggin } 31*875ebbc7SNicholas Piggin 32*875ebbc7SNicholas Piggin static inline uint64_t mfmsr(void) 33*875ebbc7SNicholas Piggin { 34*875ebbc7SNicholas Piggin uint64_t msr; 35*875ebbc7SNicholas Piggin 36*875ebbc7SNicholas Piggin asm volatile ("mfmsr %[msr]" : [msr] "=r" (msr) :: "memory"); 37*875ebbc7SNicholas Piggin 38*875ebbc7SNicholas Piggin return msr; 39*875ebbc7SNicholas Piggin } 40*875ebbc7SNicholas Piggin 41*875ebbc7SNicholas Piggin static inline void mtmsr(uint64_t msr) 42*875ebbc7SNicholas Piggin { 43*875ebbc7SNicholas Piggin asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory"); 44*875ebbc7SNicholas Piggin } 45*875ebbc7SNicholas Piggin 46f4d8d939SSuraj Jitindar Singh static inline uint64_t get_tb(void) 47f4d8d939SSuraj Jitindar Singh { 48*875ebbc7SNicholas Piggin return mfspr(SPR_TB); 49f4d8d939SSuraj Jitindar Singh } 50f4d8d939SSuraj Jitindar Singh 51f4d8d939SSuraj Jitindar Singh extern void delay(uint64_t cycles); 52f4d8d939SSuraj Jitindar Singh extern void udelay(uint64_t us); 53ba33a96fSNicholas Piggin extern void sleep_tb(uint64_t cycles); 54ba33a96fSNicholas Piggin extern void usleep(uint64_t us); 55f4d8d939SSuraj Jitindar Singh 56f4d8d939SSuraj Jitindar Singh static inline void mdelay(uint64_t ms) 57f4d8d939SSuraj Jitindar Singh { 58f4d8d939SSuraj Jitindar Singh while (ms--) 59f4d8d939SSuraj Jitindar Singh udelay(1000); 60f4d8d939SSuraj Jitindar Singh } 61f4d8d939SSuraj Jitindar Singh 62ba33a96fSNicholas Piggin static inline void msleep(uint64_t ms) 63ba33a96fSNicholas Piggin { 64ba33a96fSNicholas Piggin usleep(ms * 1000); 65ba33a96fSNicholas Piggin } 66ba33a96fSNicholas Piggin 676842bc34SLaurent Vivier #endif /* _ASMPOWERPC_PROCESSOR_H_ */ 68