xref: /kvm-unit-tests/lib/linux/psci.h (revision f3bd1e054a97c65c4be2905b3c984d250437ba29)
1*f3bd1e05SAndrew Jones /*
2*f3bd1e05SAndrew Jones  * ARM Power State and Coordination Interface (PSCI) header
3*f3bd1e05SAndrew Jones  *
4*f3bd1e05SAndrew Jones  * This header holds common PSCI defines and macros shared
5*f3bd1e05SAndrew Jones  * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space.
6*f3bd1e05SAndrew Jones  *
7*f3bd1e05SAndrew Jones  * Copyright (C) 2014 Linaro Ltd.
8*f3bd1e05SAndrew Jones  * Author: Anup Patel <anup.patel@linaro.org>
9*f3bd1e05SAndrew Jones  */
10*f3bd1e05SAndrew Jones 
11*f3bd1e05SAndrew Jones #ifndef _UAPI_LINUX_PSCI_H
12*f3bd1e05SAndrew Jones #define _UAPI_LINUX_PSCI_H
13*f3bd1e05SAndrew Jones 
14*f3bd1e05SAndrew Jones /*
15*f3bd1e05SAndrew Jones  * PSCI v0.1 interface
16*f3bd1e05SAndrew Jones  *
17*f3bd1e05SAndrew Jones  * The PSCI v0.1 function numbers are implementation defined.
18*f3bd1e05SAndrew Jones  *
19*f3bd1e05SAndrew Jones  * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
20*f3bd1e05SAndrew Jones  * INVALID_PARAMS, and DENIED defined below are applicable
21*f3bd1e05SAndrew Jones  * to PSCI v0.1.
22*f3bd1e05SAndrew Jones  */
23*f3bd1e05SAndrew Jones 
24*f3bd1e05SAndrew Jones /* PSCI v0.2 interface */
25*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_BASE			0x84000000
26*f3bd1e05SAndrew Jones #define PSCI_0_2_FN(n)				(PSCI_0_2_FN_BASE + (n))
27*f3bd1e05SAndrew Jones #define PSCI_0_2_64BIT				0x40000000
28*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64_BASE			\
29*f3bd1e05SAndrew Jones 					(PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
30*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64(n)			(PSCI_0_2_FN64_BASE + (n))
31*f3bd1e05SAndrew Jones 
32*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_PSCI_VERSION		PSCI_0_2_FN(0)
33*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_CPU_SUSPEND			PSCI_0_2_FN(1)
34*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_CPU_OFF			PSCI_0_2_FN(2)
35*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_CPU_ON			PSCI_0_2_FN(3)
36*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_AFFINITY_INFO		PSCI_0_2_FN(4)
37*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_MIGRATE			PSCI_0_2_FN(5)
38*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_MIGRATE_INFO_TYPE		PSCI_0_2_FN(6)
39*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU		PSCI_0_2_FN(7)
40*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_SYSTEM_OFF			PSCI_0_2_FN(8)
41*f3bd1e05SAndrew Jones #define PSCI_0_2_FN_SYSTEM_RESET		PSCI_0_2_FN(9)
42*f3bd1e05SAndrew Jones 
43*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64_CPU_SUSPEND		PSCI_0_2_FN64(1)
44*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64_CPU_ON			PSCI_0_2_FN64(3)
45*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64_AFFINITY_INFO		PSCI_0_2_FN64(4)
46*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64_MIGRATE			PSCI_0_2_FN64(5)
47*f3bd1e05SAndrew Jones #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN64(7)
48*f3bd1e05SAndrew Jones 
49*f3bd1e05SAndrew Jones #define PSCI_1_0_FN_PSCI_FEATURES		PSCI_0_2_FN(10)
50*f3bd1e05SAndrew Jones #define PSCI_1_0_FN_SYSTEM_SUSPEND		PSCI_0_2_FN(14)
51*f3bd1e05SAndrew Jones 
52*f3bd1e05SAndrew Jones #define PSCI_1_0_FN64_SYSTEM_SUSPEND		PSCI_0_2_FN64(14)
53*f3bd1e05SAndrew Jones 
54*f3bd1e05SAndrew Jones /* PSCI v0.2 power state encoding for CPU_SUSPEND function */
55*f3bd1e05SAndrew Jones #define PSCI_0_2_POWER_STATE_ID_MASK		0xffff
56*f3bd1e05SAndrew Jones #define PSCI_0_2_POWER_STATE_ID_SHIFT		0
57*f3bd1e05SAndrew Jones #define PSCI_0_2_POWER_STATE_TYPE_SHIFT		16
58*f3bd1e05SAndrew Jones #define PSCI_0_2_POWER_STATE_TYPE_MASK		\
59*f3bd1e05SAndrew Jones 				(0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
60*f3bd1e05SAndrew Jones #define PSCI_0_2_POWER_STATE_AFFL_SHIFT		24
61*f3bd1e05SAndrew Jones #define PSCI_0_2_POWER_STATE_AFFL_MASK		\
62*f3bd1e05SAndrew Jones 				(0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
63*f3bd1e05SAndrew Jones 
64*f3bd1e05SAndrew Jones /* PSCI extended power state encoding for CPU_SUSPEND function */
65*f3bd1e05SAndrew Jones #define PSCI_1_0_EXT_POWER_STATE_ID_MASK	0xfffffff
66*f3bd1e05SAndrew Jones #define PSCI_1_0_EXT_POWER_STATE_ID_SHIFT	0
67*f3bd1e05SAndrew Jones #define PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT	30
68*f3bd1e05SAndrew Jones #define PSCI_1_0_EXT_POWER_STATE_TYPE_MASK	\
69*f3bd1e05SAndrew Jones 				(0x1 << PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT)
70*f3bd1e05SAndrew Jones 
71*f3bd1e05SAndrew Jones /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
72*f3bd1e05SAndrew Jones #define PSCI_0_2_AFFINITY_LEVEL_ON		0
73*f3bd1e05SAndrew Jones #define PSCI_0_2_AFFINITY_LEVEL_OFF		1
74*f3bd1e05SAndrew Jones #define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING	2
75*f3bd1e05SAndrew Jones 
76*f3bd1e05SAndrew Jones /* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
77*f3bd1e05SAndrew Jones #define PSCI_0_2_TOS_UP_MIGRATE			0
78*f3bd1e05SAndrew Jones #define PSCI_0_2_TOS_UP_NO_MIGRATE		1
79*f3bd1e05SAndrew Jones #define PSCI_0_2_TOS_MP				2
80*f3bd1e05SAndrew Jones 
81*f3bd1e05SAndrew Jones /* PSCI version decoding (independent of PSCI version) */
82*f3bd1e05SAndrew Jones #define PSCI_VERSION_MAJOR_SHIFT		16
83*f3bd1e05SAndrew Jones #define PSCI_VERSION_MINOR_MASK			\
84*f3bd1e05SAndrew Jones 		((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
85*f3bd1e05SAndrew Jones #define PSCI_VERSION_MAJOR_MASK			~PSCI_VERSION_MINOR_MASK
86*f3bd1e05SAndrew Jones #define PSCI_VERSION_MAJOR(ver)			\
87*f3bd1e05SAndrew Jones 		(((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
88*f3bd1e05SAndrew Jones #define PSCI_VERSION_MINOR(ver)			\
89*f3bd1e05SAndrew Jones 		((ver) & PSCI_VERSION_MINOR_MASK)
90*f3bd1e05SAndrew Jones 
91*f3bd1e05SAndrew Jones /* PSCI features decoding (>=1.0) */
92*f3bd1e05SAndrew Jones #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT	1
93*f3bd1e05SAndrew Jones #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK	\
94*f3bd1e05SAndrew Jones 			(0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT)
95*f3bd1e05SAndrew Jones 
96*f3bd1e05SAndrew Jones /* PSCI return values (inclusive of all PSCI versions) */
97*f3bd1e05SAndrew Jones #define PSCI_RET_SUCCESS			0
98*f3bd1e05SAndrew Jones #define PSCI_RET_NOT_SUPPORTED			-1
99*f3bd1e05SAndrew Jones #define PSCI_RET_INVALID_PARAMS			-2
100*f3bd1e05SAndrew Jones #define PSCI_RET_DENIED				-3
101*f3bd1e05SAndrew Jones #define PSCI_RET_ALREADY_ON			-4
102*f3bd1e05SAndrew Jones #define PSCI_RET_ON_PENDING			-5
103*f3bd1e05SAndrew Jones #define PSCI_RET_INTERNAL_FAILURE		-6
104*f3bd1e05SAndrew Jones #define PSCI_RET_NOT_PRESENT			-7
105*f3bd1e05SAndrew Jones #define PSCI_RET_DISABLED			-8
106*f3bd1e05SAndrew Jones #define PSCI_RET_INVALID_ADDRESS		-9
107*f3bd1e05SAndrew Jones 
108*f3bd1e05SAndrew Jones #endif /* _UAPI_LINUX_PSCI_H */
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