1 /* 2 * processor control and status functions 3 * 4 * Copyright (C) 2014, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #include <libcflat.h> 9 #include <asm/ptrace.h> 10 #include <asm/processor.h> 11 #include <asm/thread_info.h> 12 13 static const char *vector_names[] = { 14 "el1t_sync", 15 "el1t_irq", 16 "el1t_fiq", 17 "el1t_error", 18 "el1h_sync", 19 "el1h_irq", 20 "el1h_fiq", 21 "el1h_error", 22 "el0_sync_64", 23 "el0_irq_64", 24 "el0_fiq_64", 25 "el0_error_64", 26 "el0_sync_32", 27 "el0_irq_32", 28 "el0_fiq_32", 29 "el0_error_32", 30 }; 31 32 static const char *ec_names[EC_MAX] = { 33 [ESR_EL1_EC_UNKNOWN] = "UNKNOWN", 34 [ESR_EL1_EC_WFI] = "WFI", 35 [ESR_EL1_EC_CP15_32] = "CP15_32", 36 [ESR_EL1_EC_CP15_64] = "CP15_64", 37 [ESR_EL1_EC_CP14_MR] = "CP14_MR", 38 [ESR_EL1_EC_CP14_LS] = "CP14_LS", 39 [ESR_EL1_EC_FP_ASIMD] = "FP_ASMID", 40 [ESR_EL1_EC_CP10_ID] = "CP10_ID", 41 [ESR_EL1_EC_CP14_64] = "CP14_64", 42 [ESR_EL1_EC_ILL_ISS] = "ILL_ISS", 43 [ESR_EL1_EC_SVC32] = "SVC32", 44 [ESR_EL1_EC_SVC64] = "SVC64", 45 [ESR_EL1_EC_SYS64] = "SYS64", 46 [ESR_EL1_EC_IABT_EL0] = "IABT_EL0", 47 [ESR_EL1_EC_IABT_EL1] = "IABT_EL1", 48 [ESR_EL1_EC_PC_ALIGN] = "PC_ALIGN", 49 [ESR_EL1_EC_DABT_EL0] = "DABT_EL0", 50 [ESR_EL1_EC_DABT_EL1] = "DABT_EL1", 51 [ESR_EL1_EC_SP_ALIGN] = "SP_ALIGN", 52 [ESR_EL1_EC_FP_EXC32] = "FP_EXC32", 53 [ESR_EL1_EC_FP_EXC64] = "FP_EXC64", 54 [ESR_EL1_EC_SERROR] = "SERROR", 55 [ESR_EL1_EC_BREAKPT_EL0] = "BREAKPT_EL0", 56 [ESR_EL1_EC_BREAKPT_EL1] = "BREAKPT_EL1", 57 [ESR_EL1_EC_SOFTSTP_EL0] = "SOFTSTP_EL0", 58 [ESR_EL1_EC_SOFTSTP_EL1] = "SOFTSTP_EL1", 59 [ESR_EL1_EC_WATCHPT_EL0] = "WATCHPT_EL0", 60 [ESR_EL1_EC_WATCHPT_EL1] = "WATCHPT_EL1", 61 [ESR_EL1_EC_BKPT32] = "BKPT32", 62 [ESR_EL1_EC_BRK64] = "BRK64", 63 }; 64 65 void show_regs(struct pt_regs *regs) 66 { 67 int i; 68 69 printf("pc : [<%016lx>] lr : [<%016lx>] pstate: %08lx\n", 70 regs->pc, regs->regs[30], regs->pstate); 71 printf("sp : %016lx\n", regs->sp); 72 73 for (i = 29; i >= 0; --i) { 74 printf("x%-2d: %016lx ", i, regs->regs[i]); 75 if (i % 2 == 0) 76 printf("\n"); 77 } 78 printf("\n"); 79 } 80 81 bool get_far(unsigned int esr, unsigned long *far) 82 { 83 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 84 85 asm volatile("mrs %0, far_el1": "=r" (*far)); 86 87 switch (ec) { 88 case ESR_EL1_EC_IABT_EL0: 89 case ESR_EL1_EC_IABT_EL1: 90 case ESR_EL1_EC_PC_ALIGN: 91 case ESR_EL1_EC_DABT_EL0: 92 case ESR_EL1_EC_DABT_EL1: 93 case ESR_EL1_EC_WATCHPT_EL0: 94 case ESR_EL1_EC_WATCHPT_EL1: 95 if ((esr & 0x3f /* DFSC */) != 0x10 96 || !(esr & 0x400 /* FnV */)) 97 return true; 98 } 99 return false; 100 } 101 102 extern unsigned long _text; 103 104 static void bad_exception(enum vector v, struct pt_regs *regs, 105 unsigned int esr, bool esr_valid, bool bad_vector) 106 { 107 unsigned long far; 108 bool far_valid = get_far(esr, &far); 109 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 110 uintptr_t text = (uintptr_t)&_text; 111 112 printf("Load address: %" PRIxPTR "\n", text); 113 printf("PC: %" PRIxPTR " PC offset: %" PRIxPTR "\n", 114 (uintptr_t)regs->pc, (uintptr_t)regs->pc - text); 115 116 if (bad_vector) { 117 if (v < VECTOR_MAX) 118 printf("Unhandled vector %d (%s)\n", v, 119 vector_names[v]); 120 else 121 printf("Got bad vector=%d\n", v); 122 } else if (esr_valid) { 123 if (ec_names[ec]) 124 printf("Unhandled exception ec=%#x (%s)\n", ec, 125 ec_names[ec]); 126 else 127 printf("Got bad ec=%#x\n", ec); 128 } 129 130 printf("Vector: %d (%s)\n", v, vector_names[v]); 131 printf("ESR_EL1: %8s%08x, ec=%#x (%s)\n", "", esr, ec, ec_names[ec]); 132 printf("FAR_EL1: %016lx (%svalid)\n", far, far_valid ? "" : "not "); 133 printf("Exception frame registers:\n"); 134 show_regs(regs); 135 abort(); 136 } 137 138 void install_exception_handler(enum vector v, unsigned int ec, exception_fn fn) 139 { 140 struct thread_info *ti = current_thread_info(); 141 142 if (v < VECTOR_MAX && ec < EC_MAX) 143 ti->exception_handlers[v][ec] = fn; 144 } 145 146 void install_irq_handler(enum vector v, irq_handler_fn fn) 147 { 148 struct thread_info *ti = current_thread_info(); 149 150 if (v < VECTOR_MAX) 151 ti->exception_handlers[v][0] = (exception_fn)fn; 152 } 153 154 void default_vector_sync_handler(enum vector v, struct pt_regs *regs, 155 unsigned int esr) 156 { 157 struct thread_info *ti = thread_info_sp(regs->sp); 158 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 159 160 if (ti->flags & TIF_USER_MODE) { 161 if (ec < EC_MAX && ti->exception_handlers[v][ec]) { 162 ti->exception_handlers[v][ec](regs, esr); 163 return; 164 } 165 ti = current_thread_info(); 166 } 167 168 if (ec < EC_MAX && ti->exception_handlers[v][ec]) 169 ti->exception_handlers[v][ec](regs, esr); 170 else 171 bad_exception(v, regs, esr, true, false); 172 } 173 174 void default_vector_irq_handler(enum vector v, struct pt_regs *regs, 175 unsigned int esr) 176 { 177 struct thread_info *ti = thread_info_sp(regs->sp); 178 irq_handler_fn irq_handler = 179 (irq_handler_fn)ti->exception_handlers[v][0]; 180 181 if (ti->flags & TIF_USER_MODE) { 182 if (irq_handler) { 183 irq_handler(regs); 184 return; 185 } 186 ti = current_thread_info(); 187 irq_handler = (irq_handler_fn)ti->exception_handlers[v][0]; 188 } 189 190 if (irq_handler) 191 irq_handler(regs); 192 else 193 bad_exception(v, regs, esr, false, false); 194 } 195 196 void vector_handlers_default_init(vector_fn *handlers) 197 { 198 handlers[EL1H_SYNC] = default_vector_sync_handler; 199 handlers[EL1H_IRQ] = default_vector_irq_handler; 200 handlers[EL0_SYNC_64] = default_vector_sync_handler; 201 handlers[EL0_IRQ_64] = default_vector_irq_handler; 202 } 203 204 /* Needed to compile with -Wmissing-prototypes */ 205 void do_handle_exception(enum vector v, struct pt_regs *regs, unsigned int esr); 206 207 void do_handle_exception(enum vector v, struct pt_regs *regs, unsigned int esr) 208 { 209 struct thread_info *ti = thread_info_sp(regs->sp); 210 211 if (ti->flags & TIF_USER_MODE) { 212 if (v < VECTOR_MAX && ti->vector_handlers[v]) { 213 ti->vector_handlers[v](v, regs, esr); 214 return; 215 } 216 ti = current_thread_info(); 217 } 218 219 if (v < VECTOR_MAX && ti->vector_handlers[v]) 220 ti->vector_handlers[v](v, regs, esr); 221 else 222 bad_exception(v, regs, esr, true, true); 223 } 224 225 void install_vector_handler(enum vector v, vector_fn fn) 226 { 227 struct thread_info *ti = current_thread_info(); 228 229 if (v < VECTOR_MAX) 230 ti->vector_handlers[v] = fn; 231 } 232 233 static void __thread_info_init(struct thread_info *ti, unsigned int flags) 234 { 235 memset(ti, 0, sizeof(struct thread_info)); 236 ti->cpu = mpidr_to_cpu(get_mpidr()); 237 ti->flags = flags; 238 } 239 240 void thread_info_init(struct thread_info *ti, unsigned int flags) 241 { 242 __thread_info_init(ti, flags); 243 vector_handlers_default_init(ti->vector_handlers); 244 } 245 246 void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr) 247 { 248 sp_usr &= (~15UL); /* stack ptr needs 16-byte alignment */ 249 250 __thread_info_init(thread_info_sp(sp_usr), TIF_USER_MODE); 251 thread_info_sp(sp_usr)->pgtable = current_thread_info()->pgtable; 252 253 asm volatile( 254 "mov x0, %0\n" 255 "msr sp_el0, %1\n" 256 "msr elr_el1, %2\n" 257 "mov x3, xzr\n" /* clear and "set" PSR_MODE_EL0t */ 258 "msr spsr_el1, x3\n" 259 "eret\n" 260 :: "r" (arg), "r" (sp_usr), "r" (func) : "x0", "x3"); 261 } 262 263 bool is_user(void) 264 { 265 return current_thread_info()->flags & TIF_USER_MODE; 266 } 267 268 bool __mmu_enabled(void) 269 { 270 return read_sysreg(sctlr_el1) & SCTLR_EL1_M; 271 } 272