1 /* 2 * processor control and status functions 3 * 4 * Copyright (C) 2014, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #include <libcflat.h> 9 #include <asm/ptrace.h> 10 #include <asm/processor.h> 11 #include <asm/esr.h> 12 #include <asm/thread_info.h> 13 14 static const char *vector_names[] = { 15 "el1t_sync", 16 "el1t_irq", 17 "el1t_fiq", 18 "el1t_error", 19 "el1h_sync", 20 "el1h_irq", 21 "el1h_fiq", 22 "el1h_error", 23 "el0_sync_64", 24 "el0_irq_64", 25 "el0_fiq_64", 26 "el0_error_64", 27 "el0_sync_32", 28 "el0_irq_32", 29 "el0_fiq_32", 30 "el0_error_32", 31 }; 32 33 static const char *ec_names[EC_MAX] = { 34 [ESR_EL1_EC_UNKNOWN] = "UNKNOWN", 35 [ESR_EL1_EC_WFI] = "WFI", 36 [ESR_EL1_EC_CP15_32] = "CP15_32", 37 [ESR_EL1_EC_CP15_64] = "CP15_64", 38 [ESR_EL1_EC_CP14_MR] = "CP14_MR", 39 [ESR_EL1_EC_CP14_LS] = "CP14_LS", 40 [ESR_EL1_EC_FP_ASIMD] = "FP_ASMID", 41 [ESR_EL1_EC_CP10_ID] = "CP10_ID", 42 [ESR_EL1_EC_CP14_64] = "CP14_64", 43 [ESR_EL1_EC_ILL_ISS] = "ILL_ISS", 44 [ESR_EL1_EC_SVC32] = "SVC32", 45 [ESR_EL1_EC_SVC64] = "SVC64", 46 [ESR_EL1_EC_SYS64] = "SYS64", 47 [ESR_EL1_EC_IABT_EL0] = "IABT_EL0", 48 [ESR_EL1_EC_IABT_EL1] = "IABT_EL1", 49 [ESR_EL1_EC_PC_ALIGN] = "PC_ALIGN", 50 [ESR_EL1_EC_DABT_EL0] = "DABT_EL0", 51 [ESR_EL1_EC_DABT_EL1] = "DABT_EL1", 52 [ESR_EL1_EC_SP_ALIGN] = "SP_ALIGN", 53 [ESR_EL1_EC_FP_EXC32] = "FP_EXC32", 54 [ESR_EL1_EC_FP_EXC64] = "FP_EXC64", 55 [ESR_EL1_EC_SERROR] = "SERROR", 56 [ESR_EL1_EC_BREAKPT_EL0] = "BREAKPT_EL0", 57 [ESR_EL1_EC_BREAKPT_EL1] = "BREAKPT_EL1", 58 [ESR_EL1_EC_SOFTSTP_EL0] = "SOFTSTP_EL0", 59 [ESR_EL1_EC_SOFTSTP_EL1] = "SOFTSTP_EL1", 60 [ESR_EL1_EC_WATCHPT_EL0] = "WATCHPT_EL0", 61 [ESR_EL1_EC_WATCHPT_EL1] = "WATCHPT_EL1", 62 [ESR_EL1_EC_BKPT32] = "BKPT32", 63 [ESR_EL1_EC_BRK64] = "BRK64", 64 }; 65 66 void show_regs(struct pt_regs *regs) 67 { 68 int i; 69 70 printf("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", 71 regs->pc, regs->regs[30], regs->pstate); 72 printf("sp : %016llx\n", regs->sp); 73 74 for (i = 29; i >= 0; --i) { 75 printf("x%-2d: %016llx ", i, regs->regs[i]); 76 if (i % 2 == 0) 77 printf("\n"); 78 } 79 printf("\n"); 80 } 81 82 bool get_far(unsigned int esr, unsigned long *far) 83 { 84 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 85 86 asm volatile("mrs %0, far_el1": "=r" (*far)); 87 88 switch (ec) { 89 case ESR_EL1_EC_IABT_EL0: 90 case ESR_EL1_EC_IABT_EL1: 91 case ESR_EL1_EC_PC_ALIGN: 92 case ESR_EL1_EC_DABT_EL0: 93 case ESR_EL1_EC_DABT_EL1: 94 case ESR_EL1_EC_WATCHPT_EL0: 95 case ESR_EL1_EC_WATCHPT_EL1: 96 if ((esr & 0x3f /* DFSC */) != 0x10 97 || !(esr & 0x400 /* FnV */)) 98 return true; 99 } 100 return false; 101 } 102 103 static void bad_exception(enum vector v, struct pt_regs *regs, 104 unsigned int esr, bool esr_valid, bool bad_vector) 105 { 106 unsigned long far; 107 bool far_valid = get_far(esr, &far); 108 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 109 110 if (bad_vector) { 111 if (v < VECTOR_MAX) 112 printf("Unhandled vector %d (%s)\n", v, 113 vector_names[v]); 114 else 115 printf("Got bad vector=%d\n", v); 116 } else if (esr_valid) { 117 if (ec_names[ec]) 118 printf("Unhandled exception ec=0x%x (%s)\n", ec, 119 ec_names[ec]); 120 else 121 printf("Got bad ec=0x%x\n", ec); 122 } 123 124 printf("Vector: %d (%s)\n", v, vector_names[v]); 125 printf("ESR_EL1: %8s%08lx, ec=0x%x (%s)\n", "", esr, ec, ec_names[ec]); 126 printf("FAR_EL1: %016lx (%svalid)\n", far, far_valid ? "" : "not "); 127 printf("Exception frame registers:\n"); 128 show_regs(regs); 129 abort(); 130 } 131 132 void install_exception_handler(enum vector v, unsigned int ec, exception_fn fn) 133 { 134 struct thread_info *ti = current_thread_info(); 135 136 if (v < VECTOR_MAX && ec < EC_MAX) 137 ti->exception_handlers[v][ec] = fn; 138 } 139 140 void install_irq_handler(enum vector v, irq_handler_fn fn) 141 { 142 struct thread_info *ti = current_thread_info(); 143 144 if (v < VECTOR_MAX) 145 ti->exception_handlers[v][0] = (exception_fn)fn; 146 } 147 148 void default_vector_sync_handler(enum vector v, struct pt_regs *regs, 149 unsigned int esr) 150 { 151 struct thread_info *ti = thread_info_sp(regs->sp); 152 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 153 154 if (ti->flags & TIF_USER_MODE) { 155 if (ec < EC_MAX && ti->exception_handlers[v][ec]) { 156 ti->exception_handlers[v][ec](regs, esr); 157 return; 158 } 159 ti = current_thread_info(); 160 } 161 162 if (ec < EC_MAX && ti->exception_handlers[v][ec]) 163 ti->exception_handlers[v][ec](regs, esr); 164 else 165 bad_exception(v, regs, esr, true, false); 166 } 167 168 void default_vector_irq_handler(enum vector v, struct pt_regs *regs, 169 unsigned int esr) 170 { 171 struct thread_info *ti = thread_info_sp(regs->sp); 172 irq_handler_fn irq_handler = 173 (irq_handler_fn)ti->exception_handlers[v][0]; 174 175 if (ti->flags & TIF_USER_MODE) { 176 if (irq_handler) { 177 irq_handler(regs); 178 return; 179 } 180 ti = current_thread_info(); 181 irq_handler = (irq_handler_fn)ti->exception_handlers[v][0]; 182 } 183 184 if (irq_handler) 185 irq_handler(regs); 186 else 187 bad_exception(v, regs, esr, false, false); 188 } 189 190 void vector_handlers_default_init(vector_fn *handlers) 191 { 192 handlers[EL1H_SYNC] = default_vector_sync_handler; 193 handlers[EL1H_IRQ] = default_vector_irq_handler; 194 handlers[EL0_SYNC_64] = default_vector_sync_handler; 195 handlers[EL0_IRQ_64] = default_vector_irq_handler; 196 } 197 198 void do_handle_exception(enum vector v, struct pt_regs *regs, unsigned int esr) 199 { 200 struct thread_info *ti = thread_info_sp(regs->sp); 201 202 if (ti->flags & TIF_USER_MODE) { 203 if (v < VECTOR_MAX && ti->vector_handlers[v]) { 204 ti->vector_handlers[v](v, regs, esr); 205 return; 206 } 207 ti = current_thread_info(); 208 } 209 210 if (v < VECTOR_MAX && ti->vector_handlers[v]) 211 ti->vector_handlers[v](v, regs, esr); 212 else 213 bad_exception(v, regs, esr, true, true); 214 } 215 216 void install_vector_handler(enum vector v, vector_fn fn) 217 { 218 struct thread_info *ti = current_thread_info(); 219 220 if (v < VECTOR_MAX) 221 ti->vector_handlers[v] = fn; 222 } 223 224 void thread_info_init(struct thread_info *ti, unsigned int flags) 225 { 226 memset(ti, 0, sizeof(struct thread_info)); 227 ti->cpu = mpidr_to_cpu(get_mpidr()); 228 ti->flags = flags; 229 vector_handlers_default_init(ti->vector_handlers); 230 } 231 232 void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr) 233 { 234 sp_usr &= (~15UL); /* stack ptr needs 16-byte alignment */ 235 236 thread_info_init(thread_info_sp(sp_usr), TIF_USER_MODE); 237 238 asm volatile( 239 "mov x0, %0\n" 240 "msr sp_el0, %1\n" 241 "msr elr_el1, %2\n" 242 "mov x3, xzr\n" /* clear and "set" PSR_MODE_EL0t */ 243 "msr spsr_el1, x3\n" 244 "eret\n" 245 :: "r" (arg), "r" (sp_usr), "r" (func) : "x0", "x3"); 246 } 247 248 bool is_user(void) 249 { 250 return current_thread_info()->flags & TIF_USER_MODE; 251 } 252