1 /* 2 * processor control and status functions 3 * 4 * Copyright (C) 2014, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #include <libcflat.h> 9 #include <asm/ptrace.h> 10 #include <asm/processor.h> 11 #include <asm/thread_info.h> 12 13 static const char *vector_names[] = { 14 "el1t_sync", 15 "el1t_irq", 16 "el1t_fiq", 17 "el1t_error", 18 "el1h_sync", 19 "el1h_irq", 20 "el1h_fiq", 21 "el1h_error", 22 "el0_sync_64", 23 "el0_irq_64", 24 "el0_fiq_64", 25 "el0_error_64", 26 "el0_sync_32", 27 "el0_irq_32", 28 "el0_fiq_32", 29 "el0_error_32", 30 }; 31 32 static const char *ec_names[EC_MAX] = { 33 [ESR_EL1_EC_UNKNOWN] = "UNKNOWN", 34 [ESR_EL1_EC_WFI] = "WFI", 35 [ESR_EL1_EC_CP15_32] = "CP15_32", 36 [ESR_EL1_EC_CP15_64] = "CP15_64", 37 [ESR_EL1_EC_CP14_MR] = "CP14_MR", 38 [ESR_EL1_EC_CP14_LS] = "CP14_LS", 39 [ESR_EL1_EC_FP_ASIMD] = "FP_ASMID", 40 [ESR_EL1_EC_CP10_ID] = "CP10_ID", 41 [ESR_EL1_EC_CP14_64] = "CP14_64", 42 [ESR_EL1_EC_ILL_ISS] = "ILL_ISS", 43 [ESR_EL1_EC_SVC32] = "SVC32", 44 [ESR_EL1_EC_SVC64] = "SVC64", 45 [ESR_EL1_EC_SYS64] = "SYS64", 46 [ESR_EL1_EC_IABT_EL0] = "IABT_EL0", 47 [ESR_EL1_EC_IABT_EL1] = "IABT_EL1", 48 [ESR_EL1_EC_PC_ALIGN] = "PC_ALIGN", 49 [ESR_EL1_EC_DABT_EL0] = "DABT_EL0", 50 [ESR_EL1_EC_DABT_EL1] = "DABT_EL1", 51 [ESR_EL1_EC_SP_ALIGN] = "SP_ALIGN", 52 [ESR_EL1_EC_FP_EXC32] = "FP_EXC32", 53 [ESR_EL1_EC_FP_EXC64] = "FP_EXC64", 54 [ESR_EL1_EC_SERROR] = "SERROR", 55 [ESR_EL1_EC_BREAKPT_EL0] = "BREAKPT_EL0", 56 [ESR_EL1_EC_BREAKPT_EL1] = "BREAKPT_EL1", 57 [ESR_EL1_EC_SOFTSTP_EL0] = "SOFTSTP_EL0", 58 [ESR_EL1_EC_SOFTSTP_EL1] = "SOFTSTP_EL1", 59 [ESR_EL1_EC_WATCHPT_EL0] = "WATCHPT_EL0", 60 [ESR_EL1_EC_WATCHPT_EL1] = "WATCHPT_EL1", 61 [ESR_EL1_EC_BKPT32] = "BKPT32", 62 [ESR_EL1_EC_BRK64] = "BRK64", 63 }; 64 65 void show_regs(struct pt_regs *regs) 66 { 67 int i; 68 69 printf("pc : [<%016lx>] lr : [<%016lx>] pstate: %08lx\n", 70 regs->pc, regs->regs[30], regs->pstate); 71 printf("sp : %016lx\n", regs->sp); 72 73 for (i = 29; i >= 0; --i) { 74 printf("x%-2d: %016lx ", i, regs->regs[i]); 75 if (i % 2 == 0) 76 printf("\n"); 77 } 78 printf("\n"); 79 } 80 81 bool get_far(unsigned int esr, unsigned long *far) 82 { 83 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 84 85 asm volatile("mrs %0, far_el1": "=r" (*far)); 86 87 switch (ec) { 88 case ESR_EL1_EC_IABT_EL0: 89 case ESR_EL1_EC_IABT_EL1: 90 case ESR_EL1_EC_PC_ALIGN: 91 case ESR_EL1_EC_DABT_EL0: 92 case ESR_EL1_EC_DABT_EL1: 93 case ESR_EL1_EC_WATCHPT_EL0: 94 case ESR_EL1_EC_WATCHPT_EL1: 95 if ((esr & 0x3f /* DFSC */) != 0x10 96 || !(esr & 0x400 /* FnV */)) 97 return true; 98 } 99 return false; 100 } 101 102 extern unsigned long _text; 103 104 static void bad_exception(enum vector v, struct pt_regs *regs, 105 unsigned int esr, bool esr_valid, bool bad_vector) 106 { 107 unsigned long far; 108 bool far_valid = get_far(esr, &far); 109 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 110 uintptr_t text = (uintptr_t)&_text; 111 112 printf("Load address: %" PRIxPTR "\n", text); 113 printf("PC: %" PRIxPTR " PC offset: %" PRIxPTR "\n", 114 (uintptr_t)regs->pc, (uintptr_t)regs->pc - text); 115 116 if (bad_vector) { 117 if (v < VECTOR_MAX) 118 printf("Unhandled vector %d (%s)\n", v, 119 vector_names[v]); 120 else 121 printf("Got bad vector=%d\n", v); 122 } else if (esr_valid) { 123 if (ec_names[ec]) 124 printf("Unhandled exception ec=%#x (%s)\n", ec, 125 ec_names[ec]); 126 else 127 printf("Got bad ec=%#x\n", ec); 128 } 129 130 printf("Vector: %d (%s)\n", v, vector_names[v]); 131 printf("ESR_EL1: %8s%08x, ec=%#x (%s)\n", "", esr, ec, ec_names[ec]); 132 printf("FAR_EL1: %016lx (%svalid)\n", far, far_valid ? "" : "not "); 133 dump_stack(); 134 printf("Exception frame registers:\n"); 135 show_regs(regs); 136 abort(); 137 } 138 139 void install_exception_handler(enum vector v, unsigned int ec, exception_fn fn) 140 { 141 struct thread_info *ti = current_thread_info(); 142 143 if (v < VECTOR_MAX && ec < EC_MAX) 144 ti->exception_handlers[v][ec] = fn; 145 } 146 147 void install_irq_handler(enum vector v, irq_handler_fn fn) 148 { 149 struct thread_info *ti = current_thread_info(); 150 151 if (v < VECTOR_MAX) 152 ti->exception_handlers[v][0] = (exception_fn)fn; 153 } 154 155 void default_vector_sync_handler(enum vector v, struct pt_regs *regs, 156 unsigned int esr) 157 { 158 struct thread_info *ti = thread_info_sp(regs->sp); 159 unsigned int ec = esr >> ESR_EL1_EC_SHIFT; 160 161 if (ti->flags & TIF_USER_MODE) { 162 if (ec < EC_MAX && ti->exception_handlers[v][ec]) { 163 ti->exception_handlers[v][ec](regs, esr); 164 return; 165 } 166 ti = current_thread_info(); 167 } 168 169 if (ec < EC_MAX && ti->exception_handlers[v][ec]) 170 ti->exception_handlers[v][ec](regs, esr); 171 else 172 bad_exception(v, regs, esr, true, false); 173 } 174 175 void default_vector_irq_handler(enum vector v, struct pt_regs *regs, 176 unsigned int esr) 177 { 178 struct thread_info *ti = thread_info_sp(regs->sp); 179 irq_handler_fn irq_handler = 180 (irq_handler_fn)ti->exception_handlers[v][0]; 181 182 if (ti->flags & TIF_USER_MODE) { 183 if (irq_handler) { 184 irq_handler(regs); 185 return; 186 } 187 ti = current_thread_info(); 188 irq_handler = (irq_handler_fn)ti->exception_handlers[v][0]; 189 } 190 191 if (irq_handler) 192 irq_handler(regs); 193 else 194 bad_exception(v, regs, esr, false, false); 195 } 196 197 void vector_handlers_default_init(vector_fn *handlers) 198 { 199 handlers[EL1H_SYNC] = default_vector_sync_handler; 200 handlers[EL1H_IRQ] = default_vector_irq_handler; 201 handlers[EL0_SYNC_64] = default_vector_sync_handler; 202 handlers[EL0_IRQ_64] = default_vector_irq_handler; 203 } 204 205 /* Needed to compile with -Wmissing-prototypes */ 206 void do_handle_exception(enum vector v, struct pt_regs *regs, unsigned int esr); 207 208 void do_handle_exception(enum vector v, struct pt_regs *regs, unsigned int esr) 209 { 210 struct thread_info *ti = thread_info_sp(regs->sp); 211 212 if (ti->flags & TIF_USER_MODE) { 213 if (v < VECTOR_MAX && ti->vector_handlers[v]) { 214 ti->vector_handlers[v](v, regs, esr); 215 return; 216 } 217 ti = current_thread_info(); 218 } 219 220 if (v < VECTOR_MAX && ti->vector_handlers[v]) 221 ti->vector_handlers[v](v, regs, esr); 222 else 223 bad_exception(v, regs, esr, true, true); 224 } 225 226 void install_vector_handler(enum vector v, vector_fn fn) 227 { 228 struct thread_info *ti = current_thread_info(); 229 230 if (v < VECTOR_MAX) 231 ti->vector_handlers[v] = fn; 232 } 233 234 static void __thread_info_init(struct thread_info *ti, unsigned int flags) 235 { 236 memset(ti, 0, sizeof(struct thread_info)); 237 ti->cpu = mpidr_to_cpu(get_mpidr()); 238 ti->flags = flags; 239 } 240 241 void thread_info_init(struct thread_info *ti, unsigned int flags) 242 { 243 __thread_info_init(ti, flags); 244 vector_handlers_default_init(ti->vector_handlers); 245 } 246 247 void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr) 248 { 249 sp_usr &= (~15UL); /* stack ptr needs 16-byte alignment */ 250 251 __thread_info_init(thread_info_sp(sp_usr), TIF_USER_MODE); 252 thread_info_sp(sp_usr)->pgtable = current_thread_info()->pgtable; 253 254 asm volatile( 255 "mov x0, %0\n" 256 "msr sp_el0, %1\n" 257 "msr elr_el1, %2\n" 258 "mov x3, xzr\n" /* clear and "set" PSR_MODE_EL0t */ 259 "msr spsr_el1, x3\n" 260 "eret\n" 261 :: "r" (arg), "r" (sp_usr), "r" (func) : "x0", "x3"); 262 } 263 264 bool is_user(void) 265 { 266 return current_thread_info()->flags & TIF_USER_MODE; 267 } 268 269 bool __mmu_enabled(void) 270 { 271 return read_sysreg(sctlr_el1) & SCTLR_EL1_M; 272 } 273