1 /* 2 * All ripped off from arch/arm64/include/asm/arch_gicv3.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM64_ARCH_GICV3_H_ 9 #define _ASMARM64_ARCH_GICV3_H_ 10 11 #include <asm/sysreg.h> 12 13 #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 14 #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 15 #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 16 #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 17 #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 18 19 #ifndef __ASSEMBLY__ 20 21 #include <libcflat.h> 22 #include <asm/barrier.h> 23 24 /* 25 * Low-level accessors 26 * 27 * These system registers are 32 bits, but we make sure that the compiler 28 * sets the GP register's most significant bits to 0 with an explicit cast. 29 */ 30 31 static inline void gicv3_write_pmr(u32 val) 32 { 33 asm volatile("msr_s " xstr(ICC_PMR_EL1) ", %0" : : "r" ((u64)val)); 34 } 35 36 static inline void gicv3_write_sgi1r(u64 val) 37 { 38 asm volatile("msr_s " xstr(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 39 } 40 41 static inline u32 gicv3_read_iar(void) 42 { 43 u64 irqstat; 44 asm volatile("mrs_s %0, " xstr(ICC_IAR1_EL1) : "=r" (irqstat)); 45 dsb(sy); 46 return (u64)irqstat; 47 } 48 49 static inline void gicv3_write_eoir(u32 irq) 50 { 51 asm volatile("msr_s " xstr(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq)); 52 isb(); 53 } 54 55 static inline void gicv3_write_grpen1(u32 val) 56 { 57 asm volatile("msr_s " xstr(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val)); 58 isb(); 59 } 60 61 #define gicv3_read_typer(c) readq(c) 62 63 #endif /* !__ASSEMBLY__ */ 64 #endif /* _ASMARM64_ARCH_GICV3_H_ */ 65