xref: /kvm-unit-tests/lib/arm/asm/gic.h (revision 5b70cbdb7bc2ea65096b51565c75815cc95945b8)
1 /*
2  * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
3  *
4  * This work is licensed under the terms of the GNU LGPL, version 2.
5  */
6 #ifndef _ASMARM_GIC_H_
7 #define _ASMARM_GIC_H_
8 
9 #define GIC_NR_PRIVATE_IRQS		32
10 #define GIC_FIRST_SPI			GIC_NR_PRIVATE_IRQS
11 
12 /* Distributor registers */
13 #define GICD_CTLR			0x0000
14 #define GICD_TYPER			0x0004
15 #define GICD_IIDR			0x0008
16 #define GICD_IGROUPR			0x0080
17 #define GICD_ISENABLER			0x0100
18 #define GICD_ICENABLER			0x0180
19 #define GICD_ISPENDR			0x0200
20 #define GICD_ICPENDR			0x0280
21 #define GICD_ISACTIVER			0x0300
22 #define GICD_ICACTIVER			0x0380
23 #define GICD_IPRIORITYR			0x0400
24 #define GICD_ITARGETSR			0x0800
25 #define GICD_SGIR			0x0f00
26 #define GICD_ICPIDR2			0x0fe8
27 
28 #define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)
29 #define GICD_INT_EN_SET_SGI		0x0000ffff
30 #define GICD_INT_DEF_PRI_X4		0xa0a0a0a0
31 
32 /* CPU interface registers */
33 #define GICC_CTLR			0x0000
34 #define GICC_PMR			0x0004
35 #define GICC_IAR			0x000c
36 #define GICC_EOIR			0x0010
37 
38 #define GICC_INT_PRI_THRESHOLD		0xf0
39 #define GICC_INT_SPURIOUS		0x3ff
40 
41 #include <asm/gic-v2.h>
42 #include <asm/gic-v3.h>
43 #include <asm/gic-v3-its.h>
44 
45 #define PPI(irq)			((irq) + 16)
46 #define SPI(irq)			((irq) + GIC_FIRST_SPI)
47 
48 #ifndef __ASSEMBLY__
49 #include <asm/cpumask.h>
50 
51 enum gic_irq_state {
52 	GIC_IRQ_STATE_INACTIVE,
53 	GIC_IRQ_STATE_PENDING,
54 	GIC_IRQ_STATE_ACTIVE,
55 	GIC_IRQ_STATE_ACTIVE_PENDING,
56 };
57 
58 /*
59  * gic_init will try to find all known gics, and then
60  * initialize the gic data for the one found.
61  * returns
62  *  0   : no gic was found
63  *  > 0 : the gic version of the gic found
64  */
65 extern int gic_init(void);
66 
67 /*
68  * gic_enable_defaults enables the gic with basic but useful
69  * settings. gic_enable_defaults will call gic_init if it has
70  * not yet been invoked.
71  */
72 extern void gic_enable_defaults(void);
73 
74 /*
75  * After enabling the gic with gic_enable_defaults the functions
76  * below will work with any supported gic version.
77  */
78 extern int gic_version(void);
79 extern u32 gic_read_iar(void);
80 extern u32 gic_iar_irqnr(u32 iar);
81 extern void gic_write_eoir(u32 irqstat);
82 extern void gic_ipi_send_single(int irq, int cpu);
83 extern void gic_ipi_send_mask(int irq, const cpumask_t *dest);
84 extern enum gic_irq_state gic_irq_state(int irq);
85 
86 void gic_irq_set_clr_enable(int irq, bool enable);
87 #define gic_enable_irq(irq) gic_irq_set_clr_enable(irq, true)
88 #define gic_disable_irq(irq) gic_irq_set_clr_enable(irq, false)
89 
90 #endif /* !__ASSEMBLY__ */
91 #endif /* _ASMARM_GIC_H_ */
92