xref: /kvm-unit-tests/lib/arm/asm/assembler.h (revision b5f659be4775a1c34740cd57a30217ddc760afb9)
1*b5f659beSAlexandru Elisei /* SPDX-License-Identifier: GPL-2.0 */
2*b5f659beSAlexandru Elisei /*
3*b5f659beSAlexandru Elisei  * Based on several files from Linux version v5.10: arch/arm/mm/proc-macros.S,
4*b5f659beSAlexandru Elisei  * arch/arm/mm/proc-v7.S.
5*b5f659beSAlexandru Elisei  */
6*b5f659beSAlexandru Elisei 
7*b5f659beSAlexandru Elisei #ifndef __ASSEMBLY__
8*b5f659beSAlexandru Elisei #error "Only include this from assembly code"
9*b5f659beSAlexandru Elisei #endif
10*b5f659beSAlexandru Elisei 
11*b5f659beSAlexandru Elisei #ifndef __ASM_ASSEMBLER_H
12*b5f659beSAlexandru Elisei #define __ASM_ASSEMBLER_H
13*b5f659beSAlexandru Elisei 
14*b5f659beSAlexandru Elisei /*
15*b5f659beSAlexandru Elisei  * dcache_line_size - get the minimum D-cache line size from the CTR register
16*b5f659beSAlexandru Elisei  * on ARMv7.
17*b5f659beSAlexandru Elisei  */
18*b5f659beSAlexandru Elisei 	.macro	dcache_line_size, reg, tmp
19*b5f659beSAlexandru Elisei 	mrc	p15, 0, \tmp, c0, c0, 1		// read ctr
20*b5f659beSAlexandru Elisei 	lsr	\tmp, \tmp, #16
21*b5f659beSAlexandru Elisei 	and	\tmp, \tmp, #0xf		// cache line size encoding
22*b5f659beSAlexandru Elisei 	mov	\reg, #4			// bytes per word
23*b5f659beSAlexandru Elisei 	mov	\reg, \reg, lsl \tmp		// actual cache line size
24*b5f659beSAlexandru Elisei 	.endm
25*b5f659beSAlexandru Elisei 
26*b5f659beSAlexandru Elisei /*
27*b5f659beSAlexandru Elisei  * Macro to perform a data cache maintenance for the interval
28*b5f659beSAlexandru Elisei  * [addr, addr + size).
29*b5f659beSAlexandru Elisei  *
30*b5f659beSAlexandru Elisei  * 	op:		operation to execute
31*b5f659beSAlexandru Elisei  * 	domain		domain used in the dsb instruction
32*b5f659beSAlexandru Elisei  * 	addr:		starting virtual address of the region
33*b5f659beSAlexandru Elisei  * 	size:		size of the region
34*b5f659beSAlexandru Elisei  * 	Corrupts:	addr, size, tmp1, tmp2
35*b5f659beSAlexandru Elisei  */
36*b5f659beSAlexandru Elisei 	.macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2
37*b5f659beSAlexandru Elisei 	dcache_line_size \tmp1, \tmp2
38*b5f659beSAlexandru Elisei 	add	\size, \addr, \size
39*b5f659beSAlexandru Elisei 	sub	\tmp2, \tmp1, #1
40*b5f659beSAlexandru Elisei 	bic	\addr, \addr, \tmp2
41*b5f659beSAlexandru Elisei 9998:
42*b5f659beSAlexandru Elisei 	.ifc	\op, dccimvac
43*b5f659beSAlexandru Elisei 	mcr	p15, 0, \addr, c7, c14, 1
44*b5f659beSAlexandru Elisei 	.else
45*b5f659beSAlexandru Elisei 	.err
46*b5f659beSAlexandru Elisei 	.endif
47*b5f659beSAlexandru Elisei 	add	\addr, \addr, \tmp1
48*b5f659beSAlexandru Elisei 	cmp	\addr, \size
49*b5f659beSAlexandru Elisei 	blo	9998b
50*b5f659beSAlexandru Elisei 	dsb	\domain
51*b5f659beSAlexandru Elisei 	.endm
52*b5f659beSAlexandru Elisei 
53*b5f659beSAlexandru Elisei #endif	/* __ASM_ASSEMBLER_H */
54