1 /* 2 * All ripped off from arch/arm/include/asm/arch_gicv3.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM_ARCH_GICV3_H_ 9 #define _ASMARM_ARCH_GICV3_H_ 10 11 #ifndef __ASSEMBLY__ 12 #include <libcflat.h> 13 #include <asm/sysreg.h> 14 #include <asm/barrier.h> 15 #include <asm/io.h> 16 17 #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) 18 #define ICC_SGI1R __ACCESS_CP15_64(0, c12) 19 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) 20 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) 21 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) 22 23 static inline void gicv3_write_pmr(u32 val) 24 { 25 write_sysreg(val, ICC_PMR); 26 } 27 28 static inline void gicv3_write_sgi1r(u64 val) 29 { 30 write_sysreg(val, ICC_SGI1R); 31 } 32 33 static inline u32 gicv3_read_iar(void) 34 { 35 u32 irqstat = read_sysreg(ICC_IAR1); 36 dsb(sy); 37 return irqstat; 38 } 39 40 static inline void gicv3_write_eoir(u32 irq) 41 { 42 write_sysreg(irq, ICC_EOIR1); 43 isb(); 44 } 45 46 static inline void gicv3_write_grpen1(u32 val) 47 { 48 write_sysreg(val, ICC_IGRPEN1); 49 isb(); 50 } 51 52 /* 53 * We may access GICR_TYPER and GITS_TYPER by reading both the TYPER 54 * offset and the following offset (+ 4) and then combining them to 55 * form a 64-bit address. 56 */ 57 static inline u64 gicv3_read_typer(const volatile void __iomem *addr) 58 { 59 u64 val = readl(addr); 60 val |= (u64)readl(addr + 4) << 32; 61 return val; 62 } 63 64 #endif /* !__ASSEMBLY__ */ 65 #endif /* _ASMARM_ARCH_GICV3_H_ */ 66