1 /* 2 * Test the ARM Performance Monitors Unit (PMU). 3 * 4 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 5 * Copyright (C) 2016, Red Hat Inc, Wei Huang <wei@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU Lesser General Public License version 2.1 and 9 * only version 2.1 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License 14 * for more details. 15 */ 16 #include "libcflat.h" 17 #include "errata.h" 18 #include "asm/barrier.h" 19 #include "asm/sysreg.h" 20 #include "asm/processor.h" 21 #include <bitops.h> 22 #include <asm/gic.h> 23 24 #define PMU_PMCR_E (1 << 0) 25 #define PMU_PMCR_P (1 << 1) 26 #define PMU_PMCR_C (1 << 2) 27 #define PMU_PMCR_D (1 << 3) 28 #define PMU_PMCR_X (1 << 4) 29 #define PMU_PMCR_DP (1 << 5) 30 #define PMU_PMCR_LC (1 << 6) 31 #define PMU_PMCR_LP (1 << 7) 32 #define PMU_PMCR_N_SHIFT 11 33 #define PMU_PMCR_N_MASK 0x1f 34 #define PMU_PMCR_ID_SHIFT 16 35 #define PMU_PMCR_ID_MASK 0xff 36 #define PMU_PMCR_IMP_SHIFT 24 37 #define PMU_PMCR_IMP_MASK 0xff 38 39 #define PMU_CYCLE_IDX 31 40 41 #define NR_SAMPLES 10 42 43 /* Some PMU events */ 44 #define SW_INCR 0x0 45 #define INST_RETIRED 0x8 46 #define CPU_CYCLES 0x11 47 #define MEM_ACCESS 0x13 48 #define INST_PREC 0x1B 49 #define STALL_FRONTEND 0x23 50 #define STALL_BACKEND 0x24 51 #define CHAIN 0x1E 52 53 #define COMMON_EVENTS_LOW 0x0 54 #define COMMON_EVENTS_HIGH 0x3F 55 #define EXT_COMMON_EVENTS_LOW 0x4000 56 #define EXT_COMMON_EVENTS_HIGH 0x403F 57 58 #define ALL_SET_32 0x00000000FFFFFFFFULL 59 #define ALL_CLEAR 0x0000000000000000ULL 60 #define PRE_OVERFLOW_32 0x00000000FFFFFFF0ULL 61 #define PRE_OVERFLOW2_32 0x00000000FFFFFFDCULL 62 #define PRE_OVERFLOW_64 0xFFFFFFFFFFFFFFF0ULL 63 64 #define PRE_OVERFLOW(__overflow_at_64bits) \ 65 (__overflow_at_64bits ? PRE_OVERFLOW_64 : PRE_OVERFLOW_32) 66 67 #define PMU_PPI 23 68 69 struct pmu { 70 unsigned int version; 71 unsigned int nb_implemented_counters; 72 uint32_t pmcr_ro; 73 }; 74 75 struct pmu_stats { 76 unsigned long bitmap; 77 uint32_t interrupts[32]; 78 bool unexpected; 79 }; 80 81 static struct pmu pmu; 82 83 #if defined(__arm__) 84 #define ID_DFR0_PERFMON_SHIFT 24 85 #define ID_DFR0_PERFMON_MASK 0xf 86 87 #define ID_DFR0_PMU_NOTIMPL 0b0000 88 #define ID_DFR0_PMU_V1 0b0001 89 #define ID_DFR0_PMU_V2 0b0010 90 #define ID_DFR0_PMU_V3 0b0011 91 #define ID_DFR0_PMU_V3_8_1 0b0100 92 #define ID_DFR0_PMU_V3_8_4 0b0101 93 #define ID_DFR0_PMU_V3_8_5 0b0110 94 #define ID_DFR0_PMU_IMPDEF 0b1111 95 96 #define PMCR __ACCESS_CP15(c9, 0, c12, 0) 97 #define ID_DFR0 __ACCESS_CP15(c0, 0, c1, 2) 98 #define PMSELR __ACCESS_CP15(c9, 0, c12, 5) 99 #define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1) 100 #define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1) 101 #define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2) 102 #define PMOVSR __ACCESS_CP15(c9, 0, c12, 3) 103 #define PMCCNTR32 __ACCESS_CP15(c9, 0, c13, 0) 104 #define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2) 105 #define PMCCNTR64 __ACCESS_CP15_64(0, c9) 106 107 static inline uint32_t get_id_dfr0(void) { return read_sysreg(ID_DFR0); } 108 static inline uint32_t get_pmcr(void) { return read_sysreg(PMCR); } 109 static inline void set_pmcr(uint32_t v) { write_sysreg(v, PMCR); } 110 static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, PMCNTENSET); } 111 112 static inline uint8_t get_pmu_version(void) 113 { 114 return (get_id_dfr0() >> ID_DFR0_PERFMON_SHIFT) & ID_DFR0_PERFMON_MASK; 115 } 116 117 static inline uint64_t get_pmccntr(void) 118 { 119 return read_sysreg(PMCCNTR32); 120 } 121 122 static inline void set_pmccntr(uint64_t value) 123 { 124 write_sysreg(value & 0xffffffff, PMCCNTR32); 125 } 126 127 /* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */ 128 static inline void set_pmccfiltr(uint32_t value) 129 { 130 write_sysreg(PMU_CYCLE_IDX, PMSELR); 131 write_sysreg(value, PMXEVTYPER); 132 isb(); 133 } 134 135 /* 136 * Extra instructions inserted by the compiler would be difficult to compensate 137 * for, so hand assemble everything between, and including, the PMCR accesses 138 * to start and stop counting. isb instructions were inserted to make sure 139 * pmccntr read after this function returns the exact instructions executed in 140 * the controlled block. Total instrs = isb + mcr + 2*loop = 2 + 2*loop. 141 */ 142 static inline void precise_instrs_loop(int loop, uint32_t pmcr) 143 { 144 asm volatile( 145 " mcr p15, 0, %[pmcr], c9, c12, 0\n" 146 " isb\n" 147 "1: subs %[loop], %[loop], #1\n" 148 " bgt 1b\n" 149 " mcr p15, 0, %[z], c9, c12, 0\n" 150 " isb\n" 151 : [loop] "+r" (loop) 152 : [pmcr] "r" (pmcr), [z] "r" (0) 153 : "cc"); 154 } 155 156 static void pmu_reset(void) 157 { 158 /* reset all counters, counting disabled at PMCR level*/ 159 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); 160 /* Disable all counters */ 161 write_sysreg(ALL_SET_32, PMCNTENCLR); 162 /* clear overflow reg */ 163 write_sysreg(ALL_SET_32, PMOVSR); 164 /* disable overflow interrupts on all counters */ 165 write_sysreg(ALL_SET_32, PMINTENCLR); 166 isb(); 167 } 168 169 /* event counter tests only implemented for aarch64 */ 170 static void test_event_introspection(void) {} 171 static void test_event_counter_config(void) {} 172 static void test_basic_event_count(bool overflow_at_64bits) {} 173 static void test_mem_access(bool overflow_at_64bits) {} 174 static void test_sw_incr(bool overflow_at_64bits) {} 175 static void test_chained_counters(bool unused) {} 176 static void test_chained_sw_incr(bool unused) {} 177 static void test_chain_promotion(bool unused) {} 178 static void test_overflow_interrupt(bool overflow_at_64bits) {} 179 180 #elif defined(__aarch64__) 181 #define ID_AA64DFR0_PERFMON_SHIFT 8 182 #define ID_AA64DFR0_PERFMON_MASK 0xf 183 184 #define ID_DFR0_PMU_NOTIMPL 0b0000 185 #define ID_DFR0_PMU_V3 0b0001 186 #define ID_DFR0_PMU_V3_8_1 0b0100 187 #define ID_DFR0_PMU_V3_8_4 0b0101 188 #define ID_DFR0_PMU_V3_8_5 0b0110 189 #define ID_DFR0_PMU_IMPDEF 0b1111 190 191 static inline uint32_t get_id_aa64dfr0(void) { return read_sysreg(id_aa64dfr0_el1); } 192 static inline uint32_t get_pmcr(void) { return read_sysreg(pmcr_el0); } 193 static inline void set_pmcr(uint32_t v) { write_sysreg(v, pmcr_el0); } 194 static inline uint64_t get_pmccntr(void) { return read_sysreg(pmccntr_el0); } 195 static inline void set_pmccntr(uint64_t v) { write_sysreg(v, pmccntr_el0); } 196 static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, pmcntenset_el0); } 197 static inline void set_pmccfiltr(uint32_t v) { write_sysreg(v, pmccfiltr_el0); } 198 199 static inline uint8_t get_pmu_version(void) 200 { 201 uint8_t ver = (get_id_aa64dfr0() >> ID_AA64DFR0_PERFMON_SHIFT) & ID_AA64DFR0_PERFMON_MASK; 202 return ver; 203 } 204 205 /* 206 * Extra instructions inserted by the compiler would be difficult to compensate 207 * for, so hand assemble everything between, and including, the PMCR accesses 208 * to start and stop counting. isb instructions are inserted to make sure 209 * pmccntr read after this function returns the exact instructions executed 210 * in the controlled block. Total instrs = isb + msr + 2*loop = 2 + 2*loop. 211 */ 212 static inline void precise_instrs_loop(int loop, uint32_t pmcr) 213 { 214 uint64_t pmcr64 = pmcr; 215 asm volatile( 216 " msr pmcr_el0, %[pmcr]\n" 217 " isb\n" 218 "1: subs %w[loop], %w[loop], #1\n" 219 " b.gt 1b\n" 220 " msr pmcr_el0, xzr\n" 221 " isb\n" 222 : [loop] "+r" (loop) 223 : [pmcr] "r" (pmcr64) 224 : "cc"); 225 } 226 227 #define PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 228 #define PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 229 #define PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 230 231 #define PMEVTYPER_EXCLUDE_EL1 BIT(31) 232 #define PMEVTYPER_EXCLUDE_EL0 BIT(30) 233 234 static bool is_event_supported(uint32_t n, bool warn) 235 { 236 uint64_t pmceid0 = read_sysreg(pmceid0_el0); 237 uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); 238 bool supported; 239 uint64_t reg; 240 241 /* 242 * The low 32-bits of PMCEID0/1 respectively describe 243 * event support for events 0-31/32-63. Their High 244 * 32-bits describe support for extended events 245 * starting at 0x4000, using the same split. 246 */ 247 assert((n >= COMMON_EVENTS_LOW && n <= COMMON_EVENTS_HIGH) || 248 (n >= EXT_COMMON_EVENTS_LOW && n <= EXT_COMMON_EVENTS_HIGH)); 249 250 if (n <= COMMON_EVENTS_HIGH) 251 reg = lower_32_bits(pmceid0) | ((u64)lower_32_bits(pmceid1) << 32); 252 else 253 reg = upper_32_bits(pmceid0) | ((u64)upper_32_bits(pmceid1) << 32); 254 255 supported = reg & (1UL << (n & 0x3F)); 256 257 if (!supported && warn) 258 report_info("event 0x%x is not supported", n); 259 return supported; 260 } 261 262 static void test_event_introspection(void) 263 { 264 bool required_events; 265 266 if (!pmu.nb_implemented_counters) { 267 report_skip("No event counter, skip ..."); 268 return; 269 } 270 271 /* PMUv3 requires an implementation includes some common events */ 272 required_events = is_event_supported(SW_INCR, true) && 273 is_event_supported(CPU_CYCLES, true) && 274 (is_event_supported(INST_RETIRED, true) || 275 is_event_supported(INST_PREC, true)); 276 277 if (pmu.version >= ID_DFR0_PMU_V3_8_1) { 278 required_events = required_events && 279 is_event_supported(STALL_FRONTEND, true) && 280 is_event_supported(STALL_BACKEND, true); 281 } 282 283 report(required_events, "Check required events are implemented"); 284 } 285 286 /* 287 * Extra instructions inserted by the compiler would be difficult to compensate 288 * for, so hand assemble everything between, and including, the PMCR accesses 289 * to start and stop counting. isb instructions are inserted to make sure 290 * pmccntr read after this function returns the exact instructions executed 291 * in the controlled block. Loads @loop times the data at @address into x9. 292 */ 293 static void mem_access_loop(void *addr, long loop, uint32_t pmcr) 294 { 295 uint64_t pmcr64 = pmcr; 296 asm volatile( 297 " msr pmcr_el0, %[pmcr]\n" 298 " isb\n" 299 " mov x10, %[loop]\n" 300 "1: sub x10, x10, #1\n" 301 " ldr x9, [%[addr]]\n" 302 " cmp x10, #0x0\n" 303 " b.gt 1b\n" 304 " msr pmcr_el0, xzr\n" 305 " isb\n" 306 : 307 : [addr] "r" (addr), [pmcr] "r" (pmcr64), [loop] "r" (loop) 308 : "x9", "x10", "cc"); 309 } 310 311 static struct pmu_stats pmu_stats; 312 313 static void irq_handler(struct pt_regs *regs) 314 { 315 uint32_t irqstat, irqnr; 316 317 irqstat = gic_read_iar(); 318 irqnr = gic_iar_irqnr(irqstat); 319 320 if (irqnr == PMU_PPI) { 321 unsigned long overflows = read_sysreg(pmovsclr_el0); 322 int i; 323 324 for (i = 0; i < 32; i++) { 325 if (test_and_clear_bit(i, &overflows)) { 326 pmu_stats.interrupts[i]++; 327 pmu_stats.bitmap |= 1 << i; 328 } 329 } 330 write_sysreg(ALL_SET_32, pmovsclr_el0); 331 isb(); 332 } else { 333 pmu_stats.unexpected = true; 334 } 335 gic_write_eoir(irqstat); 336 } 337 338 static void pmu_reset_stats(void) 339 { 340 int i; 341 342 for (i = 0; i < 32; i++) 343 pmu_stats.interrupts[i] = 0; 344 345 pmu_stats.bitmap = 0; 346 pmu_stats.unexpected = false; 347 } 348 349 static void pmu_reset(void) 350 { 351 /* reset all counters, counting disabled at PMCR level*/ 352 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); 353 /* Disable all counters */ 354 write_sysreg_s(ALL_SET_32, PMCNTENCLR_EL0); 355 /* clear overflow reg */ 356 write_sysreg(ALL_SET_32, pmovsclr_el0); 357 /* disable overflow interrupts on all counters */ 358 write_sysreg(ALL_SET_32, pmintenclr_el1); 359 pmu_reset_stats(); 360 isb(); 361 } 362 363 static void test_event_counter_config(void) 364 { 365 int i; 366 367 if (!pmu.nb_implemented_counters) { 368 report_skip("No event counter, skip ..."); 369 return; 370 } 371 372 pmu_reset(); 373 374 /* 375 * Test setting through PMESELR/PMXEVTYPER and PMEVTYPERn read, 376 * select counter 0 377 */ 378 write_sysreg(1, PMSELR_EL0); 379 /* program this counter to count unsupported event */ 380 write_sysreg(0xEA, PMXEVTYPER_EL0); 381 write_sysreg(0xdeadbeef, PMXEVCNTR_EL0); 382 report((read_regn_el0(pmevtyper, 1) & 0xFFF) == 0xEA, 383 "PMESELR/PMXEVTYPER/PMEVTYPERn"); 384 report((read_regn_el0(pmevcntr, 1) == 0xdeadbeef), 385 "PMESELR/PMXEVCNTR/PMEVCNTRn"); 386 387 /* try to configure an unsupported event within the range [0x0, 0x3F] */ 388 for (i = 0; i <= 0x3F; i++) { 389 if (!is_event_supported(i, false)) 390 break; 391 } 392 if (i > 0x3F) { 393 report_skip("pmevtyper: all events within [0x0, 0x3F] are supported"); 394 return; 395 } 396 397 /* select counter 0 */ 398 write_sysreg(0, PMSELR_EL0); 399 /* program this counter to count unsupported event */ 400 write_sysreg(i, PMXEVCNTR_EL0); 401 /* read the counter value */ 402 read_sysreg(PMXEVCNTR_EL0); 403 report(read_sysreg(PMXEVCNTR_EL0) == i, 404 "read of a counter programmed with unsupported event"); 405 } 406 407 static bool satisfy_prerequisites(uint32_t *events, unsigned int nb_events) 408 { 409 int i; 410 411 if (pmu.nb_implemented_counters < nb_events) { 412 report_skip("Skip test as number of counters is too small (%d)", 413 pmu.nb_implemented_counters); 414 return false; 415 } 416 417 for (i = 0; i < nb_events; i++) { 418 if (!is_event_supported(events[i], false)) { 419 report_skip("Skip test as event 0x%x is not supported", 420 events[i]); 421 return false; 422 } 423 } 424 return true; 425 } 426 427 static uint64_t pmevcntr_mask(void) 428 { 429 /* 430 * Bits [63:0] are always incremented for 64-bit counters, 431 * even if the PMU is configured to generate an overflow at 432 * bits [31:0] 433 * 434 * For more details see the AArch64.IncrementEventCounter() 435 * pseudo-code in the ARM ARM DDI 0487I.a, section J1.1.1. 436 */ 437 if (pmu.version >= ID_DFR0_PMU_V3_8_5) 438 return ~0; 439 440 return (uint32_t)~0; 441 } 442 443 static bool check_overflow_prerequisites(bool overflow_at_64bits) 444 { 445 if (overflow_at_64bits && pmu.version < ID_DFR0_PMU_V3_8_5) { 446 report_skip("Skip test as 64 overflows need FEAT_PMUv3p5"); 447 return false; 448 } 449 450 return true; 451 } 452 453 static void test_basic_event_count(bool overflow_at_64bits) 454 { 455 uint32_t implemented_counter_mask, non_implemented_counter_mask; 456 uint64_t pre_overflow = PRE_OVERFLOW(overflow_at_64bits); 457 uint64_t pmcr_lp = overflow_at_64bits ? PMU_PMCR_LP : 0; 458 uint32_t events[] = {CPU_CYCLES, INST_RETIRED}; 459 uint32_t counter_mask; 460 461 if (!satisfy_prerequisites(events, ARRAY_SIZE(events)) || 462 !check_overflow_prerequisites(overflow_at_64bits)) 463 return; 464 465 implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1; 466 non_implemented_counter_mask = ~(BIT(31) | implemented_counter_mask); 467 counter_mask = implemented_counter_mask | non_implemented_counter_mask; 468 469 write_regn_el0(pmevtyper, 0, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 470 write_regn_el0(pmevtyper, 1, INST_RETIRED | PMEVTYPER_EXCLUDE_EL0); 471 472 /* disable all counters */ 473 write_sysreg_s(ALL_SET_32, PMCNTENCLR_EL0); 474 report(!read_sysreg_s(PMCNTENCLR_EL0) && !read_sysreg_s(PMCNTENSET_EL0), 475 "pmcntenclr: disable all counters"); 476 477 /* 478 * clear cycle and all event counters and allow counter enablement 479 * through PMCNTENSET. LC is RES1. 480 */ 481 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P | pmcr_lp); 482 isb(); 483 report(get_pmcr() == (pmu.pmcr_ro | PMU_PMCR_LC | pmcr_lp), "pmcr: reset counters"); 484 485 /* Preset counter #0 to pre overflow value to trigger an overflow */ 486 write_regn_el0(pmevcntr, 0, pre_overflow); 487 report(read_regn_el0(pmevcntr, 0) == pre_overflow, 488 "counter #0 preset to pre-overflow value"); 489 report(!read_regn_el0(pmevcntr, 1), "counter #1 is 0"); 490 491 /* 492 * Enable all implemented counters and also attempt to enable 493 * not supported counters. Counting still is disabled by !PMCR.E 494 */ 495 write_sysreg_s(counter_mask, PMCNTENSET_EL0); 496 497 /* check only those implemented are enabled */ 498 report((read_sysreg_s(PMCNTENSET_EL0) == read_sysreg_s(PMCNTENCLR_EL0)) && 499 (read_sysreg_s(PMCNTENSET_EL0) == implemented_counter_mask), 500 "pmcntenset: enabled implemented_counters"); 501 502 /* Disable all counters but counters #0 and #1 */ 503 write_sysreg_s(~0x3, PMCNTENCLR_EL0); 504 report((read_sysreg_s(PMCNTENSET_EL0) == read_sysreg_s(PMCNTENCLR_EL0)) && 505 (read_sysreg_s(PMCNTENSET_EL0) == 0x3), 506 "pmcntenset: just enabled #0 and #1"); 507 508 /* clear overflow register */ 509 write_sysreg(ALL_SET_32, pmovsclr_el0); 510 report(!read_sysreg(pmovsclr_el0), "check overflow reg is 0"); 511 512 /* disable overflow interrupts on all counters*/ 513 write_sysreg(ALL_SET_32, pmintenclr_el1); 514 report(!read_sysreg(pmintenclr_el1), 515 "pmintenclr_el1=0, all interrupts disabled"); 516 517 /* enable overflow interrupts on all event counters */ 518 write_sysreg(implemented_counter_mask | non_implemented_counter_mask, 519 pmintenset_el1); 520 report(read_sysreg(pmintenset_el1) == implemented_counter_mask, 521 "overflow interrupts enabled on all implemented counters"); 522 523 /* Set PMCR.E, execute asm code and unset PMCR.E */ 524 precise_instrs_loop(20, pmu.pmcr_ro | PMU_PMCR_E); 525 526 report_info("counter #0 is 0x%lx (CPU_CYCLES)", 527 read_regn_el0(pmevcntr, 0)); 528 report_info("counter #1 is 0x%lx (INST_RETIRED)", 529 read_regn_el0(pmevcntr, 1)); 530 531 report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); 532 report(read_sysreg(pmovsclr_el0) & 0x1, 533 "check overflow happened on #0 only"); 534 } 535 536 static void test_mem_access(bool overflow_at_64bits) 537 { 538 void *addr = malloc(PAGE_SIZE); 539 uint32_t events[] = {MEM_ACCESS, MEM_ACCESS}; 540 uint64_t pre_overflow = PRE_OVERFLOW(overflow_at_64bits); 541 uint64_t pmcr_lp = overflow_at_64bits ? PMU_PMCR_LP : 0; 542 543 if (!satisfy_prerequisites(events, ARRAY_SIZE(events)) || 544 !check_overflow_prerequisites(overflow_at_64bits)) 545 return; 546 547 pmu_reset(); 548 549 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 550 write_regn_el0(pmevtyper, 1, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 551 write_sysreg_s(0x3, PMCNTENSET_EL0); 552 isb(); 553 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 554 report_info("counter #0 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 0)); 555 report_info("counter #1 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 1)); 556 /* We may measure more than 20 mem access depending on the core */ 557 report((read_regn_el0(pmevcntr, 0) == read_regn_el0(pmevcntr, 1)) && 558 (read_regn_el0(pmevcntr, 0) >= 20) && !read_sysreg(pmovsclr_el0), 559 "Ran 20 mem accesses"); 560 561 pmu_reset(); 562 563 write_regn_el0(pmevcntr, 0, pre_overflow); 564 write_regn_el0(pmevcntr, 1, pre_overflow); 565 write_sysreg_s(0x3, PMCNTENSET_EL0); 566 isb(); 567 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 568 report(read_sysreg(pmovsclr_el0) == 0x3, 569 "Ran 20 mem accesses with expected overflows on both counters"); 570 report_info("cnt#0=0x%lx cnt#1=0x%lx overflow=0x%lx", 571 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), 572 read_sysreg(pmovsclr_el0)); 573 } 574 575 static void test_sw_incr(bool overflow_at_64bits) 576 { 577 uint64_t pre_overflow = PRE_OVERFLOW(overflow_at_64bits); 578 uint64_t pmcr_lp = overflow_at_64bits ? PMU_PMCR_LP : 0; 579 uint32_t events[] = {SW_INCR, SW_INCR}; 580 uint64_t cntr0 = (pre_overflow + 100) & pmevcntr_mask(); 581 int i; 582 583 if (!satisfy_prerequisites(events, ARRAY_SIZE(events)) || 584 !check_overflow_prerequisites(overflow_at_64bits)) 585 return; 586 587 pmu_reset(); 588 589 write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 590 write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 591 /* enable counters #0 and #1 */ 592 write_sysreg_s(0x3, PMCNTENSET_EL0); 593 594 write_regn_el0(pmevcntr, 0, pre_overflow); 595 isb(); 596 597 for (i = 0; i < 100; i++) 598 write_sysreg(0x1, pmswinc_el0); 599 600 isb(); 601 report_info("SW_INCR counter #0 has value 0x%lx", read_regn_el0(pmevcntr, 0)); 602 report(read_regn_el0(pmevcntr, 0) == pre_overflow, 603 "PWSYNC does not increment if PMCR.E is unset"); 604 605 pmu_reset(); 606 607 write_regn_el0(pmevcntr, 0, pre_overflow); 608 write_sysreg_s(0x3, PMCNTENSET_EL0); 609 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 610 isb(); 611 612 for (i = 0; i < 100; i++) 613 write_sysreg(0x3, pmswinc_el0); 614 615 isb(); 616 report(read_regn_el0(pmevcntr, 0) == cntr0, "counter #0 after + 100 SW_INCR"); 617 report(read_regn_el0(pmevcntr, 1) == 100, "counter #1 after + 100 SW_INCR"); 618 report_info("counter values after 100 SW_INCR #0=0x%lx #1=0x%lx", 619 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 620 report(read_sysreg(pmovsclr_el0) == 0x1, 621 "overflow on counter #0 after 100 SW_INCR"); 622 } 623 624 static void test_chained_counters(bool unused) 625 { 626 uint32_t events[] = {CPU_CYCLES, CHAIN}; 627 uint64_t all_set = pmevcntr_mask(); 628 629 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 630 return; 631 632 pmu_reset(); 633 634 write_regn_el0(pmevtyper, 0, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 635 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 636 /* enable counters #0 and #1 */ 637 write_sysreg_s(0x3, PMCNTENSET_EL0); 638 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); 639 640 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); 641 642 report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented"); 643 report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #1"); 644 645 /* test 64b overflow */ 646 647 pmu_reset(); 648 write_sysreg_s(0x3, PMCNTENSET_EL0); 649 650 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); 651 write_regn_el0(pmevcntr, 1, 0x1); 652 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); 653 report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); 654 report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2"); 655 report(read_sysreg(pmovsclr_el0) == 0x1, "overflow recorded for chained incr #2"); 656 657 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); 658 write_regn_el0(pmevcntr, 1, all_set); 659 660 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); 661 report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); 662 report(read_regn_el0(pmevcntr, 1) == 0, "CHAIN counter #1 wrapped"); 663 report(read_sysreg(pmovsclr_el0) == 0x3, "overflow on even and odd counters"); 664 } 665 666 static void test_chained_sw_incr(bool unused) 667 { 668 uint32_t events[] = {SW_INCR, CHAIN}; 669 uint64_t cntr0 = (PRE_OVERFLOW_32 + 100) & pmevcntr_mask(); 670 uint64_t cntr1 = (ALL_SET_32 + 1) & pmevcntr_mask(); 671 int i; 672 673 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 674 return; 675 676 pmu_reset(); 677 678 write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 679 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 680 /* enable counters #0 and #1 */ 681 write_sysreg_s(0x3, PMCNTENSET_EL0); 682 683 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); 684 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); 685 isb(); 686 687 for (i = 0; i < 100; i++) 688 write_sysreg(0x1, pmswinc_el0); 689 690 isb(); 691 report((read_sysreg(pmovsclr_el0) == 0x1) && 692 (read_regn_el0(pmevcntr, 1) == 1), 693 "overflow and chain counter incremented after 100 SW_INCR/CHAIN"); 694 report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0), 695 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 696 697 /* 64b SW_INCR and overflow on CHAIN counter*/ 698 pmu_reset(); 699 700 write_regn_el0(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); 701 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); 702 write_regn_el0(pmevcntr, 1, ALL_SET_32); 703 write_sysreg_s(0x3, PMCNTENSET_EL0); 704 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); 705 isb(); 706 707 for (i = 0; i < 100; i++) 708 write_sysreg(0x1, pmswinc_el0); 709 710 isb(); 711 report((read_sysreg(pmovsclr_el0) == 0x3) && 712 (read_regn_el0(pmevcntr, 0) == cntr0) && 713 (read_regn_el0(pmevcntr, 1) == cntr1), 714 "expected overflows and values after 100 SW_INCR/CHAIN"); 715 report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0), 716 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 717 } 718 719 static void test_chain_promotion(bool unused) 720 { 721 uint32_t events[] = {MEM_ACCESS, CHAIN}; 722 void *addr = malloc(PAGE_SIZE); 723 724 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 725 return; 726 727 /* Only enable CHAIN counter */ 728 pmu_reset(); 729 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 730 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 731 write_sysreg_s(0x2, PMCNTENSET_EL0); 732 isb(); 733 734 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 735 report(!read_regn_el0(pmevcntr, 0), 736 "chain counter not counting if even counter is disabled"); 737 738 /* Only enable even counter */ 739 pmu_reset(); 740 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW_32); 741 write_sysreg_s(0x1, PMCNTENSET_EL0); 742 isb(); 743 744 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 745 report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1), 746 "odd counter did not increment on overflow if disabled"); 747 report_info("MEM_ACCESS counter #0 has value 0x%lx", 748 read_regn_el0(pmevcntr, 0)); 749 report_info("CHAIN counter #1 has value 0x%lx", 750 read_regn_el0(pmevcntr, 1)); 751 report_info("overflow counter 0x%lx", read_sysreg(pmovsclr_el0)); 752 753 /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */ 754 pmu_reset(); 755 write_sysreg_s(0x3, PMCNTENSET_EL0); 756 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); 757 isb(); 758 759 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 760 report_info("MEM_ACCESS counter #0 has value 0x%lx", 761 read_regn_el0(pmevcntr, 0)); 762 763 /* disable the CHAIN event */ 764 write_sysreg_s(0x2, PMCNTENCLR_EL0); 765 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 766 report_info("MEM_ACCESS counter #0 has value 0x%lx", 767 read_regn_el0(pmevcntr, 0)); 768 report(read_sysreg(pmovsclr_el0) == 0x1, 769 "should have triggered an overflow on #0"); 770 report(!read_regn_el0(pmevcntr, 1), 771 "CHAIN counter #1 shouldn't have incremented"); 772 773 /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled */ 774 775 pmu_reset(); 776 write_sysreg_s(0x1, PMCNTENSET_EL0); 777 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); 778 isb(); 779 report_info("counter #0 = 0x%lx, counter #1 = 0x%lx overflow=0x%lx", 780 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), 781 read_sysreg(pmovsclr_el0)); 782 783 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 784 report_info("MEM_ACCESS counter #0 has value 0x%lx", 785 read_regn_el0(pmevcntr, 0)); 786 787 /* enable the CHAIN event */ 788 write_sysreg_s(0x3, PMCNTENSET_EL0); 789 isb(); 790 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 791 report_info("MEM_ACCESS counter #0 has value 0x%lx", 792 read_regn_el0(pmevcntr, 0)); 793 794 report((read_regn_el0(pmevcntr, 1) == 1) && 795 (read_sysreg(pmovsclr_el0) == 0x1), 796 "CHAIN counter enabled: CHAIN counter was incremented and overflow"); 797 798 report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", 799 read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); 800 801 /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ 802 pmu_reset(); 803 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 804 write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 805 write_sysreg_s(0x3, PMCNTENSET_EL0); 806 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); 807 isb(); 808 809 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 810 report_info("MEM_ACCESS counter #0 has value 0x%lx", 811 read_regn_el0(pmevcntr, 0)); 812 813 /* 0 becomes CHAINED */ 814 write_sysreg_s(0x0, PMCNTENSET_EL0); 815 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 816 write_sysreg_s(0x3, PMCNTENSET_EL0); 817 write_regn_el0(pmevcntr, 1, 0x0); 818 819 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 820 report_info("MEM_ACCESS counter #0 has value 0x%lx", 821 read_regn_el0(pmevcntr, 0)); 822 823 report((read_regn_el0(pmevcntr, 1) == 1) && 824 (read_sysreg(pmovsclr_el0) == 0x1), 825 "32b->64b: CHAIN counter incremented and overflow"); 826 827 report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", 828 read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); 829 830 /* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ 831 pmu_reset(); 832 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 833 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 834 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2_32); 835 write_sysreg_s(0x3, PMCNTENSET_EL0); 836 837 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 838 report_info("counter #0=0x%lx, counter #1=0x%lx", 839 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 840 841 write_sysreg_s(0x0, PMCNTENSET_EL0); 842 write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 843 write_sysreg_s(0x3, PMCNTENSET_EL0); 844 845 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 846 report(read_sysreg(pmovsclr_el0) == 1, 847 "overflow is expected on counter 0"); 848 report_info("counter #0=0x%lx, counter #1=0x%lx overflow=0x%lx", 849 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), 850 read_sysreg(pmovsclr_el0)); 851 } 852 853 static bool expect_interrupts(uint32_t bitmap) 854 { 855 int i; 856 857 if (pmu_stats.bitmap ^ bitmap || pmu_stats.unexpected) 858 return false; 859 860 for (i = 0; i < 32; i++) { 861 if (test_and_clear_bit(i, &pmu_stats.bitmap)) 862 if (pmu_stats.interrupts[i] != 1) 863 return false; 864 } 865 return true; 866 } 867 868 static void test_overflow_interrupt(bool overflow_at_64bits) 869 { 870 uint64_t pre_overflow = PRE_OVERFLOW(overflow_at_64bits); 871 uint64_t all_set = pmevcntr_mask(); 872 uint64_t pmcr_lp = overflow_at_64bits ? PMU_PMCR_LP : 0; 873 uint32_t events[] = {MEM_ACCESS, SW_INCR}; 874 void *addr = malloc(PAGE_SIZE); 875 int i; 876 877 if (!satisfy_prerequisites(events, ARRAY_SIZE(events)) || 878 !check_overflow_prerequisites(overflow_at_64bits)) 879 return; 880 881 gic_enable_defaults(); 882 install_irq_handler(EL1H_IRQ, irq_handler); 883 local_irq_enable(); 884 gic_enable_irq(23); 885 886 pmu_reset(); 887 888 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 889 write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 890 write_sysreg_s(0x3, PMCNTENSET_EL0); 891 write_regn_el0(pmevcntr, 0, pre_overflow); 892 write_regn_el0(pmevcntr, 1, pre_overflow); 893 isb(); 894 895 /* interrupts are disabled (PMINTENSET_EL1 == 0) */ 896 897 mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 898 report(expect_interrupts(0), "no overflow interrupt after preset"); 899 900 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 901 isb(); 902 903 for (i = 0; i < 100; i++) 904 write_sysreg(0x2, pmswinc_el0); 905 906 isb(); 907 set_pmcr(pmu.pmcr_ro); 908 isb(); 909 report(expect_interrupts(0), "no overflow interrupt after counting"); 910 911 /* enable interrupts (PMINTENSET_EL1 <= ALL_SET_32) */ 912 913 pmu_reset_stats(); 914 915 write_regn_el0(pmevcntr, 0, pre_overflow); 916 write_regn_el0(pmevcntr, 1, pre_overflow); 917 write_sysreg(ALL_SET_32, pmovsclr_el0); 918 write_sysreg(ALL_SET_32, pmintenset_el1); 919 isb(); 920 921 mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 922 923 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 924 isb(); 925 926 for (i = 0; i < 100; i++) 927 write_sysreg(0x3, pmswinc_el0); 928 929 mem_access_loop(addr, 200, pmu.pmcr_ro); 930 report_info("overflow=0x%lx", read_sysreg(pmovsclr_el0)); 931 report(expect_interrupts(0x3), 932 "overflow interrupts expected on #0 and #1"); 933 934 /* 935 * promote to 64-b: 936 * 937 * This only applies to the !overflow_at_64bits case, as 938 * overflow_at_64bits doesn't implement CHAIN events. The 939 * overflow_at_64bits case just checks that chained counters are 940 * not incremented when PMCR.LP == 1. 941 */ 942 943 pmu_reset_stats(); 944 945 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 946 write_regn_el0(pmevcntr, 0, pre_overflow); 947 isb(); 948 mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 949 report(expect_interrupts(0x1), "expect overflow interrupt"); 950 951 /* overflow on odd counter */ 952 pmu_reset_stats(); 953 write_regn_el0(pmevcntr, 0, pre_overflow); 954 write_regn_el0(pmevcntr, 1, all_set); 955 isb(); 956 mem_access_loop(addr, 400, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); 957 if (overflow_at_64bits) { 958 report(expect_interrupts(0x1), 959 "expect overflow interrupt on even counter"); 960 report(read_regn_el0(pmevcntr, 1) == all_set, 961 "Odd counter did not change"); 962 } else { 963 report(expect_interrupts(0x3), 964 "expect overflow interrupt on even and odd counter"); 965 report(read_regn_el0(pmevcntr, 1) != all_set, 966 "Odd counter wrapped"); 967 } 968 } 969 #endif 970 971 /* 972 * Ensure that the cycle counter progresses between back-to-back reads. 973 */ 974 static bool check_cycles_increase(void) 975 { 976 bool success = true; 977 978 /* init before event access, this test only cares about cycle count */ 979 pmu_reset(); 980 set_pmcntenset(1 << PMU_CYCLE_IDX); 981 set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ 982 983 set_pmcr(get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E); 984 isb(); 985 986 for (int i = 0; i < NR_SAMPLES; i++) { 987 uint64_t a, b; 988 989 a = get_pmccntr(); 990 b = get_pmccntr(); 991 992 if (a >= b) { 993 printf("Read %"PRId64" then %"PRId64".\n", a, b); 994 success = false; 995 break; 996 } 997 } 998 999 set_pmcr(get_pmcr() & ~PMU_PMCR_E); 1000 isb(); 1001 1002 return success; 1003 } 1004 1005 /* 1006 * Execute a known number of guest instructions. Only even instruction counts 1007 * greater than or equal to 4 are supported by the in-line assembly code. The 1008 * control register (PMCR_EL0) is initialized with the provided value (allowing 1009 * for example for the cycle counter or event counters to be reset). At the end 1010 * of the exact instruction loop, zero is written to PMCR_EL0 to disable 1011 * counting, allowing the cycle counter or event counters to be read at the 1012 * leisure of the calling code. 1013 */ 1014 static void measure_instrs(int num, uint32_t pmcr) 1015 { 1016 int loop = (num - 2) / 2; 1017 1018 assert(num >= 4 && ((num - 2) % 2 == 0)); 1019 precise_instrs_loop(loop, pmcr); 1020 } 1021 1022 /* 1023 * Measure cycle counts for various known instruction counts. Ensure that the 1024 * cycle counter progresses (similar to check_cycles_increase() but with more 1025 * instructions and using reset and stop controls). If supplied a positive, 1026 * nonzero CPI parameter, it also strictly checks that every measurement matches 1027 * it. Strict CPI checking is used to test -icount mode. 1028 */ 1029 static bool check_cpi(int cpi) 1030 { 1031 uint32_t pmcr = get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E; 1032 1033 /* init before event access, this test only cares about cycle count */ 1034 pmu_reset(); 1035 set_pmcntenset(1 << PMU_CYCLE_IDX); 1036 set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ 1037 1038 if (cpi > 0) 1039 printf("Checking for CPI=%d.\n", cpi); 1040 printf("instrs : cycles0 cycles1 ...\n"); 1041 1042 for (unsigned int i = 4; i < 300; i += 32) { 1043 uint64_t avg, sum = 0; 1044 1045 printf("%4d:", i); 1046 for (int j = 0; j < NR_SAMPLES; j++) { 1047 uint64_t cycles; 1048 1049 set_pmccntr(0); 1050 measure_instrs(i, pmcr); 1051 cycles = get_pmccntr(); 1052 printf(" %4"PRId64"", cycles); 1053 1054 if (!cycles) { 1055 printf("\ncycles not incrementing!\n"); 1056 return false; 1057 } else if (cpi > 0 && cycles != i * cpi) { 1058 printf("\nunexpected cycle count received!\n"); 1059 return false; 1060 } else if ((cycles >> 32) != 0) { 1061 /* The cycles taken by the loop above should 1062 * fit in 32 bits easily. We check the upper 1063 * 32 bits of the cycle counter to make sure 1064 * there is no supprise. */ 1065 printf("\ncycle count bigger than 32bit!\n"); 1066 return false; 1067 } 1068 1069 sum += cycles; 1070 } 1071 avg = sum / NR_SAMPLES; 1072 printf(" avg=%-4"PRId64" %s=%-3"PRId64"\n", avg, 1073 (avg >= i) ? "cpi" : "ipc", 1074 (avg >= i) ? avg / i : i / avg); 1075 } 1076 1077 return true; 1078 } 1079 1080 static void pmccntr64_test(void) 1081 { 1082 #ifdef __arm__ 1083 if (pmu.version == ID_DFR0_PMU_V3) { 1084 if (ERRATA(9e3f7a296940)) { 1085 write_sysreg(0xdead, PMCCNTR64); 1086 report(read_sysreg(PMCCNTR64) == 0xdead, "pmccntr64"); 1087 } else 1088 report_skip("Skipping unsafe pmccntr64 test. Set ERRATA_9e3f7a296940=y to enable."); 1089 } 1090 #endif 1091 } 1092 1093 /* Return FALSE if no PMU found, otherwise return TRUE */ 1094 static bool pmu_probe(void) 1095 { 1096 uint32_t pmcr; 1097 uint8_t implementer; 1098 1099 pmu.version = get_pmu_version(); 1100 if (pmu.version == ID_DFR0_PMU_NOTIMPL || pmu.version == ID_DFR0_PMU_IMPDEF) 1101 return false; 1102 1103 report_info("PMU version: 0x%x", pmu.version); 1104 1105 pmcr = get_pmcr(); 1106 implementer = (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK; 1107 report_info("PMU implementer/ID code: %#"PRIx32"(\"%c\")/%#"PRIx32, 1108 (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK, 1109 implementer ? implementer : ' ', 1110 (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK); 1111 1112 /* store read-only and RES0 fields of the PMCR bottom-half*/ 1113 pmu.pmcr_ro = pmcr & 0xFFFFFF00; 1114 pmu.nb_implemented_counters = 1115 (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK; 1116 report_info("Implements %d event counters", 1117 pmu.nb_implemented_counters); 1118 1119 return true; 1120 } 1121 1122 static void run_test(const char *name, const char *prefix, 1123 void (*test)(bool), void *arg) 1124 { 1125 report_prefix_push(name); 1126 report_prefix_push(prefix); 1127 1128 test(arg); 1129 1130 report_prefix_pop(); 1131 report_prefix_pop(); 1132 } 1133 1134 static void run_event_test(char *name, void (*test)(bool), 1135 bool overflow_at_64bits) 1136 { 1137 const char *prefix = overflow_at_64bits ? "64-bit overflows" 1138 : "32-bit overflows"; 1139 1140 run_test(name, prefix, test, (void *)overflow_at_64bits); 1141 } 1142 1143 int main(int argc, char *argv[]) 1144 { 1145 int cpi = 0; 1146 1147 if (!pmu_probe()) { 1148 printf("No PMU found, test skipped...\n"); 1149 return report_summary(); 1150 } 1151 1152 if (argc < 2) 1153 report_abort("no test specified"); 1154 1155 report_prefix_push("pmu"); 1156 1157 if (strcmp(argv[1], "cycle-counter") == 0) { 1158 report_prefix_push(argv[1]); 1159 if (argc > 2) 1160 cpi = atol(argv[2]); 1161 report(check_cycles_increase(), 1162 "Monotonically increasing cycle count"); 1163 report(check_cpi(cpi), "Cycle/instruction ratio"); 1164 pmccntr64_test(); 1165 report_prefix_pop(); 1166 } else if (strcmp(argv[1], "pmu-event-introspection") == 0) { 1167 report_prefix_push(argv[1]); 1168 test_event_introspection(); 1169 report_prefix_pop(); 1170 } else if (strcmp(argv[1], "pmu-event-counter-config") == 0) { 1171 report_prefix_push(argv[1]); 1172 test_event_counter_config(); 1173 report_prefix_pop(); 1174 } else if (strcmp(argv[1], "pmu-basic-event-count") == 0) { 1175 run_event_test(argv[1], test_basic_event_count, false); 1176 run_event_test(argv[1], test_basic_event_count, true); 1177 } else if (strcmp(argv[1], "pmu-mem-access") == 0) { 1178 run_event_test(argv[1], test_mem_access, false); 1179 run_event_test(argv[1], test_mem_access, true); 1180 } else if (strcmp(argv[1], "pmu-sw-incr") == 0) { 1181 run_event_test(argv[1], test_sw_incr, false); 1182 run_event_test(argv[1], test_sw_incr, true); 1183 } else if (strcmp(argv[1], "pmu-chained-counters") == 0) { 1184 run_event_test(argv[1], test_chained_counters, false); 1185 } else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) { 1186 run_event_test(argv[1], test_chained_sw_incr, false); 1187 } else if (strcmp(argv[1], "pmu-chain-promotion") == 0) { 1188 run_event_test(argv[1], test_chain_promotion, false); 1189 } else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) { 1190 run_event_test(argv[1], test_overflow_interrupt, false); 1191 run_event_test(argv[1], test_overflow_interrupt, true); 1192 } else { 1193 report_abort("Unknown sub-test '%s'", argv[1]); 1194 } 1195 1196 return report_summary(); 1197 } 1198