1 /* 2 * Test the ARM Performance Monitors Unit (PMU). 3 * 4 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 5 * Copyright (C) 2016, Red Hat Inc, Wei Huang <wei@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU Lesser General Public License version 2.1 and 9 * only version 2.1 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License 14 * for more details. 15 */ 16 #include "libcflat.h" 17 #include "errata.h" 18 #include "asm/barrier.h" 19 #include "asm/sysreg.h" 20 #include "asm/processor.h" 21 #include <bitops.h> 22 #include <asm/gic.h> 23 24 #define PMU_PMCR_E (1 << 0) 25 #define PMU_PMCR_P (1 << 1) 26 #define PMU_PMCR_C (1 << 2) 27 #define PMU_PMCR_D (1 << 3) 28 #define PMU_PMCR_X (1 << 4) 29 #define PMU_PMCR_DP (1 << 5) 30 #define PMU_PMCR_LC (1 << 6) 31 #define PMU_PMCR_N_SHIFT 11 32 #define PMU_PMCR_N_MASK 0x1f 33 #define PMU_PMCR_ID_SHIFT 16 34 #define PMU_PMCR_ID_MASK 0xff 35 #define PMU_PMCR_IMP_SHIFT 24 36 #define PMU_PMCR_IMP_MASK 0xff 37 38 #define PMU_CYCLE_IDX 31 39 40 #define NR_SAMPLES 10 41 42 /* Some PMU events */ 43 #define SW_INCR 0x0 44 #define INST_RETIRED 0x8 45 #define CPU_CYCLES 0x11 46 #define MEM_ACCESS 0x13 47 #define INST_PREC 0x1B 48 #define STALL_FRONTEND 0x23 49 #define STALL_BACKEND 0x24 50 #define CHAIN 0x1E 51 52 #define COMMON_EVENTS_LOW 0x0 53 #define COMMON_EVENTS_HIGH 0x3F 54 #define EXT_COMMON_EVENTS_LOW 0x4000 55 #define EXT_COMMON_EVENTS_HIGH 0x403F 56 57 #define ALL_SET 0xFFFFFFFF 58 #define ALL_CLEAR 0x0 59 #define PRE_OVERFLOW 0xFFFFFFF0 60 #define PRE_OVERFLOW2 0xFFFFFFDC 61 62 #define PMU_PPI 23 63 64 struct pmu { 65 unsigned int version; 66 unsigned int nb_implemented_counters; 67 uint32_t pmcr_ro; 68 }; 69 70 struct pmu_stats { 71 unsigned long bitmap; 72 uint32_t interrupts[32]; 73 bool unexpected; 74 }; 75 76 static struct pmu pmu; 77 78 #if defined(__arm__) 79 #define ID_DFR0_PERFMON_SHIFT 24 80 #define ID_DFR0_PERFMON_MASK 0xf 81 82 #define ID_DFR0_PMU_NOTIMPL 0b0000 83 #define ID_DFR0_PMU_V1 0b0001 84 #define ID_DFR0_PMU_V2 0b0010 85 #define ID_DFR0_PMU_V3 0b0011 86 #define ID_DFR0_PMU_V3_8_1 0b0100 87 #define ID_DFR0_PMU_V3_8_4 0b0101 88 #define ID_DFR0_PMU_V3_8_5 0b0110 89 #define ID_DFR0_PMU_IMPDEF 0b1111 90 91 #define PMCR __ACCESS_CP15(c9, 0, c12, 0) 92 #define ID_DFR0 __ACCESS_CP15(c0, 0, c1, 2) 93 #define PMSELR __ACCESS_CP15(c9, 0, c12, 5) 94 #define PMXEVTYPER __ACCESS_CP15(c9, 0, c13, 1) 95 #define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1) 96 #define PMCCNTR32 __ACCESS_CP15(c9, 0, c13, 0) 97 #define PMCCNTR64 __ACCESS_CP15_64(0, c9) 98 99 static inline uint32_t get_id_dfr0(void) { return read_sysreg(ID_DFR0); } 100 static inline uint32_t get_pmcr(void) { return read_sysreg(PMCR); } 101 static inline void set_pmcr(uint32_t v) { write_sysreg(v, PMCR); } 102 static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, PMCNTENSET); } 103 104 static inline uint8_t get_pmu_version(void) 105 { 106 return (get_id_dfr0() >> ID_DFR0_PERFMON_SHIFT) & ID_DFR0_PERFMON_MASK; 107 } 108 109 static inline uint64_t get_pmccntr(void) 110 { 111 return read_sysreg(PMCCNTR32); 112 } 113 114 static inline void set_pmccntr(uint64_t value) 115 { 116 write_sysreg(value & 0xffffffff, PMCCNTR32); 117 } 118 119 /* PMCCFILTR is an obsolete name for PMXEVTYPER31 in ARMv7 */ 120 static inline void set_pmccfiltr(uint32_t value) 121 { 122 write_sysreg(PMU_CYCLE_IDX, PMSELR); 123 write_sysreg(value, PMXEVTYPER); 124 isb(); 125 } 126 127 /* 128 * Extra instructions inserted by the compiler would be difficult to compensate 129 * for, so hand assemble everything between, and including, the PMCR accesses 130 * to start and stop counting. isb instructions were inserted to make sure 131 * pmccntr read after this function returns the exact instructions executed in 132 * the controlled block. Total instrs = isb + mcr + 2*loop = 2 + 2*loop. 133 */ 134 static inline void precise_instrs_loop(int loop, uint32_t pmcr) 135 { 136 asm volatile( 137 " mcr p15, 0, %[pmcr], c9, c12, 0\n" 138 " isb\n" 139 "1: subs %[loop], %[loop], #1\n" 140 " bgt 1b\n" 141 " mcr p15, 0, %[z], c9, c12, 0\n" 142 " isb\n" 143 : [loop] "+r" (loop) 144 : [pmcr] "r" (pmcr), [z] "r" (0) 145 : "cc"); 146 } 147 148 /* event counter tests only implemented for aarch64 */ 149 static void test_event_introspection(void) {} 150 static void test_event_counter_config(void) {} 151 static void test_basic_event_count(void) {} 152 static void test_mem_access(void) {} 153 static void test_sw_incr(void) {} 154 static void test_chained_counters(void) {} 155 static void test_chained_sw_incr(void) {} 156 static void test_chain_promotion(void) {} 157 static void test_overflow_interrupt(void) {} 158 159 #elif defined(__aarch64__) 160 #define ID_AA64DFR0_PERFMON_SHIFT 8 161 #define ID_AA64DFR0_PERFMON_MASK 0xf 162 163 #define ID_DFR0_PMU_NOTIMPL 0b0000 164 #define ID_DFR0_PMU_V3 0b0001 165 #define ID_DFR0_PMU_V3_8_1 0b0100 166 #define ID_DFR0_PMU_V3_8_4 0b0101 167 #define ID_DFR0_PMU_V3_8_5 0b0110 168 #define ID_DFR0_PMU_IMPDEF 0b1111 169 170 static inline uint32_t get_id_aa64dfr0(void) { return read_sysreg(id_aa64dfr0_el1); } 171 static inline uint32_t get_pmcr(void) { return read_sysreg(pmcr_el0); } 172 static inline void set_pmcr(uint32_t v) { write_sysreg(v, pmcr_el0); } 173 static inline uint64_t get_pmccntr(void) { return read_sysreg(pmccntr_el0); } 174 static inline void set_pmccntr(uint64_t v) { write_sysreg(v, pmccntr_el0); } 175 static inline void set_pmcntenset(uint32_t v) { write_sysreg(v, pmcntenset_el0); } 176 static inline void set_pmccfiltr(uint32_t v) { write_sysreg(v, pmccfiltr_el0); } 177 178 static inline uint8_t get_pmu_version(void) 179 { 180 uint8_t ver = (get_id_aa64dfr0() >> ID_AA64DFR0_PERFMON_SHIFT) & ID_AA64DFR0_PERFMON_MASK; 181 return ver; 182 } 183 184 /* 185 * Extra instructions inserted by the compiler would be difficult to compensate 186 * for, so hand assemble everything between, and including, the PMCR accesses 187 * to start and stop counting. isb instructions are inserted to make sure 188 * pmccntr read after this function returns the exact instructions executed 189 * in the controlled block. Total instrs = isb + msr + 2*loop = 2 + 2*loop. 190 */ 191 static inline void precise_instrs_loop(int loop, uint32_t pmcr) 192 { 193 asm volatile( 194 " msr pmcr_el0, %[pmcr]\n" 195 " isb\n" 196 "1: subs %[loop], %[loop], #1\n" 197 " b.gt 1b\n" 198 " msr pmcr_el0, xzr\n" 199 " isb\n" 200 : [loop] "+r" (loop) 201 : [pmcr] "r" (pmcr) 202 : "cc"); 203 } 204 205 #define PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 206 #define PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 207 #define PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 208 209 #define PMEVTYPER_EXCLUDE_EL1 BIT(31) 210 #define PMEVTYPER_EXCLUDE_EL0 BIT(30) 211 212 static bool is_event_supported(uint32_t n, bool warn) 213 { 214 uint64_t pmceid0 = read_sysreg(pmceid0_el0); 215 uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); 216 bool supported; 217 uint64_t reg; 218 219 /* 220 * The low 32-bits of PMCEID0/1 respectively describe 221 * event support for events 0-31/32-63. Their High 222 * 32-bits describe support for extended events 223 * starting at 0x4000, using the same split. 224 */ 225 assert((n >= COMMON_EVENTS_LOW && n <= COMMON_EVENTS_HIGH) || 226 (n >= EXT_COMMON_EVENTS_LOW && n <= EXT_COMMON_EVENTS_HIGH)); 227 228 if (n <= COMMON_EVENTS_HIGH) 229 reg = lower_32_bits(pmceid0) | ((u64)lower_32_bits(pmceid1) << 32); 230 else 231 reg = upper_32_bits(pmceid0) | ((u64)upper_32_bits(pmceid1) << 32); 232 233 supported = reg & (1UL << (n & 0x3F)); 234 235 if (!supported && warn) 236 report_info("event 0x%x is not supported", n); 237 return supported; 238 } 239 240 static void test_event_introspection(void) 241 { 242 bool required_events; 243 244 if (!pmu.nb_implemented_counters) { 245 report_skip("No event counter, skip ..."); 246 return; 247 } 248 249 /* PMUv3 requires an implementation includes some common events */ 250 required_events = is_event_supported(SW_INCR, true) && 251 is_event_supported(CPU_CYCLES, true) && 252 (is_event_supported(INST_RETIRED, true) || 253 is_event_supported(INST_PREC, true)); 254 255 if (pmu.version >= ID_DFR0_PMU_V3_8_1) { 256 required_events = required_events && 257 is_event_supported(STALL_FRONTEND, true) && 258 is_event_supported(STALL_BACKEND, true); 259 } 260 261 report(required_events, "Check required events are implemented"); 262 } 263 264 /* 265 * Extra instructions inserted by the compiler would be difficult to compensate 266 * for, so hand assemble everything between, and including, the PMCR accesses 267 * to start and stop counting. isb instructions are inserted to make sure 268 * pmccntr read after this function returns the exact instructions executed 269 * in the controlled block. Loads @loop times the data at @address into x9. 270 */ 271 static void mem_access_loop(void *addr, int loop, uint32_t pmcr) 272 { 273 asm volatile( 274 " msr pmcr_el0, %[pmcr]\n" 275 " isb\n" 276 " mov x10, %[loop]\n" 277 "1: sub x10, x10, #1\n" 278 " ldr x9, [%[addr]]\n" 279 " cmp x10, #0x0\n" 280 " b.gt 1b\n" 281 " msr pmcr_el0, xzr\n" 282 " isb\n" 283 : 284 : [addr] "r" (addr), [pmcr] "r" (pmcr), [loop] "r" (loop) 285 : "x9", "x10", "cc"); 286 } 287 288 static struct pmu_stats pmu_stats; 289 290 static void irq_handler(struct pt_regs *regs) 291 { 292 uint32_t irqstat, irqnr; 293 294 irqstat = gic_read_iar(); 295 irqnr = gic_iar_irqnr(irqstat); 296 297 if (irqnr == PMU_PPI) { 298 unsigned long overflows = read_sysreg(pmovsclr_el0); 299 int i; 300 301 for (i = 0; i < 32; i++) { 302 if (test_and_clear_bit(i, &overflows)) { 303 pmu_stats.interrupts[i]++; 304 pmu_stats.bitmap |= 1 << i; 305 } 306 } 307 write_sysreg(ALL_SET, pmovsclr_el0); 308 } else { 309 pmu_stats.unexpected = true; 310 } 311 gic_write_eoir(irqstat); 312 } 313 314 static void pmu_reset_stats(void) 315 { 316 int i; 317 318 for (i = 0; i < 32; i++) 319 pmu_stats.interrupts[i] = 0; 320 321 pmu_stats.bitmap = 0; 322 pmu_stats.unexpected = false; 323 } 324 325 static void pmu_reset(void) 326 { 327 /* reset all counters, counting disabled at PMCR level*/ 328 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); 329 /* Disable all counters */ 330 write_sysreg_s(ALL_SET, PMCNTENCLR_EL0); 331 /* clear overflow reg */ 332 write_sysreg(ALL_SET, pmovsclr_el0); 333 /* disable overflow interrupts on all counters */ 334 write_sysreg(ALL_SET, pmintenclr_el1); 335 pmu_reset_stats(); 336 isb(); 337 } 338 339 static void test_event_counter_config(void) 340 { 341 int i; 342 343 if (!pmu.nb_implemented_counters) { 344 report_skip("No event counter, skip ..."); 345 return; 346 } 347 348 pmu_reset(); 349 350 /* 351 * Test setting through PMESELR/PMXEVTYPER and PMEVTYPERn read, 352 * select counter 0 353 */ 354 write_sysreg(1, PMSELR_EL0); 355 /* program this counter to count unsupported event */ 356 write_sysreg(0xEA, PMXEVTYPER_EL0); 357 write_sysreg(0xdeadbeef, PMXEVCNTR_EL0); 358 report((read_regn_el0(pmevtyper, 1) & 0xFFF) == 0xEA, 359 "PMESELR/PMXEVTYPER/PMEVTYPERn"); 360 report((read_regn_el0(pmevcntr, 1) == 0xdeadbeef), 361 "PMESELR/PMXEVCNTR/PMEVCNTRn"); 362 363 /* try to configure an unsupported event within the range [0x0, 0x3F] */ 364 for (i = 0; i <= 0x3F; i++) { 365 if (!is_event_supported(i, false)) 366 break; 367 } 368 if (i > 0x3F) { 369 report_skip("pmevtyper: all events within [0x0, 0x3F] are supported"); 370 return; 371 } 372 373 /* select counter 0 */ 374 write_sysreg(0, PMSELR_EL0); 375 /* program this counter to count unsupported event */ 376 write_sysreg(i, PMXEVCNTR_EL0); 377 /* read the counter value */ 378 read_sysreg(PMXEVCNTR_EL0); 379 report(read_sysreg(PMXEVCNTR_EL0) == i, 380 "read of a counter programmed with unsupported event"); 381 } 382 383 static bool satisfy_prerequisites(uint32_t *events, unsigned int nb_events) 384 { 385 int i; 386 387 if (pmu.nb_implemented_counters < nb_events) { 388 report_skip("Skip test as number of counters is too small (%d)", 389 pmu.nb_implemented_counters); 390 return false; 391 } 392 393 for (i = 0; i < nb_events; i++) { 394 if (!is_event_supported(events[i], false)) { 395 report_skip("Skip test as event 0x%x is not supported", 396 events[i]); 397 return false; 398 } 399 } 400 return true; 401 } 402 403 static void test_basic_event_count(void) 404 { 405 uint32_t implemented_counter_mask, non_implemented_counter_mask; 406 uint32_t counter_mask; 407 uint32_t events[] = {CPU_CYCLES, INST_RETIRED}; 408 409 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 410 return; 411 412 implemented_counter_mask = BIT(pmu.nb_implemented_counters) - 1; 413 non_implemented_counter_mask = ~(BIT(31) | implemented_counter_mask); 414 counter_mask = implemented_counter_mask | non_implemented_counter_mask; 415 416 write_regn_el0(pmevtyper, 0, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 417 write_regn_el0(pmevtyper, 1, INST_RETIRED | PMEVTYPER_EXCLUDE_EL0); 418 419 /* disable all counters */ 420 write_sysreg_s(ALL_SET, PMCNTENCLR_EL0); 421 report(!read_sysreg_s(PMCNTENCLR_EL0) && !read_sysreg_s(PMCNTENSET_EL0), 422 "pmcntenclr: disable all counters"); 423 424 /* 425 * clear cycle and all event counters and allow counter enablement 426 * through PMCNTENSET. LC is RES1. 427 */ 428 set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P); 429 isb(); 430 report(get_pmcr() == (pmu.pmcr_ro | PMU_PMCR_LC), "pmcr: reset counters"); 431 432 /* Preset counter #0 to pre overflow value to trigger an overflow */ 433 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 434 report(read_regn_el0(pmevcntr, 0) == PRE_OVERFLOW, 435 "counter #0 preset to pre-overflow value"); 436 report(!read_regn_el0(pmevcntr, 1), "counter #1 is 0"); 437 438 /* 439 * Enable all implemented counters and also attempt to enable 440 * not supported counters. Counting still is disabled by !PMCR.E 441 */ 442 write_sysreg_s(counter_mask, PMCNTENSET_EL0); 443 444 /* check only those implemented are enabled */ 445 report((read_sysreg_s(PMCNTENSET_EL0) == read_sysreg_s(PMCNTENCLR_EL0)) && 446 (read_sysreg_s(PMCNTENSET_EL0) == implemented_counter_mask), 447 "pmcntenset: enabled implemented_counters"); 448 449 /* Disable all counters but counters #0 and #1 */ 450 write_sysreg_s(~0x3, PMCNTENCLR_EL0); 451 report((read_sysreg_s(PMCNTENSET_EL0) == read_sysreg_s(PMCNTENCLR_EL0)) && 452 (read_sysreg_s(PMCNTENSET_EL0) == 0x3), 453 "pmcntenset: just enabled #0 and #1"); 454 455 /* clear overflow register */ 456 write_sysreg(ALL_SET, pmovsclr_el0); 457 report(!read_sysreg(pmovsclr_el0), "check overflow reg is 0"); 458 459 /* disable overflow interrupts on all counters*/ 460 write_sysreg(ALL_SET, pmintenclr_el1); 461 report(!read_sysreg(pmintenclr_el1), 462 "pmintenclr_el1=0, all interrupts disabled"); 463 464 /* enable overflow interrupts on all event counters */ 465 write_sysreg(implemented_counter_mask | non_implemented_counter_mask, 466 pmintenset_el1); 467 report(read_sysreg(pmintenset_el1) == implemented_counter_mask, 468 "overflow interrupts enabled on all implemented counters"); 469 470 /* Set PMCR.E, execute asm code and unset PMCR.E */ 471 precise_instrs_loop(20, pmu.pmcr_ro | PMU_PMCR_E); 472 473 report_info("counter #0 is 0x%lx (CPU_CYCLES)", 474 read_regn_el0(pmevcntr, 0)); 475 report_info("counter #1 is 0x%lx (INST_RETIRED)", 476 read_regn_el0(pmevcntr, 1)); 477 478 report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); 479 report(read_sysreg(pmovsclr_el0) & 0x1, 480 "check overflow happened on #0 only"); 481 } 482 483 static void test_mem_access(void) 484 { 485 void *addr = malloc(PAGE_SIZE); 486 uint32_t events[] = {MEM_ACCESS, MEM_ACCESS}; 487 488 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 489 return; 490 491 pmu_reset(); 492 493 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 494 write_regn_el0(pmevtyper, 1, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 495 write_sysreg_s(0x3, PMCNTENSET_EL0); 496 isb(); 497 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 498 report_info("counter #0 is %ld (MEM_ACCESS)", read_regn_el0(pmevcntr, 0)); 499 report_info("counter #1 is %ld (MEM_ACCESS)", read_regn_el0(pmevcntr, 1)); 500 /* We may measure more than 20 mem access depending on the core */ 501 report((read_regn_el0(pmevcntr, 0) == read_regn_el0(pmevcntr, 1)) && 502 (read_regn_el0(pmevcntr, 0) >= 20) && !read_sysreg(pmovsclr_el0), 503 "Ran 20 mem accesses"); 504 505 pmu_reset(); 506 507 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 508 write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); 509 write_sysreg_s(0x3, PMCNTENSET_EL0); 510 isb(); 511 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 512 report(read_sysreg(pmovsclr_el0) == 0x3, 513 "Ran 20 mem accesses with expected overflows on both counters"); 514 report_info("cnt#0 = %ld cnt#1=%ld overflow=0x%lx", 515 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), 516 read_sysreg(pmovsclr_el0)); 517 } 518 519 static void test_sw_incr(void) 520 { 521 uint32_t events[] = {SW_INCR, SW_INCR}; 522 int i; 523 524 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 525 return; 526 527 pmu_reset(); 528 529 write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 530 write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 531 /* enable counters #0 and #1 */ 532 write_sysreg_s(0x3, PMCNTENSET_EL0); 533 534 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 535 536 for (i = 0; i < 100; i++) 537 write_sysreg(0x1, pmswinc_el0); 538 539 report_info("SW_INCR counter #0 has value %ld", read_regn_el0(pmevcntr, 0)); 540 report(read_regn_el0(pmevcntr, 0) == PRE_OVERFLOW, 541 "PWSYNC does not increment if PMCR.E is unset"); 542 543 pmu_reset(); 544 545 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 546 write_sysreg_s(0x3, PMCNTENSET_EL0); 547 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); 548 549 for (i = 0; i < 100; i++) 550 write_sysreg(0x3, pmswinc_el0); 551 552 report(read_regn_el0(pmevcntr, 0) == 84, "counter #1 after + 100 SW_INCR"); 553 report(read_regn_el0(pmevcntr, 1) == 100, 554 "counter #0 after + 100 SW_INCR"); 555 report_info("counter values after 100 SW_INCR #0=%ld #1=%ld", 556 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 557 report(read_sysreg(pmovsclr_el0) == 0x1, 558 "overflow on counter #0 after 100 SW_INCR"); 559 } 560 561 static void test_chained_counters(void) 562 { 563 uint32_t events[] = {CPU_CYCLES, CHAIN}; 564 565 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 566 return; 567 568 pmu_reset(); 569 570 write_regn_el0(pmevtyper, 0, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 571 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 572 /* enable counters #0 and #1 */ 573 write_sysreg_s(0x3, PMCNTENSET_EL0); 574 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 575 576 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); 577 578 report(read_regn_el0(pmevcntr, 1) == 1, "CHAIN counter #1 incremented"); 579 report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #1"); 580 581 /* test 64b overflow */ 582 583 pmu_reset(); 584 write_sysreg_s(0x3, PMCNTENSET_EL0); 585 586 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 587 write_regn_el0(pmevcntr, 1, 0x1); 588 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); 589 report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); 590 report(read_regn_el0(pmevcntr, 1) == 2, "CHAIN counter #1 set to 2"); 591 report(!read_sysreg(pmovsclr_el0), "no overflow recorded for chained incr #2"); 592 593 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 594 write_regn_el0(pmevcntr, 1, ALL_SET); 595 596 precise_instrs_loop(22, pmu.pmcr_ro | PMU_PMCR_E); 597 report_info("overflow reg = 0x%lx", read_sysreg(pmovsclr_el0)); 598 report(!read_regn_el0(pmevcntr, 1), "CHAIN counter #1 wrapped"); 599 report(read_sysreg(pmovsclr_el0) == 0x2, "overflow on chain counter"); 600 } 601 602 static void test_chained_sw_incr(void) 603 { 604 uint32_t events[] = {SW_INCR, CHAIN}; 605 int i; 606 607 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 608 return; 609 610 pmu_reset(); 611 612 write_regn_el0(pmevtyper, 0, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 613 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 614 /* enable counters #0 and #1 */ 615 write_sysreg_s(0x3, PMCNTENSET_EL0); 616 617 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 618 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); 619 for (i = 0; i < 100; i++) 620 write_sysreg(0x1, pmswinc_el0); 621 622 report(!read_sysreg(pmovsclr_el0) && (read_regn_el0(pmevcntr, 1) == 1), 623 "no overflow and chain counter incremented after 100 SW_INCR/CHAIN"); 624 report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0), 625 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 626 627 /* 64b SW_INCR and overflow on CHAIN counter*/ 628 pmu_reset(); 629 630 write_regn_el0(pmevtyper, 1, events[1] | PMEVTYPER_EXCLUDE_EL0); 631 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 632 write_regn_el0(pmevcntr, 1, ALL_SET); 633 write_sysreg_s(0x3, PMCNTENSET_EL0); 634 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); 635 for (i = 0; i < 100; i++) 636 write_sysreg(0x1, pmswinc_el0); 637 638 report((read_sysreg(pmovsclr_el0) == 0x2) && 639 (read_regn_el0(pmevcntr, 1) == 0) && 640 (read_regn_el0(pmevcntr, 0) == 84), 641 "overflow on chain counter and expected values after 100 SW_INCR/CHAIN"); 642 report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0), 643 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 644 } 645 646 static void test_chain_promotion(void) 647 { 648 uint32_t events[] = {MEM_ACCESS, CHAIN}; 649 void *addr = malloc(PAGE_SIZE); 650 651 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 652 return; 653 654 /* Only enable CHAIN counter */ 655 pmu_reset(); 656 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 657 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 658 write_sysreg_s(0x2, PMCNTENSET_EL0); 659 isb(); 660 661 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 662 report(!read_regn_el0(pmevcntr, 0), 663 "chain counter not counting if even counter is disabled"); 664 665 /* Only enable even counter */ 666 pmu_reset(); 667 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 668 write_sysreg_s(0x1, PMCNTENSET_EL0); 669 isb(); 670 671 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 672 report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1), 673 "odd counter did not increment on overflow if disabled"); 674 report_info("MEM_ACCESS counter #0 has value %ld", 675 read_regn_el0(pmevcntr, 0)); 676 report_info("CHAIN counter #1 has value %ld", 677 read_regn_el0(pmevcntr, 1)); 678 report_info("overflow counter %ld", read_sysreg(pmovsclr_el0)); 679 680 /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */ 681 pmu_reset(); 682 write_sysreg_s(0x3, PMCNTENSET_EL0); 683 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); 684 isb(); 685 686 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 687 report_info("MEM_ACCESS counter #0 has value 0x%lx", 688 read_regn_el0(pmevcntr, 0)); 689 690 /* disable the CHAIN event */ 691 write_sysreg_s(0x2, PMCNTENCLR_EL0); 692 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 693 report_info("MEM_ACCESS counter #0 has value 0x%lx", 694 read_regn_el0(pmevcntr, 0)); 695 report(read_sysreg(pmovsclr_el0) == 0x1, 696 "should have triggered an overflow on #0"); 697 report(!read_regn_el0(pmevcntr, 1), 698 "CHAIN counter #1 shouldn't have incremented"); 699 700 /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled */ 701 702 pmu_reset(); 703 write_sysreg_s(0x1, PMCNTENSET_EL0); 704 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); 705 isb(); 706 report_info("counter #0 = 0x%lx, counter #1 = 0x%lx overflow=0x%lx", 707 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), 708 read_sysreg(pmovsclr_el0)); 709 710 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 711 report_info("MEM_ACCESS counter #0 has value 0x%lx", 712 read_regn_el0(pmevcntr, 0)); 713 714 /* enable the CHAIN event */ 715 write_sysreg_s(0x3, PMCNTENSET_EL0); 716 isb(); 717 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 718 report_info("MEM_ACCESS counter #0 has value 0x%lx", 719 read_regn_el0(pmevcntr, 0)); 720 721 report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), 722 "CHAIN counter enabled: CHAIN counter was incremented and no overflow"); 723 724 report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", 725 read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); 726 727 /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ 728 pmu_reset(); 729 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 730 write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 731 write_sysreg_s(0x3, PMCNTENSET_EL0); 732 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); 733 isb(); 734 735 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 736 report_info("MEM_ACCESS counter #0 has value 0x%lx", 737 read_regn_el0(pmevcntr, 0)); 738 739 /* 0 becomes CHAINED */ 740 write_sysreg_s(0x0, PMCNTENSET_EL0); 741 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 742 write_sysreg_s(0x3, PMCNTENSET_EL0); 743 write_regn_el0(pmevcntr, 1, 0x0); 744 745 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 746 report_info("MEM_ACCESS counter #0 has value 0x%lx", 747 read_regn_el0(pmevcntr, 0)); 748 749 report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), 750 "32b->64b: CHAIN counter incremented and no overflow"); 751 752 report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", 753 read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); 754 755 /* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ 756 pmu_reset(); 757 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 758 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 759 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); 760 write_sysreg_s(0x3, PMCNTENSET_EL0); 761 762 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 763 report_info("counter #0=0x%lx, counter #1=0x%lx", 764 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); 765 766 write_sysreg_s(0x0, PMCNTENSET_EL0); 767 write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); 768 write_sysreg_s(0x3, PMCNTENSET_EL0); 769 770 mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); 771 report(read_sysreg(pmovsclr_el0) == 1, 772 "overflow is expected on counter 0"); 773 report_info("counter #0=0x%lx, counter #1=0x%lx overflow=0x%lx", 774 read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), 775 read_sysreg(pmovsclr_el0)); 776 } 777 778 static bool expect_interrupts(uint32_t bitmap) 779 { 780 int i; 781 782 if (pmu_stats.bitmap ^ bitmap || pmu_stats.unexpected) 783 return false; 784 785 for (i = 0; i < 32; i++) { 786 if (test_and_clear_bit(i, &pmu_stats.bitmap)) 787 if (pmu_stats.interrupts[i] != 1) 788 return false; 789 } 790 return true; 791 } 792 793 static void test_overflow_interrupt(void) 794 { 795 uint32_t events[] = {MEM_ACCESS, SW_INCR}; 796 void *addr = malloc(PAGE_SIZE); 797 int i; 798 799 if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) 800 return; 801 802 gic_enable_defaults(); 803 install_irq_handler(EL1H_IRQ, irq_handler); 804 local_irq_enable(); 805 gic_enable_irq(23); 806 807 pmu_reset(); 808 809 write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); 810 write_regn_el0(pmevtyper, 1, SW_INCR | PMEVTYPER_EXCLUDE_EL0); 811 write_sysreg_s(0x3, PMCNTENSET_EL0); 812 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 813 write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); 814 isb(); 815 816 /* interrupts are disabled */ 817 818 mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); 819 report(expect_interrupts(0), "no overflow interrupt after preset"); 820 821 set_pmcr(pmu.pmcr_ro | PMU_PMCR_E); 822 for (i = 0; i < 100; i++) 823 write_sysreg(0x2, pmswinc_el0); 824 825 set_pmcr(pmu.pmcr_ro); 826 report(expect_interrupts(0), "no overflow interrupt after counting"); 827 828 /* enable interrupts */ 829 830 pmu_reset_stats(); 831 832 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 833 write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); 834 write_sysreg(ALL_SET, pmintenset_el1); 835 isb(); 836 837 mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); 838 for (i = 0; i < 100; i++) 839 write_sysreg(0x3, pmswinc_el0); 840 841 mem_access_loop(addr, 200, pmu.pmcr_ro); 842 report_info("overflow=0x%lx", read_sysreg(pmovsclr_el0)); 843 report(expect_interrupts(0x3), 844 "overflow interrupts expected on #0 and #1"); 845 846 /* promote to 64-b */ 847 848 pmu_reset_stats(); 849 850 write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); 851 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 852 isb(); 853 mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); 854 report(expect_interrupts(0), 855 "no overflow interrupt expected on 32b boundary"); 856 857 /* overflow on odd counter */ 858 pmu_reset_stats(); 859 write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); 860 write_regn_el0(pmevcntr, 1, ALL_SET); 861 isb(); 862 mem_access_loop(addr, 400, pmu.pmcr_ro | PMU_PMCR_E); 863 report(expect_interrupts(0x2), 864 "expect overflow interrupt on odd counter"); 865 } 866 #endif 867 868 /* 869 * Ensure that the cycle counter progresses between back-to-back reads. 870 */ 871 static bool check_cycles_increase(void) 872 { 873 bool success = true; 874 875 /* init before event access, this test only cares about cycle count */ 876 set_pmcntenset(1 << PMU_CYCLE_IDX); 877 set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ 878 879 set_pmcr(get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E); 880 881 for (int i = 0; i < NR_SAMPLES; i++) { 882 uint64_t a, b; 883 884 a = get_pmccntr(); 885 b = get_pmccntr(); 886 887 if (a >= b) { 888 printf("Read %"PRId64" then %"PRId64".\n", a, b); 889 success = false; 890 break; 891 } 892 } 893 894 set_pmcr(get_pmcr() & ~PMU_PMCR_E); 895 896 return success; 897 } 898 899 /* 900 * Execute a known number of guest instructions. Only even instruction counts 901 * greater than or equal to 4 are supported by the in-line assembly code. The 902 * control register (PMCR_EL0) is initialized with the provided value (allowing 903 * for example for the cycle counter or event counters to be reset). At the end 904 * of the exact instruction loop, zero is written to PMCR_EL0 to disable 905 * counting, allowing the cycle counter or event counters to be read at the 906 * leisure of the calling code. 907 */ 908 static void measure_instrs(int num, uint32_t pmcr) 909 { 910 int loop = (num - 2) / 2; 911 912 assert(num >= 4 && ((num - 2) % 2 == 0)); 913 precise_instrs_loop(loop, pmcr); 914 } 915 916 /* 917 * Measure cycle counts for various known instruction counts. Ensure that the 918 * cycle counter progresses (similar to check_cycles_increase() but with more 919 * instructions and using reset and stop controls). If supplied a positive, 920 * nonzero CPI parameter, it also strictly checks that every measurement matches 921 * it. Strict CPI checking is used to test -icount mode. 922 */ 923 static bool check_cpi(int cpi) 924 { 925 uint32_t pmcr = get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E; 926 927 /* init before event access, this test only cares about cycle count */ 928 set_pmcntenset(1 << PMU_CYCLE_IDX); 929 set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ 930 931 if (cpi > 0) 932 printf("Checking for CPI=%d.\n", cpi); 933 printf("instrs : cycles0 cycles1 ...\n"); 934 935 for (unsigned int i = 4; i < 300; i += 32) { 936 uint64_t avg, sum = 0; 937 938 printf("%4d:", i); 939 for (int j = 0; j < NR_SAMPLES; j++) { 940 uint64_t cycles; 941 942 set_pmccntr(0); 943 measure_instrs(i, pmcr); 944 cycles = get_pmccntr(); 945 printf(" %4"PRId64"", cycles); 946 947 if (!cycles) { 948 printf("\ncycles not incrementing!\n"); 949 return false; 950 } else if (cpi > 0 && cycles != i * cpi) { 951 printf("\nunexpected cycle count received!\n"); 952 return false; 953 } else if ((cycles >> 32) != 0) { 954 /* The cycles taken by the loop above should 955 * fit in 32 bits easily. We check the upper 956 * 32 bits of the cycle counter to make sure 957 * there is no supprise. */ 958 printf("\ncycle count bigger than 32bit!\n"); 959 return false; 960 } 961 962 sum += cycles; 963 } 964 avg = sum / NR_SAMPLES; 965 printf(" avg=%-4"PRId64" %s=%-3"PRId64"\n", avg, 966 (avg >= i) ? "cpi" : "ipc", 967 (avg >= i) ? avg / i : i / avg); 968 } 969 970 return true; 971 } 972 973 static void pmccntr64_test(void) 974 { 975 #ifdef __arm__ 976 if (pmu.version == ID_DFR0_PMU_V3) { 977 if (ERRATA(9e3f7a296940)) { 978 write_sysreg(0xdead, PMCCNTR64); 979 report(read_sysreg(PMCCNTR64) == 0xdead, "pmccntr64"); 980 } else 981 report_skip("Skipping unsafe pmccntr64 test. Set ERRATA_9e3f7a296940=y to enable."); 982 } 983 #endif 984 } 985 986 /* Return FALSE if no PMU found, otherwise return TRUE */ 987 static bool pmu_probe(void) 988 { 989 uint32_t pmcr = get_pmcr(); 990 991 pmu.version = get_pmu_version(); 992 if (pmu.version == ID_DFR0_PMU_NOTIMPL || pmu.version == ID_DFR0_PMU_IMPDEF) 993 return false; 994 995 report_info("PMU version: 0x%x", pmu.version); 996 997 pmcr = get_pmcr(); 998 report_info("PMU implementer/ID code: %#x(\"%c\")/%#x", 999 (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK, 1000 ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) ? : ' ', 1001 (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK); 1002 1003 /* store read-only and RES0 fields of the PMCR bottom-half*/ 1004 pmu.pmcr_ro = pmcr & 0xFFFFFF00; 1005 pmu.nb_implemented_counters = 1006 (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK; 1007 report_info("Implements %d event counters", 1008 pmu.nb_implemented_counters); 1009 1010 return true; 1011 } 1012 1013 int main(int argc, char *argv[]) 1014 { 1015 int cpi = 0; 1016 1017 if (!pmu_probe()) { 1018 printf("No PMU found, test skipped...\n"); 1019 return report_summary(); 1020 } 1021 1022 if (argc < 2) 1023 report_abort("no test specified"); 1024 1025 report_prefix_push("pmu"); 1026 1027 if (strcmp(argv[1], "cycle-counter") == 0) { 1028 report_prefix_push(argv[1]); 1029 if (argc > 2) 1030 cpi = atol(argv[2]); 1031 report(check_cycles_increase(), 1032 "Monotonically increasing cycle count"); 1033 report(check_cpi(cpi), "Cycle/instruction ratio"); 1034 pmccntr64_test(); 1035 report_prefix_pop(); 1036 } else if (strcmp(argv[1], "pmu-event-introspection") == 0) { 1037 report_prefix_push(argv[1]); 1038 test_event_introspection(); 1039 report_prefix_pop(); 1040 } else if (strcmp(argv[1], "pmu-event-counter-config") == 0) { 1041 report_prefix_push(argv[1]); 1042 test_event_counter_config(); 1043 report_prefix_pop(); 1044 } else if (strcmp(argv[1], "pmu-basic-event-count") == 0) { 1045 report_prefix_push(argv[1]); 1046 test_basic_event_count(); 1047 report_prefix_pop(); 1048 } else if (strcmp(argv[1], "pmu-mem-access") == 0) { 1049 report_prefix_push(argv[1]); 1050 test_mem_access(); 1051 report_prefix_pop(); 1052 } else if (strcmp(argv[1], "pmu-sw-incr") == 0) { 1053 report_prefix_push(argv[1]); 1054 test_sw_incr(); 1055 report_prefix_pop(); 1056 } else if (strcmp(argv[1], "pmu-chained-counters") == 0) { 1057 report_prefix_push(argv[1]); 1058 test_chained_counters(); 1059 report_prefix_pop(); 1060 } else if (strcmp(argv[1], "pmu-chained-sw-incr") == 0) { 1061 report_prefix_push(argv[1]); 1062 test_chained_sw_incr(); 1063 report_prefix_pop(); 1064 } else if (strcmp(argv[1], "pmu-chain-promotion") == 0) { 1065 report_prefix_push(argv[1]); 1066 test_chain_promotion(); 1067 report_prefix_pop(); 1068 } else if (strcmp(argv[1], "pmu-overflow-interrupt") == 0) { 1069 report_prefix_push(argv[1]); 1070 test_overflow_interrupt(); 1071 report_prefix_pop(); 1072 } else { 1073 report_abort("Unknown sub-test '%s'", argv[1]); 1074 } 1075 1076 return report_summary(); 1077 } 1078