xref: /kvm-unit-tests/arm/cstart64.S (revision 33a6576c6e1bfd98fd35402c9f64dfd7537dd2ff)
1/*
2 * Boot entry point and assembler functions for aarch64 tests.
3 *
4 * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2.
7 */
8#define __ASSEMBLY__
9#include <auxinfo.h>
10#include <asm/asm-offsets.h>
11#include <asm/ptrace.h>
12#include <asm/processor.h>
13#include <asm/page.h>
14#include <asm/pgtable-hwdef.h>
15
16.section .init
17
18/*
19 * Bootloader params are in x0-x3. See kernel doc
20 * Documentation/arm64/booting.txt
21 */
22.globl start
23start:
24	/* get our base address */
25	adrp	x4, start
26	add     x4, x4, :lo12:start
27
28	/*
29	 * Update all R_AARCH64_RELATIVE relocations using the table
30	 * of Elf64_Rela entries between reloc_start/end. The build
31	 * will not emit other relocation types.
32	 *
33	 * struct Elf64_Rela {
34	 * 	uint64_t r_offset;
35	 * 	uint64_t r_info;
36	 * 	int64_t  r_addend;
37	 * }
38	 */
39	adrp	x5, reloc_start
40	add     x5, x5, :lo12:reloc_start
41	adrp	x6, reloc_end
42	add     x6, x6, :lo12:reloc_end
431:
44	cmp	x5, x6
45	b.hs	1f
46	ldr	x7, [x5]			// r_offset
47	ldr	x8, [x5, #16]			// r_addend
48	add	x8, x8, x4			// val = base + r_addend
49	str	x8, [x4, x7]			// base[r_offset] = val
50	add	x5, x5, #24
51	b	1b
52
531:
54	/* set up stack */
55	mov	x4, #1
56	msr	spsel, x4
57	isb
58	adrp    x4, stackptr
59	add     sp, x4, :lo12:stackptr
60
61	/* enable FP/ASIMD */
62	mov	x4, #(3 << 20)
63	msr	cpacr_el1, x4
64
65	/* set up exception handling */
66	bl	exceptions_init
67
68	/* complete setup */
69	bl	setup				// x0 is the addr of the dtb
70	bl	get_mmu_off
71	cbnz	x0, 1f
72	bl	setup_vm
73
741:
75	/* run the test */
76	adrp	x0, __argc
77	ldr	x0, [x0, :lo12:__argc]
78	adrp	x1, __argv
79	add	x1, x1, :lo12:__argv
80	adrp	x2, __environ
81	add	x2, x2, :lo12:__environ
82	bl	main
83	bl	exit
84	b	halt
85
86exceptions_init:
87	adrp	x4, vector_table
88	add	x4, x4, :lo12:vector_table
89	msr	vbar_el1, x4
90	isb
91	ret
92
93.text
94
95.globl get_mmu_off
96get_mmu_off:
97	adrp	x0, auxinfo
98	ldr	x0, [x0, :lo12:auxinfo + 8]
99	and	x0, x0, #AUXINFO_MMU_OFF
100	ret
101
102.globl secondary_entry
103secondary_entry:
104	/* Enable FP/ASIMD */
105	mov	x0, #(3 << 20)
106	msr	cpacr_el1, x0
107
108	/* set up exception handling */
109	bl	exceptions_init
110
111	/* enable the MMU unless requested off */
112	bl	get_mmu_off
113	cbnz	x0, 1f
114	adrp	x0, mmu_idmap
115	ldr	x0, [x0, :lo12:mmu_idmap]
116	bl	asm_mmu_enable
117
1181:
119	/* set the stack */
120	adrp	x0, secondary_data
121	ldr	x0, [x0, :lo12:secondary_data]
122	mov	sp, x0
123
124	/* finish init in C code */
125	bl	secondary_cinit
126
127	/* x0 is now the entry function, run it */
128	blr	x0
129	b	do_idle
130
131.globl halt
132halt:
1331:	wfi
134	b	1b
135
136/*
137 * asm_mmu_enable
138 *   Inputs:
139 *     x0 is the base address of the translation table
140 *   Outputs: none
141 *
142 * Adapted from
143 *   arch/arm64/kernel/head.S
144 *   arch/arm64/mm/proc.S
145 */
146
147/*
148 * Memory region attributes for LPAE:
149 *
150 *   n = AttrIndx[2:0]
151 *                      n       MAIR
152 *   DEVICE_nGnRnE      000     00000000
153 *   DEVICE_nGnRE       001     00000100
154 *   DEVICE_GRE         010     00001100
155 *   NORMAL_NC          011     01000100
156 *   NORMAL             100     11111111
157 */
158#define MAIR(attr, mt) ((attr) << ((mt) * 8))
159
160.globl asm_mmu_enable
161asm_mmu_enable:
162	tlbi	vmalle1			// invalidate I + D TLBs
163	dsb	nsh
164
165	/* TCR */
166	ldr	x1, =TCR_TxSZ(VA_BITS) |		\
167		     TCR_TG0_64K | TCR_TG1_64K |	\
168		     TCR_IRGN_WBWA | TCR_ORGN_WBWA |	\
169		     TCR_SHARED
170	mrs	x2, id_aa64mmfr0_el1
171	bfi	x1, x2, #32, #3
172	msr	tcr_el1, x1
173
174	/* MAIR */
175	ldr	x1, =MAIR(0x00, MT_DEVICE_nGnRnE) |	\
176		     MAIR(0x04, MT_DEVICE_nGnRE) |	\
177		     MAIR(0x0c, MT_DEVICE_GRE) |	\
178		     MAIR(0x44, MT_NORMAL_NC) |		\
179		     MAIR(0xff, MT_NORMAL)
180	msr	mair_el1, x1
181
182	/* TTBR0 */
183	msr	ttbr0_el1, x0
184	isb
185
186	/* SCTLR */
187	mrs	x1, sctlr_el1
188	orr	x1, x1, SCTLR_EL1_C
189	orr	x1, x1, SCTLR_EL1_I
190	orr	x1, x1, SCTLR_EL1_M
191	msr	sctlr_el1, x1
192	isb
193
194	ret
195
196/* Taken with small changes from arch/arm64/incluse/asm/assembler.h */
197.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2
198	adrp	\tmp1, dcache_line_size
199	ldr	\tmp1, [\tmp1, :lo12:dcache_line_size]
200	sub	\tmp2, \tmp1, #1
201	bic	\start, \start, \tmp2
2029998:
203	dc	\op , \start
204	add	\start, \start, \tmp1
205	cmp	\start, \end
206	b.lo	9998b
207	dsb	\domain
208.endm
209
210.globl asm_mmu_disable
211asm_mmu_disable:
212	mrs	x0, sctlr_el1
213	bic	x0, x0, SCTLR_EL1_M
214	msr	sctlr_el1, x0
215	isb
216
217	/* Clean + invalidate the entire memory */
218	adrp	x0, __phys_offset
219	ldr	x0, [x0, :lo12:__phys_offset]
220	adrp	x1, __phys_end
221	ldr	x1, [x1, :lo12:__phys_end]
222	dcache_by_line_op civac, sy, x0, x1, x2, x3
223	isb
224
225	ret
226
227/*
228 * Vectors
229 * Adapted from arch/arm64/kernel/entry.S
230 */
231.macro vector_stub, name, vec
232\name:
233	stp	 x0,  x1, [sp, #-S_FRAME_SIZE]!
234	stp	 x2,  x3, [sp,  #16]
235	stp	 x4,  x5, [sp,  #32]
236	stp	 x6,  x7, [sp,  #48]
237	stp	 x8,  x9, [sp,  #64]
238	stp	x10, x11, [sp,  #80]
239	stp	x12, x13, [sp,  #96]
240	stp	x14, x15, [sp, #112]
241	stp	x16, x17, [sp, #128]
242	stp	x18, x19, [sp, #144]
243	stp	x20, x21, [sp, #160]
244	stp	x22, x23, [sp, #176]
245	stp	x24, x25, [sp, #192]
246	stp	x26, x27, [sp, #208]
247	stp	x28, x29, [sp, #224]
248
249	str	x30, [sp, #S_LR]
250
251	.if \vec >= 8
252	mrs	x1, sp_el0
253	.else
254	add	x1, sp, #S_FRAME_SIZE
255	.endif
256	str	x1, [sp, #S_SP]
257
258	mrs	x1, elr_el1
259	mrs	x2, spsr_el1
260	stp	x1, x2, [sp, #S_PC]
261
262	mov	x0, \vec
263	mov	x1, sp
264	mrs	x2, esr_el1
265	bl	do_handle_exception
266
267	ldp	x1, x2, [sp, #S_PC]
268	msr	spsr_el1, x2
269	msr	elr_el1, x1
270
271	.if \vec >= 8
272	ldr	x1, [sp, #S_SP]
273	msr	sp_el0, x1
274	.endif
275
276	ldr	x30, [sp, #S_LR]
277
278	ldp	x28, x29, [sp, #224]
279	ldp	x26, x27, [sp, #208]
280	ldp	x24, x25, [sp, #192]
281	ldp	x22, x23, [sp, #176]
282	ldp	x20, x21, [sp, #160]
283	ldp	x18, x19, [sp, #144]
284	ldp	x16, x17, [sp, #128]
285	ldp	x14, x15, [sp, #112]
286	ldp	x12, x13, [sp,  #96]
287	ldp	x10, x11, [sp,  #80]
288	ldp	 x8,  x9, [sp,  #64]
289	ldp	 x6,  x7, [sp,  #48]
290	ldp	 x4,  x5, [sp,  #32]
291	ldp	 x2,  x3, [sp,  #16]
292	ldp	 x0,  x1, [sp], #S_FRAME_SIZE
293
294	eret
295.endm
296
297vector_stub	el1t_sync,     0
298vector_stub	el1t_irq,      1
299vector_stub	el1t_fiq,      2
300vector_stub	el1t_error,    3
301
302vector_stub	el1h_sync,     4
303vector_stub	el1h_irq,      5
304vector_stub	el1h_fiq,      6
305vector_stub	el1h_error,    7
306
307vector_stub	el0_sync_64,   8
308vector_stub	el0_irq_64,    9
309vector_stub	el0_fiq_64,   10
310vector_stub	el0_error_64, 11
311
312vector_stub	el0_sync_32,  12
313vector_stub	el0_irq_32,   13
314vector_stub	el0_fiq_32,   14
315vector_stub	el0_error_32, 15
316
317.section .text.ex
318
319.macro ventry, label
320.align 7
321	b	\label
322.endm
323
324.align 11
325vector_table:
326	ventry	el1t_sync			// Synchronous EL1t
327	ventry	el1t_irq			// IRQ EL1t
328	ventry	el1t_fiq			// FIQ EL1t
329	ventry	el1t_error			// Error EL1t
330
331	ventry	el1h_sync			// Synchronous EL1h
332	ventry	el1h_irq			// IRQ EL1h
333	ventry	el1h_fiq			// FIQ EL1h
334	ventry	el1h_error			// Error EL1h
335
336	ventry	el0_sync_64			// Synchronous 64-bit EL0
337	ventry	el0_irq_64			// IRQ 64-bit EL0
338	ventry	el0_fiq_64			// FIQ 64-bit EL0
339	ventry	el0_error_64			// Error 64-bit EL0
340
341	ventry	el0_sync_32			// Synchronous 32-bit EL0
342	ventry	el0_irq_32			// IRQ 32-bit EL0
343	ventry	el0_fiq_32			// FIQ 32-bit EL0
344	ventry	el0_error_32			// Error 32-bit EL0
345