139ac3f84SAndrew Jones/* 239ac3f84SAndrew Jones * Boot entry point and assembler functions for aarch64 tests. 339ac3f84SAndrew Jones * 449f758b8SAndrew Jones * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 539ac3f84SAndrew Jones * 649f758b8SAndrew Jones * This work is licensed under the terms of the GNU GPL, version 2. 739ac3f84SAndrew Jones */ 839ac3f84SAndrew Jones#define __ASSEMBLY__ 962bdc67fSAndrew Jones#include <auxinfo.h> 1039ac3f84SAndrew Jones#include <asm/asm-offsets.h> 11b5f659beSAlexandru Elisei#include <asm/assembler.h> 127ee966e9SAndrew Jones#include <asm/ptrace.h> 13db328a24SAndrew Jones#include <asm/page.h> 14db328a24SAndrew Jones#include <asm/pgtable-hwdef.h> 15993c37beSAndrew Jones#include <asm/thread_info.h> 161dd3501aSAlexandru Elisei#include <asm/sysreg.h> 17993c37beSAndrew Jones 18d231b539SNikos Nikoleris#ifdef CONFIG_EFI 19d231b539SNikos Nikoleris#include "efi/crt0-efi-aarch64.S" 20d231b539SNikos Nikoleris#else 21d231b539SNikos Nikoleris 22993c37beSAndrew Jones.macro zero_range, tmp1, tmp2 23993c37beSAndrew Jones9998: cmp \tmp1, \tmp2 24993c37beSAndrew Jones b.eq 9997f 25993c37beSAndrew Jones stp xzr, xzr, [\tmp1], #16 26993c37beSAndrew Jones b 9998b 27993c37beSAndrew Jones9997: 28993c37beSAndrew Jones.endm 2939ac3f84SAndrew Jones 3039ac3f84SAndrew Jones.section .init 3139ac3f84SAndrew Jones 32f6416021SAndrew Jones/* 33f6416021SAndrew Jones * Bootloader params are in x0-x3. See kernel doc 34f6416021SAndrew Jones * Documentation/arm64/booting.txt 35f6416021SAndrew Jones */ 3639ac3f84SAndrew Jones.globl start 3739ac3f84SAndrew Jonesstart: 38f6416021SAndrew Jones /* get our base address */ 39f6416021SAndrew Jones adrp x4, start 40f6416021SAndrew Jones add x4, x4, :lo12:start 41f6416021SAndrew Jones 4239ac3f84SAndrew Jones /* 43f6416021SAndrew Jones * Update all R_AARCH64_RELATIVE relocations using the table 44f6416021SAndrew Jones * of Elf64_Rela entries between reloc_start/end. The build 45f6416021SAndrew Jones * will not emit other relocation types. 46f6416021SAndrew Jones * 47f6416021SAndrew Jones * struct Elf64_Rela { 48f6416021SAndrew Jones * uint64_t r_offset; 49f6416021SAndrew Jones * uint64_t r_info; 50f6416021SAndrew Jones * int64_t r_addend; 51f6416021SAndrew Jones * } 5239ac3f84SAndrew Jones */ 53f6416021SAndrew Jones adrp x5, reloc_start 54f6416021SAndrew Jones add x5, x5, :lo12:reloc_start 55f6416021SAndrew Jones adrp x6, reloc_end 56f6416021SAndrew Jones add x6, x6, :lo12:reloc_end 57f6416021SAndrew Jones1: 58f6416021SAndrew Jones cmp x5, x6 59f6416021SAndrew Jones b.hs 1f 60f6416021SAndrew Jones ldr x7, [x5] // r_offset 61f6416021SAndrew Jones ldr x8, [x5, #16] // r_addend 62f6416021SAndrew Jones add x8, x8, x4 // val = base + r_addend 63f6416021SAndrew Jones str x8, [x4, x7] // base[r_offset] = val 64f6416021SAndrew Jones add x5, x5, #24 65f6416021SAndrew Jones b 1b 66f6416021SAndrew Jones 67f6416021SAndrew Jones1: 68993c37beSAndrew Jones /* zero BSS */ 69993c37beSAndrew Jones adrp x4, bss 70993c37beSAndrew Jones add x4, x4, :lo12:bss 71993c37beSAndrew Jones adrp x5, ebss 72993c37beSAndrew Jones add x5, x5, :lo12:ebss 73993c37beSAndrew Jones zero_range x4, x5 74993c37beSAndrew Jones 75993c37beSAndrew Jones /* zero and set up stack */ 76993c37beSAndrew Jones adrp x5, stacktop 77993c37beSAndrew Jones add x5, x5, :lo12:stacktop 78993c37beSAndrew Jones sub x4, x5, #THREAD_SIZE 79993c37beSAndrew Jones zero_range x4, x5 8010b65ce7SAlexandru Elisei 8110b65ce7SAlexandru Elisei /* set SCTLR_EL1 to a known value */ 8210b65ce7SAlexandru Elisei ldr x4, =INIT_SCTLR_EL1_MMU_OFF 8310b65ce7SAlexandru Elisei msr sctlr_el1, x4 8410b65ce7SAlexandru Elisei isb 8510b65ce7SAlexandru Elisei 861693644dSAndrew Jones mov x4, #1 871693644dSAndrew Jones msr spsel, x4 8863ab2d70SPaolo Bonzini adrp x4, stackptr 8963ab2d70SPaolo Bonzini add sp, x4, :lo12:stackptr 9039ac3f84SAndrew Jones 91f6416021SAndrew Jones /* enable FP/ASIMD */ 92f6416021SAndrew Jones mov x4, #(3 << 20) 93f6416021SAndrew Jones msr cpacr_el1, x4 9439ac3f84SAndrew Jones 9539ac3f84SAndrew Jones /* set up exception handling */ 967ee966e9SAndrew Jones bl exceptions_init 9739ac3f84SAndrew Jones 9839ac3f84SAndrew Jones /* complete setup */ 995a2a7371SAndrew Jones adrp x1, stacktop 1005a2a7371SAndrew Jones add x1, x1, :lo12:stacktop // x1 is the base of free memory 101f6416021SAndrew Jones bl setup // x0 is the addr of the dtb 10239ac3f84SAndrew Jones 10339ac3f84SAndrew Jones /* run the test */ 10463ab2d70SPaolo Bonzini adrp x0, __argc 105364bb39dSAndrew Jones ldr w0, [x0, :lo12:__argc] 10663ab2d70SPaolo Bonzini adrp x1, __argv 10763ab2d70SPaolo Bonzini add x1, x1, :lo12:__argv 10863ab2d70SPaolo Bonzini adrp x2, __environ 10963ab2d70SPaolo Bonzini add x2, x2, :lo12:__environ 11039ac3f84SAndrew Jones bl main 11139ac3f84SAndrew Jones bl exit 11239ac3f84SAndrew Jones b halt 11339ac3f84SAndrew Jones 114d231b539SNikos Nikoleris#endif 115d231b539SNikos Nikoleris 11639ac3f84SAndrew Jones.text 11739ac3f84SAndrew Jones 118bd5bd157SAndrew Jones/* 119bd5bd157SAndrew Jones * psci_invoke_hvc / psci_invoke_smc 120bd5bd157SAndrew Jones * 121bd5bd157SAndrew Jones * Inputs: 122bd5bd157SAndrew Jones * w0 -- function_id 123bd5bd157SAndrew Jones * x1 -- arg0 124bd5bd157SAndrew Jones * x2 -- arg1 125bd5bd157SAndrew Jones * x3 -- arg2 126bd5bd157SAndrew Jones * 127bd5bd157SAndrew Jones * Outputs: 128bd5bd157SAndrew Jones * x0 -- return code 129bd5bd157SAndrew Jones */ 130bd5bd157SAndrew Jones.globl psci_invoke_hvc 131bd5bd157SAndrew Jonespsci_invoke_hvc: 132bd5bd157SAndrew Jones hvc #0 133bd5bd157SAndrew Jones ret 134bd5bd157SAndrew Jones 135bd5bd157SAndrew Jones.globl psci_invoke_smc 136bd5bd157SAndrew Jonespsci_invoke_smc: 137bd5bd157SAndrew Jones smc #0 138bd5bd157SAndrew Jones ret 139bd5bd157SAndrew Jones 14062bdc67fSAndrew Jonesget_mmu_off: 14162bdc67fSAndrew Jones adrp x0, auxinfo 14262bdc67fSAndrew Jones ldr x0, [x0, :lo12:auxinfo + 8] 14362bdc67fSAndrew Jones and x0, x0, #AUXINFO_MMU_OFF 14462bdc67fSAndrew Jones ret 14562bdc67fSAndrew Jones 14668ea0e0bSAndrew Jones.globl secondary_entry 14768ea0e0bSAndrew Jonessecondary_entry: 14868ea0e0bSAndrew Jones /* Enable FP/ASIMD */ 14968ea0e0bSAndrew Jones mov x0, #(3 << 20) 15068ea0e0bSAndrew Jones msr cpacr_el1, x0 15168ea0e0bSAndrew Jones 15268ea0e0bSAndrew Jones /* set up exception handling */ 15368ea0e0bSAndrew Jones bl exceptions_init 15468ea0e0bSAndrew Jones 15562bdc67fSAndrew Jones /* enable the MMU unless requested off */ 15662bdc67fSAndrew Jones bl get_mmu_off 15762bdc67fSAndrew Jones cbnz x0, 1f 15863ab2d70SPaolo Bonzini adrp x0, mmu_idmap 15963ab2d70SPaolo Bonzini ldr x0, [x0, :lo12:mmu_idmap] 16068ea0e0bSAndrew Jones bl asm_mmu_enable 16168ea0e0bSAndrew Jones 16262bdc67fSAndrew Jones1: 16368ea0e0bSAndrew Jones /* set the stack */ 16463ab2d70SPaolo Bonzini adrp x0, secondary_data 16563ab2d70SPaolo Bonzini ldr x0, [x0, :lo12:secondary_data] 16668ea0e0bSAndrew Jones mov sp, x0 16768ea0e0bSAndrew Jones 16868ea0e0bSAndrew Jones /* finish init in C code */ 16968ea0e0bSAndrew Jones bl secondary_cinit 17068ea0e0bSAndrew Jones 17168ea0e0bSAndrew Jones /* x0 is now the entry function, run it */ 172543ce33cSAndrew Jones blr x0 1739246de4cSAndrew Jones b do_idle 17468ea0e0bSAndrew Jones 17539ac3f84SAndrew Jones.globl halt 17639ac3f84SAndrew Joneshalt: 17739ac3f84SAndrew Jones1: wfi 17839ac3f84SAndrew Jones b 1b 1797ee966e9SAndrew Jones 1807ee966e9SAndrew Jones/* 181db328a24SAndrew Jones * asm_mmu_enable 182db328a24SAndrew Jones * Inputs: 183db328a24SAndrew Jones * x0 is the base address of the translation table 184db328a24SAndrew Jones * Outputs: none 185db328a24SAndrew Jones * 186db328a24SAndrew Jones * Adapted from 187db328a24SAndrew Jones * arch/arm64/kernel/head.S 188db328a24SAndrew Jones * arch/arm64/mm/proc.S 189db328a24SAndrew Jones */ 190db328a24SAndrew Jones 191db328a24SAndrew Jones/* 192db328a24SAndrew Jones * Memory region attributes for LPAE: 193db328a24SAndrew Jones * 194db328a24SAndrew Jones * n = AttrIndx[2:0] 195db328a24SAndrew Jones * n MAIR 196db328a24SAndrew Jones * DEVICE_nGnRnE 000 00000000 197db328a24SAndrew Jones * DEVICE_nGnRE 001 00000100 198db328a24SAndrew Jones * DEVICE_GRE 010 00001100 199db328a24SAndrew Jones * NORMAL_NC 011 01000100 200db328a24SAndrew Jones * NORMAL 100 11111111 201cc70e4b6SNikos Nikoleris * NORMAL_WT 101 10111011 202cc70e4b6SNikos Nikoleris * DEVICE_nGRE 110 00001000 203db328a24SAndrew Jones */ 204db328a24SAndrew Jones#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 205db328a24SAndrew Jones 206a2d06852SNikos Nikoleris#if PAGE_SIZE == SZ_64K 207a2d06852SNikos Nikoleris#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 208a2d06852SNikos Nikoleris#elif PAGE_SIZE == SZ_16K 209a2d06852SNikos Nikoleris#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 210a2d06852SNikos Nikoleris#elif PAGE_SIZE == SZ_4K 211a2d06852SNikos Nikoleris#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 212a2d06852SNikos Nikoleris#endif 213a2d06852SNikos Nikoleris 214db328a24SAndrew Jones.globl asm_mmu_enable 215db328a24SAndrew Jonesasm_mmu_enable: 21642d51704SAlexandru Elisei tlbi vmalle1 // invalidate I + D TLBs 21742d51704SAlexandru Elisei dsb nsh 218db328a24SAndrew Jones 219db328a24SAndrew Jones /* TCR */ 220db328a24SAndrew Jones ldr x1, =TCR_TxSZ(VA_BITS) | \ 221a2d06852SNikos Nikoleris TCR_TG_FLAGS | \ 222db328a24SAndrew Jones TCR_IRGN_WBWA | TCR_ORGN_WBWA | \ 2238425ac5cSAlexandru Elisei TCR_SHARED | \ 2248425ac5cSAlexandru Elisei TCR_EPD1 225d140ad48SAndrew Jones mrs x2, id_aa64mmfr0_el1 226db328a24SAndrew Jones bfi x1, x2, #32, #3 227db328a24SAndrew Jones msr tcr_el1, x1 228db328a24SAndrew Jones 229db328a24SAndrew Jones /* MAIR */ 230db328a24SAndrew Jones ldr x1, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 231db328a24SAndrew Jones MAIR(0x04, MT_DEVICE_nGnRE) | \ 232db328a24SAndrew Jones MAIR(0x0c, MT_DEVICE_GRE) | \ 233db328a24SAndrew Jones MAIR(0x44, MT_NORMAL_NC) | \ 234cc70e4b6SNikos Nikoleris MAIR(0xff, MT_NORMAL) | \ 235cc70e4b6SNikos Nikoleris MAIR(0xbb, MT_NORMAL_WT) | \ 236cc70e4b6SNikos Nikoleris MAIR(0x08, MT_DEVICE_nGRE) 237db328a24SAndrew Jones msr mair_el1, x1 238db328a24SAndrew Jones 239db328a24SAndrew Jones /* TTBR0 */ 240db328a24SAndrew Jones msr ttbr0_el1, x0 241db328a24SAndrew Jones isb 242db328a24SAndrew Jones 243db328a24SAndrew Jones /* SCTLR */ 244db328a24SAndrew Jones mrs x1, sctlr_el1 245db328a24SAndrew Jones orr x1, x1, SCTLR_EL1_C 246db328a24SAndrew Jones orr x1, x1, SCTLR_EL1_I 247db328a24SAndrew Jones orr x1, x1, SCTLR_EL1_M 248db328a24SAndrew Jones msr sctlr_el1, x1 249db328a24SAndrew Jones isb 250db328a24SAndrew Jones 251db328a24SAndrew Jones ret 252db328a24SAndrew Jones 253e27b176bSAndrew Jones.globl asm_mmu_disable 254e27b176bSAndrew Jonesasm_mmu_disable: 255e27b176bSAndrew Jones mrs x0, sctlr_el1 256e27b176bSAndrew Jones bic x0, x0, SCTLR_EL1_M 257e27b176bSAndrew Jones msr sctlr_el1, x0 258e27b176bSAndrew Jones isb 259410b3bf0SAlexandru Elisei 260410b3bf0SAlexandru Elisei /* Clean + invalidate the entire memory */ 261410b3bf0SAlexandru Elisei adrp x0, __phys_offset 262410b3bf0SAlexandru Elisei ldr x0, [x0, :lo12:__phys_offset] 263410b3bf0SAlexandru Elisei adrp x1, __phys_end 264410b3bf0SAlexandru Elisei ldr x1, [x1, :lo12:__phys_end] 265b5f659beSAlexandru Elisei sub x1, x1, x0 266410b3bf0SAlexandru Elisei dcache_by_line_op civac, sy, x0, x1, x2, x3 267410b3bf0SAlexandru Elisei 268e27b176bSAndrew Jones ret 269e27b176bSAndrew Jones 270db328a24SAndrew Jones/* 2717ee966e9SAndrew Jones * Vectors 2722da0f98cSAndrew Jones */ 2732da0f98cSAndrew Jones 27423e17626SNikos Nikoleris.globl exceptions_init 2752da0f98cSAndrew Jonesexceptions_init: 2762da0f98cSAndrew Jones adrp x4, vector_table 2772da0f98cSAndrew Jones add x4, x4, :lo12:vector_table 2782da0f98cSAndrew Jones msr vbar_el1, x4 2792da0f98cSAndrew Jones isb 2802da0f98cSAndrew Jones ret 2812da0f98cSAndrew Jones 2822da0f98cSAndrew Jones/* 2832da0f98cSAndrew Jones * Vector stubs 2847ee966e9SAndrew Jones * Adapted from arch/arm64/kernel/entry.S 285332b6216SNikos Nikoleris * Declare as weak to allow external tests to redefine and override a 286332b6216SNikos Nikoleris * vector_stub. 2877ee966e9SAndrew Jones */ 2887ee966e9SAndrew Jones.macro vector_stub, name, vec 289332b6216SNikos Nikoleris.weak \name 2907ee966e9SAndrew Jones\name: 2917ee966e9SAndrew Jones stp x0, x1, [sp, #-S_FRAME_SIZE]! 2927ee966e9SAndrew Jones stp x2, x3, [sp, #16] 2937ee966e9SAndrew Jones stp x4, x5, [sp, #32] 2947ee966e9SAndrew Jones stp x6, x7, [sp, #48] 2957ee966e9SAndrew Jones stp x8, x9, [sp, #64] 2967ee966e9SAndrew Jones stp x10, x11, [sp, #80] 2977ee966e9SAndrew Jones stp x12, x13, [sp, #96] 2987ee966e9SAndrew Jones stp x14, x15, [sp, #112] 2997ee966e9SAndrew Jones stp x16, x17, [sp, #128] 3007ee966e9SAndrew Jones stp x18, x19, [sp, #144] 3017ee966e9SAndrew Jones stp x20, x21, [sp, #160] 3027ee966e9SAndrew Jones stp x22, x23, [sp, #176] 3037ee966e9SAndrew Jones stp x24, x25, [sp, #192] 3047ee966e9SAndrew Jones stp x26, x27, [sp, #208] 3057ee966e9SAndrew Jones stp x28, x29, [sp, #224] 3067ee966e9SAndrew Jones 3077ee966e9SAndrew Jones str x30, [sp, #S_LR] 3087ee966e9SAndrew Jones 3097ee966e9SAndrew Jones .if \vec >= 8 3107ee966e9SAndrew Jones mrs x1, sp_el0 3117ee966e9SAndrew Jones .else 3127ee966e9SAndrew Jones add x1, sp, #S_FRAME_SIZE 3137ee966e9SAndrew Jones .endif 3147ee966e9SAndrew Jones str x1, [sp, #S_SP] 3157ee966e9SAndrew Jones 3167ee966e9SAndrew Jones mrs x1, elr_el1 3177ee966e9SAndrew Jones mrs x2, spsr_el1 3187ee966e9SAndrew Jones stp x1, x2, [sp, #S_PC] 3197ee966e9SAndrew Jones 320*ecb5e711SNadav Amit /* 321*ecb5e711SNadav Amit * Save a frame pointer using the link to allow unwinding of 322*ecb5e711SNadav Amit * exceptions. 323*ecb5e711SNadav Amit */ 324*ecb5e711SNadav Amit stp x29, x1, [sp, #S_FP] 325*ecb5e711SNadav Amit add x29, sp, #S_FP 326*ecb5e711SNadav Amit 327f6d10793SAndrew Jones mov x0, \vec 3287ee966e9SAndrew Jones mov x1, sp 3297ee966e9SAndrew Jones mrs x2, esr_el1 3307ee966e9SAndrew Jones bl do_handle_exception 3317ee966e9SAndrew Jones 3327ee966e9SAndrew Jones ldp x1, x2, [sp, #S_PC] 3337ee966e9SAndrew Jones msr spsr_el1, x2 3347ee966e9SAndrew Jones msr elr_el1, x1 3357ee966e9SAndrew Jones 3367ee966e9SAndrew Jones .if \vec >= 8 3377ee966e9SAndrew Jones ldr x1, [sp, #S_SP] 3387ee966e9SAndrew Jones msr sp_el0, x1 3397ee966e9SAndrew Jones .endif 3407ee966e9SAndrew Jones 3417ee966e9SAndrew Jones ldr x30, [sp, #S_LR] 3427ee966e9SAndrew Jones 3437ee966e9SAndrew Jones ldp x28, x29, [sp, #224] 3447ee966e9SAndrew Jones ldp x26, x27, [sp, #208] 3457ee966e9SAndrew Jones ldp x24, x25, [sp, #192] 3467ee966e9SAndrew Jones ldp x22, x23, [sp, #176] 3477ee966e9SAndrew Jones ldp x20, x21, [sp, #160] 3487ee966e9SAndrew Jones ldp x18, x19, [sp, #144] 3497ee966e9SAndrew Jones ldp x16, x17, [sp, #128] 3507ee966e9SAndrew Jones ldp x14, x15, [sp, #112] 3517ee966e9SAndrew Jones ldp x12, x13, [sp, #96] 3527ee966e9SAndrew Jones ldp x10, x11, [sp, #80] 3537ee966e9SAndrew Jones ldp x8, x9, [sp, #64] 3547ee966e9SAndrew Jones ldp x6, x7, [sp, #48] 3557ee966e9SAndrew Jones ldp x4, x5, [sp, #32] 3567ee966e9SAndrew Jones ldp x2, x3, [sp, #16] 3577ee966e9SAndrew Jones ldp x0, x1, [sp], #S_FRAME_SIZE 3587ee966e9SAndrew Jones 3597ee966e9SAndrew Jones eret 3607ee966e9SAndrew Jones.endm 3617ee966e9SAndrew Jones 362*ecb5e711SNadav Amit.globl vector_stub_start 363*ecb5e711SNadav Amitvector_stub_start: 364*ecb5e711SNadav Amit 3657ee966e9SAndrew Jonesvector_stub el1t_sync, 0 3667ee966e9SAndrew Jonesvector_stub el1t_irq, 1 3677ee966e9SAndrew Jonesvector_stub el1t_fiq, 2 3687ee966e9SAndrew Jonesvector_stub el1t_error, 3 3697ee966e9SAndrew Jones 3707ee966e9SAndrew Jonesvector_stub el1h_sync, 4 3717ee966e9SAndrew Jonesvector_stub el1h_irq, 5 3727ee966e9SAndrew Jonesvector_stub el1h_fiq, 6 3737ee966e9SAndrew Jonesvector_stub el1h_error, 7 3747ee966e9SAndrew Jones 3757ee966e9SAndrew Jonesvector_stub el0_sync_64, 8 3767ee966e9SAndrew Jonesvector_stub el0_irq_64, 9 3777ee966e9SAndrew Jonesvector_stub el0_fiq_64, 10 3787ee966e9SAndrew Jonesvector_stub el0_error_64, 11 3797ee966e9SAndrew Jones 3807ee966e9SAndrew Jonesvector_stub el0_sync_32, 12 3817ee966e9SAndrew Jonesvector_stub el0_irq_32, 13 3827ee966e9SAndrew Jonesvector_stub el0_fiq_32, 14 3837ee966e9SAndrew Jonesvector_stub el0_error_32, 15 3847ee966e9SAndrew Jones 385*ecb5e711SNadav Amit.globl vector_stub_end 386*ecb5e711SNadav Amitvector_stub_end: 387*ecb5e711SNadav Amit 3887ee966e9SAndrew Jones.section .text.ex 3897ee966e9SAndrew Jones 3907ee966e9SAndrew Jones.macro ventry, label 3917ee966e9SAndrew Jones.align 7 3927ee966e9SAndrew Jones b \label 3937ee966e9SAndrew Jones.endm 3947ee966e9SAndrew Jones 395332b6216SNikos Nikoleris 396332b6216SNikos Nikoleris/* 397332b6216SNikos Nikoleris * Declare as weak to allow external tests to redefine and override the 398332b6216SNikos Nikoleris * default vector table. 399332b6216SNikos Nikoleris */ 4007ee966e9SAndrew Jones.align 11 401332b6216SNikos Nikoleris.weak vector_table 4027ee966e9SAndrew Jonesvector_table: 4037ee966e9SAndrew Jones ventry el1t_sync // Synchronous EL1t 4047ee966e9SAndrew Jones ventry el1t_irq // IRQ EL1t 4057ee966e9SAndrew Jones ventry el1t_fiq // FIQ EL1t 4067ee966e9SAndrew Jones ventry el1t_error // Error EL1t 4077ee966e9SAndrew Jones 4087ee966e9SAndrew Jones ventry el1h_sync // Synchronous EL1h 4097ee966e9SAndrew Jones ventry el1h_irq // IRQ EL1h 4107ee966e9SAndrew Jones ventry el1h_fiq // FIQ EL1h 4117ee966e9SAndrew Jones ventry el1h_error // Error EL1h 4127ee966e9SAndrew Jones 4137ee966e9SAndrew Jones ventry el0_sync_64 // Synchronous 64-bit EL0 4147ee966e9SAndrew Jones ventry el0_irq_64 // IRQ 64-bit EL0 4157ee966e9SAndrew Jones ventry el0_fiq_64 // FIQ 64-bit EL0 4167ee966e9SAndrew Jones ventry el0_error_64 // Error 64-bit EL0 4177ee966e9SAndrew Jones 4187ee966e9SAndrew Jones ventry el0_sync_32 // Synchronous 32-bit EL0 4197ee966e9SAndrew Jones ventry el0_irq_32 // IRQ 32-bit EL0 4207ee966e9SAndrew Jones ventry el0_fiq_32 // FIQ 32-bit EL0 4217ee966e9SAndrew Jones ventry el0_error_32 // Error 32-bit EL0 422