139ac3f84SAndrew Jones/* 239ac3f84SAndrew Jones * Boot entry point and assembler functions for aarch64 tests. 339ac3f84SAndrew Jones * 449f758b8SAndrew Jones * Copyright (C) 2017, Red Hat Inc, Andrew Jones <drjones@redhat.com> 539ac3f84SAndrew Jones * 649f758b8SAndrew Jones * This work is licensed under the terms of the GNU GPL, version 2. 739ac3f84SAndrew Jones */ 839ac3f84SAndrew Jones#define __ASSEMBLY__ 962bdc67fSAndrew Jones#include <auxinfo.h> 1039ac3f84SAndrew Jones#include <asm/asm-offsets.h> 11b5f659beSAlexandru Elisei#include <asm/assembler.h> 127ee966e9SAndrew Jones#include <asm/ptrace.h> 13db328a24SAndrew Jones#include <asm/page.h> 14db328a24SAndrew Jones#include <asm/pgtable-hwdef.h> 15993c37beSAndrew Jones#include <asm/thread_info.h> 161dd3501aSAlexandru Elisei#include <asm/sysreg.h> 17993c37beSAndrew Jones 18d231b539SNikos Nikoleris#ifdef CONFIG_EFI 19d231b539SNikos Nikoleris#include "efi/crt0-efi-aarch64.S" 20d231b539SNikos Nikoleris#else 21d231b539SNikos Nikoleris 22993c37beSAndrew Jones.macro zero_range, tmp1, tmp2 23993c37beSAndrew Jones9998: cmp \tmp1, \tmp2 24993c37beSAndrew Jones b.eq 9997f 25993c37beSAndrew Jones stp xzr, xzr, [\tmp1], #16 26993c37beSAndrew Jones b 9998b 27993c37beSAndrew Jones9997: 28993c37beSAndrew Jones.endm 2939ac3f84SAndrew Jones 3039ac3f84SAndrew Jones.section .init 3139ac3f84SAndrew Jones 32f6416021SAndrew Jones/* 33f6416021SAndrew Jones * Bootloader params are in x0-x3. See kernel doc 34f6416021SAndrew Jones * Documentation/arm64/booting.txt 35f6416021SAndrew Jones */ 3639ac3f84SAndrew Jones.globl start 3739ac3f84SAndrew Jonesstart: 38f6416021SAndrew Jones /* get our base address */ 39f6416021SAndrew Jones adrp x4, start 40f6416021SAndrew Jones add x4, x4, :lo12:start 41f6416021SAndrew Jones 4239ac3f84SAndrew Jones /* 43f6416021SAndrew Jones * Update all R_AARCH64_RELATIVE relocations using the table 44f6416021SAndrew Jones * of Elf64_Rela entries between reloc_start/end. The build 45f6416021SAndrew Jones * will not emit other relocation types. 46f6416021SAndrew Jones * 47f6416021SAndrew Jones * struct Elf64_Rela { 48f6416021SAndrew Jones * uint64_t r_offset; 49f6416021SAndrew Jones * uint64_t r_info; 50f6416021SAndrew Jones * int64_t r_addend; 51f6416021SAndrew Jones * } 5239ac3f84SAndrew Jones */ 53f6416021SAndrew Jones adrp x5, reloc_start 54f6416021SAndrew Jones add x5, x5, :lo12:reloc_start 55f6416021SAndrew Jones adrp x6, reloc_end 56f6416021SAndrew Jones add x6, x6, :lo12:reloc_end 57f6416021SAndrew Jones1: 58f6416021SAndrew Jones cmp x5, x6 59f6416021SAndrew Jones b.hs 1f 60f6416021SAndrew Jones ldr x7, [x5] // r_offset 61f6416021SAndrew Jones ldr x8, [x5, #16] // r_addend 62f6416021SAndrew Jones add x8, x8, x4 // val = base + r_addend 63f6416021SAndrew Jones str x8, [x4, x7] // base[r_offset] = val 64f6416021SAndrew Jones add x5, x5, #24 65f6416021SAndrew Jones b 1b 66f6416021SAndrew Jones 67f6416021SAndrew Jones1: 68993c37beSAndrew Jones /* zero BSS */ 69993c37beSAndrew Jones adrp x4, bss 70993c37beSAndrew Jones add x4, x4, :lo12:bss 71993c37beSAndrew Jones adrp x5, ebss 72993c37beSAndrew Jones add x5, x5, :lo12:ebss 73993c37beSAndrew Jones zero_range x4, x5 74993c37beSAndrew Jones 75993c37beSAndrew Jones /* zero and set up stack */ 76993c37beSAndrew Jones adrp x5, stacktop 77993c37beSAndrew Jones add x5, x5, :lo12:stacktop 78993c37beSAndrew Jones sub x4, x5, #THREAD_SIZE 79993c37beSAndrew Jones zero_range x4, x5 8010b65ce7SAlexandru Elisei 8110b65ce7SAlexandru Elisei /* set SCTLR_EL1 to a known value */ 8210b65ce7SAlexandru Elisei ldr x4, =INIT_SCTLR_EL1_MMU_OFF 8310b65ce7SAlexandru Elisei msr sctlr_el1, x4 8410b65ce7SAlexandru Elisei isb 8510b65ce7SAlexandru Elisei 861693644dSAndrew Jones mov x4, #1 871693644dSAndrew Jones msr spsel, x4 8863ab2d70SPaolo Bonzini adrp x4, stackptr 8963ab2d70SPaolo Bonzini add sp, x4, :lo12:stackptr 9039ac3f84SAndrew Jones 91f6416021SAndrew Jones /* enable FP/ASIMD */ 92f6416021SAndrew Jones mov x4, #(3 << 20) 93f6416021SAndrew Jones msr cpacr_el1, x4 9439ac3f84SAndrew Jones 9539ac3f84SAndrew Jones /* set up exception handling */ 967ee966e9SAndrew Jones bl exceptions_init 9739ac3f84SAndrew Jones 9839ac3f84SAndrew Jones /* complete setup */ 995a2a7371SAndrew Jones adrp x1, stacktop 1005a2a7371SAndrew Jones add x1, x1, :lo12:stacktop // x1 is the base of free memory 101f6416021SAndrew Jones bl setup // x0 is the addr of the dtb 10239ac3f84SAndrew Jones 10339ac3f84SAndrew Jones /* run the test */ 10463ab2d70SPaolo Bonzini adrp x0, __argc 105364bb39dSAndrew Jones ldr w0, [x0, :lo12:__argc] 10663ab2d70SPaolo Bonzini adrp x1, __argv 10763ab2d70SPaolo Bonzini add x1, x1, :lo12:__argv 10863ab2d70SPaolo Bonzini adrp x2, __environ 10963ab2d70SPaolo Bonzini add x2, x2, :lo12:__environ 11039ac3f84SAndrew Jones bl main 11139ac3f84SAndrew Jones bl exit 11239ac3f84SAndrew Jones b halt 11339ac3f84SAndrew Jones 114d231b539SNikos Nikoleris#endif 115d231b539SNikos Nikoleris 11639ac3f84SAndrew Jones.text 11739ac3f84SAndrew Jones 118bd5bd157SAndrew Jones/* 119*cddb18bcSAlexandru Elisei * arm_smccc_hvc / arm_smccc_smc 120bd5bd157SAndrew Jones * 121bd5bd157SAndrew Jones * Inputs: 122bd5bd157SAndrew Jones * w0 -- function_id 123bd5bd157SAndrew Jones * x1 -- arg0 124bd5bd157SAndrew Jones * x2 -- arg1 125bd5bd157SAndrew Jones * x3 -- arg2 126*cddb18bcSAlexandru Elisei * x4 -- arg3 127*cddb18bcSAlexandru Elisei * x5 -- arg4 128*cddb18bcSAlexandru Elisei * x6 -- arg5 129*cddb18bcSAlexandru Elisei * x7 -- arg6 130*cddb18bcSAlexandru Elisei * sp -- { arg7, arg8, arg9, arg10, result } 131bd5bd157SAndrew Jones * 132bd5bd157SAndrew Jones * Outputs: 133bd5bd157SAndrew Jones * x0 -- return code 134*cddb18bcSAlexandru Elisei * 135*cddb18bcSAlexandru Elisei * If result pointer is not NULL: 136*cddb18bcSAlexandru Elisei * result.r0 -- return code 137*cddb18bcSAlexandru Elisei * result.r1 -- x1 138*cddb18bcSAlexandru Elisei * result.r2 -- x2 139*cddb18bcSAlexandru Elisei * result.r3 -- x3 140*cddb18bcSAlexandru Elisei * result.r4 -- x4 141*cddb18bcSAlexandru Elisei * result.r5 -- x5 142*cddb18bcSAlexandru Elisei * result.r6 -- x6 143*cddb18bcSAlexandru Elisei * result.r7 -- x7 144*cddb18bcSAlexandru Elisei * result.r8 -- x8 145*cddb18bcSAlexandru Elisei * result.r9 -- x9 146bd5bd157SAndrew Jones */ 147*cddb18bcSAlexandru Elisei.macro do_smccc_call instr 148*cddb18bcSAlexandru Elisei /* Save x8-x11 on stack */ 149*cddb18bcSAlexandru Elisei stp x9, x8, [sp, #-16]! 150*cddb18bcSAlexandru Elisei stp x11, x10, [sp, #-16]! 151*cddb18bcSAlexandru Elisei /* Load arg7 - arg10 from the stack */ 152*cddb18bcSAlexandru Elisei ldp x8, x9, [sp, #32] 153*cddb18bcSAlexandru Elisei ldp x10, x11, [sp, #48] 154*cddb18bcSAlexandru Elisei \instr #0 155*cddb18bcSAlexandru Elisei /* Get the result address */ 156*cddb18bcSAlexandru Elisei ldr x10, [sp, #64] 157*cddb18bcSAlexandru Elisei cmp x10, xzr 158*cddb18bcSAlexandru Elisei b.eq 1f 159*cddb18bcSAlexandru Elisei stp x0, x1, [x10, #0] 160*cddb18bcSAlexandru Elisei stp x2, x3, [x10, #16] 161*cddb18bcSAlexandru Elisei stp x4, x5, [x10, #32] 162*cddb18bcSAlexandru Elisei stp x6, x7, [x10, #48] 163*cddb18bcSAlexandru Elisei stp x8, x9, [x10, #64] 164*cddb18bcSAlexandru Elisei1: 165*cddb18bcSAlexandru Elisei /* Restore x8-x11 from stack */ 166*cddb18bcSAlexandru Elisei ldp x11, x10, [sp], #16 167*cddb18bcSAlexandru Elisei ldp x9, x8, [sp], #16 168bd5bd157SAndrew Jones ret 169*cddb18bcSAlexandru Elisei.endm 170bd5bd157SAndrew Jones 171*cddb18bcSAlexandru Elisei.globl arm_smccc_hvc 172*cddb18bcSAlexandru Eliseiarm_smccc_hvc: 173*cddb18bcSAlexandru Elisei do_smccc_call hvc 174*cddb18bcSAlexandru Elisei 175*cddb18bcSAlexandru Elisei.globl arm_smccc_smc 176*cddb18bcSAlexandru Eliseiarm_smccc_smc: 177*cddb18bcSAlexandru Elisei do_smccc_call smc 178bd5bd157SAndrew Jones 17962bdc67fSAndrew Jonesget_mmu_off: 18062bdc67fSAndrew Jones adrp x0, auxinfo 18162bdc67fSAndrew Jones ldr x0, [x0, :lo12:auxinfo + 8] 18262bdc67fSAndrew Jones and x0, x0, #AUXINFO_MMU_OFF 18362bdc67fSAndrew Jones ret 18462bdc67fSAndrew Jones 18568ea0e0bSAndrew Jones.globl secondary_entry 18668ea0e0bSAndrew Jonessecondary_entry: 18768ea0e0bSAndrew Jones /* Enable FP/ASIMD */ 18868ea0e0bSAndrew Jones mov x0, #(3 << 20) 18968ea0e0bSAndrew Jones msr cpacr_el1, x0 19068ea0e0bSAndrew Jones 19168ea0e0bSAndrew Jones /* set up exception handling */ 19268ea0e0bSAndrew Jones bl exceptions_init 19368ea0e0bSAndrew Jones 19462bdc67fSAndrew Jones /* enable the MMU unless requested off */ 19562bdc67fSAndrew Jones bl get_mmu_off 19662bdc67fSAndrew Jones cbnz x0, 1f 19763ab2d70SPaolo Bonzini adrp x0, mmu_idmap 19863ab2d70SPaolo Bonzini ldr x0, [x0, :lo12:mmu_idmap] 19968ea0e0bSAndrew Jones bl asm_mmu_enable 20068ea0e0bSAndrew Jones 20162bdc67fSAndrew Jones1: 20268ea0e0bSAndrew Jones /* set the stack */ 20363ab2d70SPaolo Bonzini adrp x0, secondary_data 20463ab2d70SPaolo Bonzini ldr x0, [x0, :lo12:secondary_data] 20568ea0e0bSAndrew Jones mov sp, x0 20668ea0e0bSAndrew Jones 20768ea0e0bSAndrew Jones /* finish init in C code */ 20868ea0e0bSAndrew Jones bl secondary_cinit 20968ea0e0bSAndrew Jones 21068ea0e0bSAndrew Jones /* x0 is now the entry function, run it */ 211543ce33cSAndrew Jones blr x0 2129246de4cSAndrew Jones b do_idle 21368ea0e0bSAndrew Jones 21439ac3f84SAndrew Jones.globl halt 21539ac3f84SAndrew Joneshalt: 21639ac3f84SAndrew Jones1: wfi 21739ac3f84SAndrew Jones b 1b 2187ee966e9SAndrew Jones 2197ee966e9SAndrew Jones/* 220db328a24SAndrew Jones * asm_mmu_enable 221db328a24SAndrew Jones * Inputs: 222db328a24SAndrew Jones * x0 is the base address of the translation table 223db328a24SAndrew Jones * Outputs: none 224db328a24SAndrew Jones * 225db328a24SAndrew Jones * Adapted from 226db328a24SAndrew Jones * arch/arm64/kernel/head.S 227db328a24SAndrew Jones * arch/arm64/mm/proc.S 228db328a24SAndrew Jones */ 229db328a24SAndrew Jones 230db328a24SAndrew Jones/* 231db328a24SAndrew Jones * Memory region attributes for LPAE: 232db328a24SAndrew Jones * 233db328a24SAndrew Jones * n = AttrIndx[2:0] 234db328a24SAndrew Jones * n MAIR 235db328a24SAndrew Jones * DEVICE_nGnRnE 000 00000000 236db328a24SAndrew Jones * DEVICE_nGnRE 001 00000100 237db328a24SAndrew Jones * DEVICE_GRE 010 00001100 238db328a24SAndrew Jones * NORMAL_NC 011 01000100 239db328a24SAndrew Jones * NORMAL 100 11111111 240cc70e4b6SNikos Nikoleris * NORMAL_WT 101 10111011 241cc70e4b6SNikos Nikoleris * DEVICE_nGRE 110 00001000 242db328a24SAndrew Jones */ 243db328a24SAndrew Jones#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 244db328a24SAndrew Jones 245a2d06852SNikos Nikoleris#if PAGE_SIZE == SZ_64K 246a2d06852SNikos Nikoleris#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 247a2d06852SNikos Nikoleris#elif PAGE_SIZE == SZ_16K 248a2d06852SNikos Nikoleris#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K 249a2d06852SNikos Nikoleris#elif PAGE_SIZE == SZ_4K 250a2d06852SNikos Nikoleris#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 251a2d06852SNikos Nikoleris#endif 252a2d06852SNikos Nikoleris 253db328a24SAndrew Jones.globl asm_mmu_enable 254db328a24SAndrew Jonesasm_mmu_enable: 25542d51704SAlexandru Elisei tlbi vmalle1 // invalidate I + D TLBs 25642d51704SAlexandru Elisei dsb nsh 257db328a24SAndrew Jones 258db328a24SAndrew Jones /* TCR */ 259db328a24SAndrew Jones ldr x1, =TCR_TxSZ(VA_BITS) | \ 260a2d06852SNikos Nikoleris TCR_TG_FLAGS | \ 261db328a24SAndrew Jones TCR_IRGN_WBWA | TCR_ORGN_WBWA | \ 2628425ac5cSAlexandru Elisei TCR_SHARED | \ 2638425ac5cSAlexandru Elisei TCR_EPD1 264d140ad48SAndrew Jones mrs x2, id_aa64mmfr0_el1 265db328a24SAndrew Jones bfi x1, x2, #32, #3 266db328a24SAndrew Jones msr tcr_el1, x1 267db328a24SAndrew Jones 268db328a24SAndrew Jones /* MAIR */ 269db328a24SAndrew Jones ldr x1, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 270db328a24SAndrew Jones MAIR(0x04, MT_DEVICE_nGnRE) | \ 271db328a24SAndrew Jones MAIR(0x0c, MT_DEVICE_GRE) | \ 272db328a24SAndrew Jones MAIR(0x44, MT_NORMAL_NC) | \ 273cc70e4b6SNikos Nikoleris MAIR(0xff, MT_NORMAL) | \ 274cc70e4b6SNikos Nikoleris MAIR(0xbb, MT_NORMAL_WT) | \ 275cc70e4b6SNikos Nikoleris MAIR(0x08, MT_DEVICE_nGRE) 276db328a24SAndrew Jones msr mair_el1, x1 277db328a24SAndrew Jones 278db328a24SAndrew Jones /* TTBR0 */ 279db328a24SAndrew Jones msr ttbr0_el1, x0 280db328a24SAndrew Jones isb 281db328a24SAndrew Jones 282db328a24SAndrew Jones /* SCTLR */ 283db328a24SAndrew Jones mrs x1, sctlr_el1 284db328a24SAndrew Jones orr x1, x1, SCTLR_EL1_C 285db328a24SAndrew Jones orr x1, x1, SCTLR_EL1_I 286db328a24SAndrew Jones orr x1, x1, SCTLR_EL1_M 287db328a24SAndrew Jones msr sctlr_el1, x1 288db328a24SAndrew Jones isb 289db328a24SAndrew Jones 290db328a24SAndrew Jones ret 291db328a24SAndrew Jones 292e27b176bSAndrew Jones.globl asm_mmu_disable 293e27b176bSAndrew Jonesasm_mmu_disable: 294e27b176bSAndrew Jones mrs x0, sctlr_el1 295e27b176bSAndrew Jones bic x0, x0, SCTLR_EL1_M 296e27b176bSAndrew Jones msr sctlr_el1, x0 297e27b176bSAndrew Jones isb 298410b3bf0SAlexandru Elisei 299410b3bf0SAlexandru Elisei /* Clean + invalidate the entire memory */ 300410b3bf0SAlexandru Elisei adrp x0, __phys_offset 301410b3bf0SAlexandru Elisei ldr x0, [x0, :lo12:__phys_offset] 302410b3bf0SAlexandru Elisei adrp x1, __phys_end 303410b3bf0SAlexandru Elisei ldr x1, [x1, :lo12:__phys_end] 304b5f659beSAlexandru Elisei sub x1, x1, x0 305410b3bf0SAlexandru Elisei dcache_by_line_op civac, sy, x0, x1, x2, x3 306410b3bf0SAlexandru Elisei 307e27b176bSAndrew Jones ret 308e27b176bSAndrew Jones 309db328a24SAndrew Jones/* 3107ee966e9SAndrew Jones * Vectors 3112da0f98cSAndrew Jones */ 3122da0f98cSAndrew Jones 31323e17626SNikos Nikoleris.globl exceptions_init 3142da0f98cSAndrew Jonesexceptions_init: 3152da0f98cSAndrew Jones adrp x4, vector_table 3162da0f98cSAndrew Jones add x4, x4, :lo12:vector_table 3172da0f98cSAndrew Jones msr vbar_el1, x4 3182da0f98cSAndrew Jones isb 3192da0f98cSAndrew Jones ret 3202da0f98cSAndrew Jones 3212da0f98cSAndrew Jones/* 3222da0f98cSAndrew Jones * Vector stubs 3237ee966e9SAndrew Jones * Adapted from arch/arm64/kernel/entry.S 324332b6216SNikos Nikoleris * Declare as weak to allow external tests to redefine and override a 325332b6216SNikos Nikoleris * vector_stub. 3267ee966e9SAndrew Jones */ 3277ee966e9SAndrew Jones.macro vector_stub, name, vec 328332b6216SNikos Nikoleris.weak \name 3297ee966e9SAndrew Jones\name: 3307ee966e9SAndrew Jones stp x0, x1, [sp, #-S_FRAME_SIZE]! 3317ee966e9SAndrew Jones stp x2, x3, [sp, #16] 3327ee966e9SAndrew Jones stp x4, x5, [sp, #32] 3337ee966e9SAndrew Jones stp x6, x7, [sp, #48] 3347ee966e9SAndrew Jones stp x8, x9, [sp, #64] 3357ee966e9SAndrew Jones stp x10, x11, [sp, #80] 3367ee966e9SAndrew Jones stp x12, x13, [sp, #96] 3377ee966e9SAndrew Jones stp x14, x15, [sp, #112] 3387ee966e9SAndrew Jones stp x16, x17, [sp, #128] 3397ee966e9SAndrew Jones stp x18, x19, [sp, #144] 3407ee966e9SAndrew Jones stp x20, x21, [sp, #160] 3417ee966e9SAndrew Jones stp x22, x23, [sp, #176] 3427ee966e9SAndrew Jones stp x24, x25, [sp, #192] 3437ee966e9SAndrew Jones stp x26, x27, [sp, #208] 3447ee966e9SAndrew Jones stp x28, x29, [sp, #224] 3457ee966e9SAndrew Jones 3467ee966e9SAndrew Jones str x30, [sp, #S_LR] 3477ee966e9SAndrew Jones 3487ee966e9SAndrew Jones .if \vec >= 8 3497ee966e9SAndrew Jones mrs x1, sp_el0 3507ee966e9SAndrew Jones .else 3517ee966e9SAndrew Jones add x1, sp, #S_FRAME_SIZE 3527ee966e9SAndrew Jones .endif 3537ee966e9SAndrew Jones str x1, [sp, #S_SP] 3547ee966e9SAndrew Jones 3557ee966e9SAndrew Jones mrs x1, elr_el1 3567ee966e9SAndrew Jones mrs x2, spsr_el1 3577ee966e9SAndrew Jones stp x1, x2, [sp, #S_PC] 3587ee966e9SAndrew Jones 359ecb5e711SNadav Amit /* 360ecb5e711SNadav Amit * Save a frame pointer using the link to allow unwinding of 361ecb5e711SNadav Amit * exceptions. 362ecb5e711SNadav Amit */ 363ecb5e711SNadav Amit stp x29, x1, [sp, #S_FP] 364ecb5e711SNadav Amit add x29, sp, #S_FP 365ecb5e711SNadav Amit 366f6d10793SAndrew Jones mov x0, \vec 3677ee966e9SAndrew Jones mov x1, sp 3687ee966e9SAndrew Jones mrs x2, esr_el1 3697ee966e9SAndrew Jones bl do_handle_exception 3707ee966e9SAndrew Jones 3717ee966e9SAndrew Jones ldp x1, x2, [sp, #S_PC] 3727ee966e9SAndrew Jones msr spsr_el1, x2 3737ee966e9SAndrew Jones msr elr_el1, x1 3747ee966e9SAndrew Jones 3757ee966e9SAndrew Jones .if \vec >= 8 3767ee966e9SAndrew Jones ldr x1, [sp, #S_SP] 3777ee966e9SAndrew Jones msr sp_el0, x1 3787ee966e9SAndrew Jones .endif 3797ee966e9SAndrew Jones 3807ee966e9SAndrew Jones ldr x30, [sp, #S_LR] 3817ee966e9SAndrew Jones 3827ee966e9SAndrew Jones ldp x28, x29, [sp, #224] 3837ee966e9SAndrew Jones ldp x26, x27, [sp, #208] 3847ee966e9SAndrew Jones ldp x24, x25, [sp, #192] 3857ee966e9SAndrew Jones ldp x22, x23, [sp, #176] 3867ee966e9SAndrew Jones ldp x20, x21, [sp, #160] 3877ee966e9SAndrew Jones ldp x18, x19, [sp, #144] 3887ee966e9SAndrew Jones ldp x16, x17, [sp, #128] 3897ee966e9SAndrew Jones ldp x14, x15, [sp, #112] 3907ee966e9SAndrew Jones ldp x12, x13, [sp, #96] 3917ee966e9SAndrew Jones ldp x10, x11, [sp, #80] 3927ee966e9SAndrew Jones ldp x8, x9, [sp, #64] 3937ee966e9SAndrew Jones ldp x6, x7, [sp, #48] 3947ee966e9SAndrew Jones ldp x4, x5, [sp, #32] 3957ee966e9SAndrew Jones ldp x2, x3, [sp, #16] 3967ee966e9SAndrew Jones ldp x0, x1, [sp], #S_FRAME_SIZE 3977ee966e9SAndrew Jones 3987ee966e9SAndrew Jones eret 3997ee966e9SAndrew Jones.endm 4007ee966e9SAndrew Jones 401ecb5e711SNadav Amit.globl vector_stub_start 402ecb5e711SNadav Amitvector_stub_start: 403ecb5e711SNadav Amit 4047ee966e9SAndrew Jonesvector_stub el1t_sync, 0 4057ee966e9SAndrew Jonesvector_stub el1t_irq, 1 4067ee966e9SAndrew Jonesvector_stub el1t_fiq, 2 4077ee966e9SAndrew Jonesvector_stub el1t_error, 3 4087ee966e9SAndrew Jones 4097ee966e9SAndrew Jonesvector_stub el1h_sync, 4 4107ee966e9SAndrew Jonesvector_stub el1h_irq, 5 4117ee966e9SAndrew Jonesvector_stub el1h_fiq, 6 4127ee966e9SAndrew Jonesvector_stub el1h_error, 7 4137ee966e9SAndrew Jones 4147ee966e9SAndrew Jonesvector_stub el0_sync_64, 8 4157ee966e9SAndrew Jonesvector_stub el0_irq_64, 9 4167ee966e9SAndrew Jonesvector_stub el0_fiq_64, 10 4177ee966e9SAndrew Jonesvector_stub el0_error_64, 11 4187ee966e9SAndrew Jones 4197ee966e9SAndrew Jonesvector_stub el0_sync_32, 12 4207ee966e9SAndrew Jonesvector_stub el0_irq_32, 13 4217ee966e9SAndrew Jonesvector_stub el0_fiq_32, 14 4227ee966e9SAndrew Jonesvector_stub el0_error_32, 15 4237ee966e9SAndrew Jones 424ecb5e711SNadav Amit.globl vector_stub_end 425ecb5e711SNadav Amitvector_stub_end: 426ecb5e711SNadav Amit 4277ee966e9SAndrew Jones.section .text.ex 4287ee966e9SAndrew Jones 4297ee966e9SAndrew Jones.macro ventry, label 4307ee966e9SAndrew Jones.align 7 4317ee966e9SAndrew Jones b \label 4327ee966e9SAndrew Jones.endm 4337ee966e9SAndrew Jones 434332b6216SNikos Nikoleris 435332b6216SNikos Nikoleris/* 436332b6216SNikos Nikoleris * Declare as weak to allow external tests to redefine and override the 437332b6216SNikos Nikoleris * default vector table. 438332b6216SNikos Nikoleris */ 4397ee966e9SAndrew Jones.align 11 440332b6216SNikos Nikoleris.weak vector_table 4417ee966e9SAndrew Jonesvector_table: 4427ee966e9SAndrew Jones ventry el1t_sync // Synchronous EL1t 4437ee966e9SAndrew Jones ventry el1t_irq // IRQ EL1t 4447ee966e9SAndrew Jones ventry el1t_fiq // FIQ EL1t 4457ee966e9SAndrew Jones ventry el1t_error // Error EL1t 4467ee966e9SAndrew Jones 4477ee966e9SAndrew Jones ventry el1h_sync // Synchronous EL1h 4487ee966e9SAndrew Jones ventry el1h_irq // IRQ EL1h 4497ee966e9SAndrew Jones ventry el1h_fiq // FIQ EL1h 4507ee966e9SAndrew Jones ventry el1h_error // Error EL1h 4517ee966e9SAndrew Jones 4527ee966e9SAndrew Jones ventry el0_sync_64 // Synchronous 64-bit EL0 4537ee966e9SAndrew Jones ventry el0_irq_64 // IRQ 64-bit EL0 4547ee966e9SAndrew Jones ventry el0_fiq_64 // FIQ 64-bit EL0 4557ee966e9SAndrew Jones ventry el0_error_64 // Error 64-bit EL0 4567ee966e9SAndrew Jones 4577ee966e9SAndrew Jones ventry el0_sync_32 // Synchronous 32-bit EL0 4587ee966e9SAndrew Jones ventry el0_irq_32 // IRQ 32-bit EL0 4597ee966e9SAndrew Jones ventry el0_fiq_32 // FIQ 32-bit EL0 4607ee966e9SAndrew Jones ventry el0_error_32 // Error 32-bit EL0 461