139ac3f84SAndrew Jones/* 239ac3f84SAndrew Jones * Boot entry point and assembler functions for aarch64 tests. 339ac3f84SAndrew Jones * 439ac3f84SAndrew Jones * Copyright (C) 2014, Red Hat Inc, Andrew Jones <drjones@redhat.com> 539ac3f84SAndrew Jones * 639ac3f84SAndrew Jones * This work is licensed under the terms of the GNU LGPL, version 2. 739ac3f84SAndrew Jones */ 839ac3f84SAndrew Jones#define __ASSEMBLY__ 939ac3f84SAndrew Jones#include <asm/asm-offsets.h> 10*7ee966e9SAndrew Jones#include <asm/ptrace.h> 1139ac3f84SAndrew Jones 1239ac3f84SAndrew Jones.section .init 1339ac3f84SAndrew Jones 1439ac3f84SAndrew Jones.globl start 1539ac3f84SAndrew Jonesstart: 1639ac3f84SAndrew Jones /* 1739ac3f84SAndrew Jones * bootloader params are in x0-x3 1839ac3f84SAndrew Jones * The physical address of the dtb is in x0, x1-x3 are reserved 1939ac3f84SAndrew Jones * See the kernel doc Documentation/arm64/booting.txt 2039ac3f84SAndrew Jones */ 2139ac3f84SAndrew Jones adr x4, stacktop 2239ac3f84SAndrew Jones mov sp, x4 2339ac3f84SAndrew Jones stp x0, x1, [sp, #-16]! 2439ac3f84SAndrew Jones 2539ac3f84SAndrew Jones /* Enable FP/ASIMD */ 2639ac3f84SAndrew Jones mov x0, #(3 << 20) 2739ac3f84SAndrew Jones msr cpacr_el1, x0 2839ac3f84SAndrew Jones 2939ac3f84SAndrew Jones /* set up exception handling */ 30*7ee966e9SAndrew Jones bl exceptions_init 3139ac3f84SAndrew Jones 3239ac3f84SAndrew Jones /* complete setup */ 3339ac3f84SAndrew Jones ldp x0, x1, [sp], #16 3439ac3f84SAndrew Jones bl setup 3539ac3f84SAndrew Jones 3639ac3f84SAndrew Jones /* run the test */ 3739ac3f84SAndrew Jones adr x0, __argc 3839ac3f84SAndrew Jones ldr x0, [x0] 3939ac3f84SAndrew Jones adr x1, __argv 4039ac3f84SAndrew Jones bl main 4139ac3f84SAndrew Jones bl exit 4239ac3f84SAndrew Jones b halt 4339ac3f84SAndrew Jones 44*7ee966e9SAndrew Jonesexceptions_init: 45*7ee966e9SAndrew Jones adr x0, vector_table 46*7ee966e9SAndrew Jones msr vbar_el1, x0 47*7ee966e9SAndrew Jones isb 48*7ee966e9SAndrew Jones ret 49*7ee966e9SAndrew Jones 5039ac3f84SAndrew Jones.text 5139ac3f84SAndrew Jones 5239ac3f84SAndrew Jones.globl halt 5339ac3f84SAndrew Joneshalt: 5439ac3f84SAndrew Jones1: wfi 5539ac3f84SAndrew Jones b 1b 56*7ee966e9SAndrew Jones 57*7ee966e9SAndrew Jones/* 58*7ee966e9SAndrew Jones * Vectors 59*7ee966e9SAndrew Jones * Adapted from arch/arm64/kernel/entry.S 60*7ee966e9SAndrew Jones */ 61*7ee966e9SAndrew Jones.macro vector_stub, name, vec 62*7ee966e9SAndrew Jones\name: 63*7ee966e9SAndrew Jones stp x0, x1, [sp, #-S_FRAME_SIZE]! 64*7ee966e9SAndrew Jones stp x2, x3, [sp, #16] 65*7ee966e9SAndrew Jones stp x4, x5, [sp, #32] 66*7ee966e9SAndrew Jones stp x6, x7, [sp, #48] 67*7ee966e9SAndrew Jones stp x8, x9, [sp, #64] 68*7ee966e9SAndrew Jones stp x10, x11, [sp, #80] 69*7ee966e9SAndrew Jones stp x12, x13, [sp, #96] 70*7ee966e9SAndrew Jones stp x14, x15, [sp, #112] 71*7ee966e9SAndrew Jones stp x16, x17, [sp, #128] 72*7ee966e9SAndrew Jones stp x18, x19, [sp, #144] 73*7ee966e9SAndrew Jones stp x20, x21, [sp, #160] 74*7ee966e9SAndrew Jones stp x22, x23, [sp, #176] 75*7ee966e9SAndrew Jones stp x24, x25, [sp, #192] 76*7ee966e9SAndrew Jones stp x26, x27, [sp, #208] 77*7ee966e9SAndrew Jones stp x28, x29, [sp, #224] 78*7ee966e9SAndrew Jones 79*7ee966e9SAndrew Jones str x30, [sp, #S_LR] 80*7ee966e9SAndrew Jones 81*7ee966e9SAndrew Jones .if \vec >= 8 82*7ee966e9SAndrew Jones mrs x1, sp_el0 83*7ee966e9SAndrew Jones .else 84*7ee966e9SAndrew Jones add x1, sp, #S_FRAME_SIZE 85*7ee966e9SAndrew Jones .endif 86*7ee966e9SAndrew Jones str x1, [sp, #S_SP] 87*7ee966e9SAndrew Jones 88*7ee966e9SAndrew Jones mrs x1, elr_el1 89*7ee966e9SAndrew Jones mrs x2, spsr_el1 90*7ee966e9SAndrew Jones stp x1, x2, [sp, #S_PC] 91*7ee966e9SAndrew Jones 92*7ee966e9SAndrew Jones and x2, x2, #PSR_MODE_MASK 93*7ee966e9SAndrew Jones cmp x2, #PSR_MODE_EL0t 94*7ee966e9SAndrew Jones b.ne 1f 95*7ee966e9SAndrew Jones adr x2, user_mode 96*7ee966e9SAndrew Jones str xzr, [x2] /* we're in kernel mode now */ 97*7ee966e9SAndrew Jones 98*7ee966e9SAndrew Jones1: mov x0, \vec 99*7ee966e9SAndrew Jones mov x1, sp 100*7ee966e9SAndrew Jones mrs x2, esr_el1 101*7ee966e9SAndrew Jones bl do_handle_exception 102*7ee966e9SAndrew Jones 103*7ee966e9SAndrew Jones ldp x1, x2, [sp, #S_PC] 104*7ee966e9SAndrew Jones msr spsr_el1, x2 105*7ee966e9SAndrew Jones msr elr_el1, x1 106*7ee966e9SAndrew Jones 107*7ee966e9SAndrew Jones and x2, x2, #PSR_MODE_MASK 108*7ee966e9SAndrew Jones cmp x2, #PSR_MODE_EL0t 109*7ee966e9SAndrew Jones b.ne 1f 110*7ee966e9SAndrew Jones adr x2, user_mode 111*7ee966e9SAndrew Jones mov x1, #1 112*7ee966e9SAndrew Jones str x1, [x2] /* we're going back to user mode */ 113*7ee966e9SAndrew Jones 114*7ee966e9SAndrew Jones1: 115*7ee966e9SAndrew Jones .if \vec >= 8 116*7ee966e9SAndrew Jones ldr x1, [sp, #S_SP] 117*7ee966e9SAndrew Jones msr sp_el0, x1 118*7ee966e9SAndrew Jones .endif 119*7ee966e9SAndrew Jones 120*7ee966e9SAndrew Jones ldr x30, [sp, #S_LR] 121*7ee966e9SAndrew Jones 122*7ee966e9SAndrew Jones ldp x28, x29, [sp, #224] 123*7ee966e9SAndrew Jones ldp x26, x27, [sp, #208] 124*7ee966e9SAndrew Jones ldp x24, x25, [sp, #192] 125*7ee966e9SAndrew Jones ldp x22, x23, [sp, #176] 126*7ee966e9SAndrew Jones ldp x20, x21, [sp, #160] 127*7ee966e9SAndrew Jones ldp x18, x19, [sp, #144] 128*7ee966e9SAndrew Jones ldp x16, x17, [sp, #128] 129*7ee966e9SAndrew Jones ldp x14, x15, [sp, #112] 130*7ee966e9SAndrew Jones ldp x12, x13, [sp, #96] 131*7ee966e9SAndrew Jones ldp x10, x11, [sp, #80] 132*7ee966e9SAndrew Jones ldp x8, x9, [sp, #64] 133*7ee966e9SAndrew Jones ldp x6, x7, [sp, #48] 134*7ee966e9SAndrew Jones ldp x4, x5, [sp, #32] 135*7ee966e9SAndrew Jones ldp x2, x3, [sp, #16] 136*7ee966e9SAndrew Jones ldp x0, x1, [sp], #S_FRAME_SIZE 137*7ee966e9SAndrew Jones 138*7ee966e9SAndrew Jones eret 139*7ee966e9SAndrew Jones.endm 140*7ee966e9SAndrew Jones 141*7ee966e9SAndrew Jonesvector_stub el1t_sync, 0 142*7ee966e9SAndrew Jonesvector_stub el1t_irq, 1 143*7ee966e9SAndrew Jonesvector_stub el1t_fiq, 2 144*7ee966e9SAndrew Jonesvector_stub el1t_error, 3 145*7ee966e9SAndrew Jones 146*7ee966e9SAndrew Jonesvector_stub el1h_sync, 4 147*7ee966e9SAndrew Jonesvector_stub el1h_irq, 5 148*7ee966e9SAndrew Jonesvector_stub el1h_fiq, 6 149*7ee966e9SAndrew Jonesvector_stub el1h_error, 7 150*7ee966e9SAndrew Jones 151*7ee966e9SAndrew Jonesvector_stub el0_sync_64, 8 152*7ee966e9SAndrew Jonesvector_stub el0_irq_64, 9 153*7ee966e9SAndrew Jonesvector_stub el0_fiq_64, 10 154*7ee966e9SAndrew Jonesvector_stub el0_error_64, 11 155*7ee966e9SAndrew Jones 156*7ee966e9SAndrew Jonesvector_stub el0_sync_32, 12 157*7ee966e9SAndrew Jonesvector_stub el0_irq_32, 13 158*7ee966e9SAndrew Jonesvector_stub el0_fiq_32, 14 159*7ee966e9SAndrew Jonesvector_stub el0_error_32, 15 160*7ee966e9SAndrew Jones 161*7ee966e9SAndrew Jones.section .text.ex 162*7ee966e9SAndrew Jones 163*7ee966e9SAndrew Jones.macro ventry, label 164*7ee966e9SAndrew Jones.align 7 165*7ee966e9SAndrew Jones b \label 166*7ee966e9SAndrew Jones.endm 167*7ee966e9SAndrew Jones 168*7ee966e9SAndrew Jones.align 11 169*7ee966e9SAndrew Jonesvector_table: 170*7ee966e9SAndrew Jones ventry el1t_sync // Synchronous EL1t 171*7ee966e9SAndrew Jones ventry el1t_irq // IRQ EL1t 172*7ee966e9SAndrew Jones ventry el1t_fiq // FIQ EL1t 173*7ee966e9SAndrew Jones ventry el1t_error // Error EL1t 174*7ee966e9SAndrew Jones 175*7ee966e9SAndrew Jones ventry el1h_sync // Synchronous EL1h 176*7ee966e9SAndrew Jones ventry el1h_irq // IRQ EL1h 177*7ee966e9SAndrew Jones ventry el1h_fiq // FIQ EL1h 178*7ee966e9SAndrew Jones ventry el1h_error // Error EL1h 179*7ee966e9SAndrew Jones 180*7ee966e9SAndrew Jones ventry el0_sync_64 // Synchronous 64-bit EL0 181*7ee966e9SAndrew Jones ventry el0_irq_64 // IRQ 64-bit EL0 182*7ee966e9SAndrew Jones ventry el0_fiq_64 // FIQ 64-bit EL0 183*7ee966e9SAndrew Jones ventry el0_error_64 // Error 64-bit EL0 184*7ee966e9SAndrew Jones 185*7ee966e9SAndrew Jones ventry el0_sync_32 // Synchronous 32-bit EL0 186*7ee966e9SAndrew Jones ventry el0_irq_32 // IRQ 32-bit EL0 187*7ee966e9SAndrew Jones ventry el0_fiq_32 // FIQ 32-bit EL0 188*7ee966e9SAndrew Jones ventry el0_error_32 // Error 32-bit EL0 189