1 // Copyright © 2019 Intel Corporation 2 // 3 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 4 // 5 // Copyright © 2020, Microsoft Corporation 6 // 7 // Copyright 2018-2019 CrowdStrike, Inc. 8 // 9 // 10 use crate::arch::x86::{ 11 CpuIdEntry, DescriptorTable, FpuState, LapicState, MsrEntry, SegmentRegister, SpecialRegisters, 12 StandardRegisters, 13 }; 14 use serde::{Deserialize, Serialize}; 15 use std::fmt; 16 17 /// 18 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms 19 /// 20 pub use { 21 mshv_bindings::hv_cpuid_entry, mshv_bindings::mshv_user_mem_region as MemoryRegion, 22 mshv_bindings::msr_entry, mshv_bindings::CpuId, mshv_bindings::DebugRegisters, 23 mshv_bindings::FloatingPointUnit, mshv_bindings::LapicState as MshvLapicState, 24 mshv_bindings::MiscRegs as MiscRegisters, mshv_bindings::MsrList, 25 mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, 26 mshv_bindings::SegmentRegister as MshvSegmentRegister, 27 mshv_bindings::SpecialRegisters as MshvSpecialRegisters, 28 mshv_bindings::StandardRegisters as MshvStandardRegisters, mshv_bindings::SuspendRegisters, 29 mshv_bindings::TableRegister, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave, 30 mshv_bindings::Xcrs as ExtendedControlRegisters, 31 }; 32 33 #[derive(Clone, Serialize, Deserialize)] 34 pub struct VcpuMshvState { 35 pub msrs: Vec<MsrEntry>, 36 pub vcpu_events: VcpuEvents, 37 pub regs: MshvStandardRegisters, 38 pub sregs: MshvSpecialRegisters, 39 pub fpu: FpuState, 40 pub xcrs: ExtendedControlRegisters, 41 pub lapic: LapicState, 42 pub dbg: DebugRegisters, 43 pub xsave: Xsave, 44 pub misc: MiscRegisters, 45 } 46 47 impl fmt::Display for VcpuMshvState { 48 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 49 let expected_num_msrs = self.msrs.len(); 50 let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; 51 52 for (i, entry) in self.msrs.iter().enumerate() { 53 msr_entries[i][1] = entry.data; 54 msr_entries[i][0] = entry.index as u64; 55 } 56 write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- Local APIC: {:?} --- DBG: {:?} --- Xsave: {:?}", 57 msr_entries.len(), 58 msr_entries, 59 self.vcpu_events, 60 self.regs, 61 self.sregs, 62 self.fpu, 63 self.xcrs, 64 self.lapic, 65 self.dbg, 66 self.xsave, 67 ) 68 } 69 } 70 71 impl From<StandardRegisters> for MshvStandardRegisters { 72 fn from(regs: StandardRegisters) -> Self { 73 Self { 74 rax: regs.rax, 75 rbx: regs.rbx, 76 rcx: regs.rcx, 77 rdx: regs.rdx, 78 rsi: regs.rsi, 79 rdi: regs.rdi, 80 rsp: regs.rsp, 81 rbp: regs.rbp, 82 r8: regs.r8, 83 r9: regs.r9, 84 r10: regs.r10, 85 r11: regs.r11, 86 r12: regs.r12, 87 r13: regs.r13, 88 r14: regs.r14, 89 r15: regs.r15, 90 rip: regs.rip, 91 rflags: regs.rflags, 92 } 93 } 94 } 95 96 impl From<MshvStandardRegisters> for StandardRegisters { 97 fn from(regs: MshvStandardRegisters) -> Self { 98 Self { 99 rax: regs.rax, 100 rbx: regs.rbx, 101 rcx: regs.rcx, 102 rdx: regs.rdx, 103 rsi: regs.rsi, 104 rdi: regs.rdi, 105 rsp: regs.rsp, 106 rbp: regs.rbp, 107 r8: regs.r8, 108 r9: regs.r9, 109 r10: regs.r10, 110 r11: regs.r11, 111 r12: regs.r12, 112 r13: regs.r13, 113 r14: regs.r14, 114 r15: regs.r15, 115 rip: regs.rip, 116 rflags: regs.rflags, 117 } 118 } 119 } 120 121 impl From<SegmentRegister> for MshvSegmentRegister { 122 fn from(s: SegmentRegister) -> Self { 123 Self { 124 base: s.base, 125 limit: s.limit, 126 selector: s.selector, 127 type_: s.type_, 128 present: s.present, 129 dpl: s.dpl, 130 db: s.db, 131 s: s.s, 132 l: s.l, 133 g: s.g, 134 avl: s.avl, 135 unusable: s.unusable, 136 ..Default::default() 137 } 138 } 139 } 140 141 impl From<MshvSegmentRegister> for SegmentRegister { 142 fn from(s: MshvSegmentRegister) -> Self { 143 Self { 144 base: s.base, 145 limit: s.limit, 146 selector: s.selector, 147 type_: s.type_, 148 present: s.present, 149 dpl: s.dpl, 150 db: s.db, 151 s: s.s, 152 l: s.l, 153 g: s.g, 154 avl: s.avl, 155 unusable: s.unusable, 156 } 157 } 158 } 159 160 impl From<DescriptorTable> for TableRegister { 161 fn from(dt: DescriptorTable) -> Self { 162 Self { 163 base: dt.base, 164 limit: dt.limit, 165 } 166 } 167 } 168 169 impl From<TableRegister> for DescriptorTable { 170 fn from(dt: TableRegister) -> Self { 171 Self { 172 base: dt.base, 173 limit: dt.limit, 174 } 175 } 176 } 177 178 impl From<SpecialRegisters> for MshvSpecialRegisters { 179 fn from(s: SpecialRegisters) -> Self { 180 Self { 181 cs: s.cs.into(), 182 ds: s.ds.into(), 183 es: s.es.into(), 184 fs: s.fs.into(), 185 gs: s.gs.into(), 186 ss: s.ss.into(), 187 tr: s.tr.into(), 188 ldt: s.ldt.into(), 189 gdt: s.gdt.into(), 190 idt: s.idt.into(), 191 cr0: s.cr0, 192 cr2: s.cr2, 193 cr3: s.cr3, 194 cr4: s.cr4, 195 cr8: s.cr8, 196 efer: s.efer, 197 apic_base: s.apic_base, 198 interrupt_bitmap: s.interrupt_bitmap, 199 } 200 } 201 } 202 203 impl From<MshvSpecialRegisters> for SpecialRegisters { 204 fn from(s: MshvSpecialRegisters) -> Self { 205 Self { 206 cs: s.cs.into(), 207 ds: s.ds.into(), 208 es: s.es.into(), 209 fs: s.fs.into(), 210 gs: s.gs.into(), 211 ss: s.ss.into(), 212 tr: s.tr.into(), 213 ldt: s.ldt.into(), 214 gdt: s.gdt.into(), 215 idt: s.idt.into(), 216 cr0: s.cr0, 217 cr2: s.cr2, 218 cr3: s.cr3, 219 cr4: s.cr4, 220 cr8: s.cr8, 221 efer: s.efer, 222 apic_base: s.apic_base, 223 interrupt_bitmap: s.interrupt_bitmap, 224 } 225 } 226 } 227 228 impl From<CpuIdEntry> for hv_cpuid_entry { 229 fn from(e: CpuIdEntry) -> Self { 230 Self { 231 function: e.function, 232 index: e.index, 233 flags: e.flags, 234 eax: e.eax, 235 ebx: e.ebx, 236 ecx: e.ecx, 237 edx: e.edx, 238 ..Default::default() 239 } 240 } 241 } 242 243 impl From<hv_cpuid_entry> for CpuIdEntry { 244 fn from(e: hv_cpuid_entry) -> Self { 245 Self { 246 function: e.function, 247 index: e.index, 248 flags: e.flags, 249 eax: e.eax, 250 ebx: e.ebx, 251 ecx: e.ecx, 252 edx: e.edx, 253 } 254 } 255 } 256 257 impl From<FloatingPointUnit> for FpuState { 258 fn from(s: FloatingPointUnit) -> Self { 259 Self { 260 fpr: s.fpr, 261 fcw: s.fcw, 262 fsw: s.fsw, 263 ftwx: s.ftwx, 264 last_opcode: s.last_opcode, 265 last_ip: s.last_ip, 266 last_dp: s.last_dp, 267 xmm: s.xmm, 268 mxcsr: s.mxcsr, 269 } 270 } 271 } 272 273 impl From<FpuState> for FloatingPointUnit { 274 fn from(s: FpuState) -> Self { 275 Self { 276 fpr: s.fpr, 277 fcw: s.fcw, 278 fsw: s.fsw, 279 ftwx: s.ftwx, 280 last_opcode: s.last_opcode, 281 last_ip: s.last_ip, 282 last_dp: s.last_dp, 283 xmm: s.xmm, 284 mxcsr: s.mxcsr, 285 ..Default::default() 286 } 287 } 288 } 289 290 impl From<LapicState> for MshvLapicState { 291 fn from(s: LapicState) -> Self { 292 Self { regs: s.regs } 293 } 294 } 295 296 impl From<MshvLapicState> for LapicState { 297 fn from(s: MshvLapicState) -> Self { 298 Self { regs: s.regs } 299 } 300 } 301 302 impl From<msr_entry> for MsrEntry { 303 fn from(e: msr_entry) -> Self { 304 Self { 305 index: e.index, 306 data: e.data, 307 } 308 } 309 } 310 311 impl From<MsrEntry> for msr_entry { 312 fn from(e: MsrEntry) -> Self { 313 Self { 314 index: e.index, 315 data: e.data, 316 ..Default::default() 317 } 318 } 319 } 320