1 // Copyright © 2019 Intel Corporation 2 // 3 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 4 // 5 // Copyright © 2020, Microsoft Corporation 6 // 7 // Copyright 2018-2019 CrowdStrike, Inc. 8 // 9 // 10 use crate::arch::x86::{ 11 CpuIdEntry, DescriptorTable, FpuState, LapicState, MsrEntry, SegmentRegister, SpecialRegisters, 12 StandardRegisters, 13 }; 14 use serde::{Deserialize, Serialize}; 15 use std::fmt; 16 17 pub mod emulator; 18 19 /// 20 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms 21 /// 22 pub use { 23 mshv_bindings::hv_cpuid_entry, mshv_bindings::mshv_user_mem_region as MemoryRegion, 24 mshv_bindings::msr_entry, mshv_bindings::AllVpStateComponents, mshv_bindings::CpuId, 25 mshv_bindings::DebugRegisters, mshv_bindings::FloatingPointUnit, 26 mshv_bindings::LapicState as MshvLapicState, mshv_bindings::MiscRegs as MiscRegisters, 27 mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, 28 mshv_bindings::SegmentRegister as MshvSegmentRegister, 29 mshv_bindings::SpecialRegisters as MshvSpecialRegisters, 30 mshv_bindings::StandardRegisters as MshvStandardRegisters, mshv_bindings::SuspendRegisters, 31 mshv_bindings::TableRegister, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave, 32 mshv_bindings::Xcrs as ExtendedControlRegisters, 33 }; 34 35 #[derive(Clone, Serialize, Deserialize)] 36 pub struct VcpuMshvState { 37 pub msrs: Vec<MsrEntry>, 38 pub vcpu_events: VcpuEvents, 39 pub regs: MshvStandardRegisters, 40 pub sregs: MshvSpecialRegisters, 41 pub fpu: FpuState, 42 pub xcrs: ExtendedControlRegisters, 43 pub dbg: DebugRegisters, 44 pub misc: MiscRegisters, 45 pub vp_states: AllVpStateComponents, 46 } 47 48 #[derive(Clone, Copy, Debug, Default, Serialize, Deserialize)] 49 pub struct MshvClockData { 50 pub ref_time: u64, 51 } 52 53 impl fmt::Display for VcpuMshvState { 54 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 55 let expected_num_msrs = self.msrs.len(); 56 let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; 57 58 for (i, entry) in self.msrs.iter().enumerate() { 59 msr_entries[i][1] = entry.data; 60 msr_entries[i][0] = entry.index as u64; 61 } 62 write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- DBG: {:?} --- VP States: {:?}", 63 msr_entries.len(), 64 msr_entries, 65 self.vcpu_events, 66 self.regs, 67 self.sregs, 68 self.fpu, 69 self.xcrs, 70 self.dbg, 71 self.vp_states, 72 ) 73 } 74 } 75 76 impl From<StandardRegisters> for MshvStandardRegisters { 77 fn from(regs: StandardRegisters) -> Self { 78 Self { 79 rax: regs.rax, 80 rbx: regs.rbx, 81 rcx: regs.rcx, 82 rdx: regs.rdx, 83 rsi: regs.rsi, 84 rdi: regs.rdi, 85 rsp: regs.rsp, 86 rbp: regs.rbp, 87 r8: regs.r8, 88 r9: regs.r9, 89 r10: regs.r10, 90 r11: regs.r11, 91 r12: regs.r12, 92 r13: regs.r13, 93 r14: regs.r14, 94 r15: regs.r15, 95 rip: regs.rip, 96 rflags: regs.rflags, 97 } 98 } 99 } 100 101 impl From<MshvStandardRegisters> for StandardRegisters { 102 fn from(regs: MshvStandardRegisters) -> Self { 103 Self { 104 rax: regs.rax, 105 rbx: regs.rbx, 106 rcx: regs.rcx, 107 rdx: regs.rdx, 108 rsi: regs.rsi, 109 rdi: regs.rdi, 110 rsp: regs.rsp, 111 rbp: regs.rbp, 112 r8: regs.r8, 113 r9: regs.r9, 114 r10: regs.r10, 115 r11: regs.r11, 116 r12: regs.r12, 117 r13: regs.r13, 118 r14: regs.r14, 119 r15: regs.r15, 120 rip: regs.rip, 121 rflags: regs.rflags, 122 } 123 } 124 } 125 126 impl From<SegmentRegister> for MshvSegmentRegister { 127 fn from(s: SegmentRegister) -> Self { 128 Self { 129 base: s.base, 130 limit: s.limit, 131 selector: s.selector, 132 type_: s.type_, 133 present: s.present, 134 dpl: s.dpl, 135 db: s.db, 136 s: s.s, 137 l: s.l, 138 g: s.g, 139 avl: s.avl, 140 unusable: s.unusable, 141 ..Default::default() 142 } 143 } 144 } 145 146 impl From<MshvSegmentRegister> for SegmentRegister { 147 fn from(s: MshvSegmentRegister) -> Self { 148 Self { 149 base: s.base, 150 limit: s.limit, 151 selector: s.selector, 152 type_: s.type_, 153 present: s.present, 154 dpl: s.dpl, 155 db: s.db, 156 s: s.s, 157 l: s.l, 158 g: s.g, 159 avl: s.avl, 160 unusable: s.unusable, 161 } 162 } 163 } 164 165 impl From<DescriptorTable> for TableRegister { 166 fn from(dt: DescriptorTable) -> Self { 167 Self { 168 base: dt.base, 169 limit: dt.limit, 170 } 171 } 172 } 173 174 impl From<TableRegister> for DescriptorTable { 175 fn from(dt: TableRegister) -> Self { 176 Self { 177 base: dt.base, 178 limit: dt.limit, 179 } 180 } 181 } 182 183 impl From<SpecialRegisters> for MshvSpecialRegisters { 184 fn from(s: SpecialRegisters) -> Self { 185 Self { 186 cs: s.cs.into(), 187 ds: s.ds.into(), 188 es: s.es.into(), 189 fs: s.fs.into(), 190 gs: s.gs.into(), 191 ss: s.ss.into(), 192 tr: s.tr.into(), 193 ldt: s.ldt.into(), 194 gdt: s.gdt.into(), 195 idt: s.idt.into(), 196 cr0: s.cr0, 197 cr2: s.cr2, 198 cr3: s.cr3, 199 cr4: s.cr4, 200 cr8: s.cr8, 201 efer: s.efer, 202 apic_base: s.apic_base, 203 interrupt_bitmap: s.interrupt_bitmap, 204 } 205 } 206 } 207 208 impl From<MshvSpecialRegisters> for SpecialRegisters { 209 fn from(s: MshvSpecialRegisters) -> Self { 210 Self { 211 cs: s.cs.into(), 212 ds: s.ds.into(), 213 es: s.es.into(), 214 fs: s.fs.into(), 215 gs: s.gs.into(), 216 ss: s.ss.into(), 217 tr: s.tr.into(), 218 ldt: s.ldt.into(), 219 gdt: s.gdt.into(), 220 idt: s.idt.into(), 221 cr0: s.cr0, 222 cr2: s.cr2, 223 cr3: s.cr3, 224 cr4: s.cr4, 225 cr8: s.cr8, 226 efer: s.efer, 227 apic_base: s.apic_base, 228 interrupt_bitmap: s.interrupt_bitmap, 229 } 230 } 231 } 232 233 impl From<CpuIdEntry> for hv_cpuid_entry { 234 fn from(e: CpuIdEntry) -> Self { 235 Self { 236 function: e.function, 237 index: e.index, 238 flags: e.flags, 239 eax: e.eax, 240 ebx: e.ebx, 241 ecx: e.ecx, 242 edx: e.edx, 243 ..Default::default() 244 } 245 } 246 } 247 248 impl From<hv_cpuid_entry> for CpuIdEntry { 249 fn from(e: hv_cpuid_entry) -> Self { 250 Self { 251 function: e.function, 252 index: e.index, 253 flags: e.flags, 254 eax: e.eax, 255 ebx: e.ebx, 256 ecx: e.ecx, 257 edx: e.edx, 258 } 259 } 260 } 261 262 impl From<FloatingPointUnit> for FpuState { 263 fn from(s: FloatingPointUnit) -> Self { 264 Self { 265 fpr: s.fpr, 266 fcw: s.fcw, 267 fsw: s.fsw, 268 ftwx: s.ftwx, 269 last_opcode: s.last_opcode, 270 last_ip: s.last_ip, 271 last_dp: s.last_dp, 272 xmm: s.xmm, 273 mxcsr: s.mxcsr, 274 } 275 } 276 } 277 278 impl From<FpuState> for FloatingPointUnit { 279 fn from(s: FpuState) -> Self { 280 Self { 281 fpr: s.fpr, 282 fcw: s.fcw, 283 fsw: s.fsw, 284 ftwx: s.ftwx, 285 last_opcode: s.last_opcode, 286 last_ip: s.last_ip, 287 last_dp: s.last_dp, 288 xmm: s.xmm, 289 mxcsr: s.mxcsr, 290 ..Default::default() 291 } 292 } 293 } 294 295 impl From<LapicState> for MshvLapicState { 296 fn from(s: LapicState) -> Self { 297 Self { regs: s.regs } 298 } 299 } 300 301 impl From<MshvLapicState> for LapicState { 302 fn from(s: MshvLapicState) -> Self { 303 Self { regs: s.regs } 304 } 305 } 306 307 impl From<msr_entry> for MsrEntry { 308 fn from(e: msr_entry) -> Self { 309 Self { 310 index: e.index, 311 data: e.data, 312 } 313 } 314 } 315 316 impl From<MsrEntry> for msr_entry { 317 fn from(e: MsrEntry) -> Self { 318 Self { 319 index: e.index, 320 data: e.data, 321 ..Default::default() 322 } 323 } 324 } 325