1 // Copyright © 2019 Intel Corporation 2 // 3 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 4 // 5 // Copyright © 2020, Microsoft Corporation 6 // 7 // Copyright 2018-2019 CrowdStrike, Inc. 8 // 9 // 10 use crate::arch::x86::{ 11 CpuIdEntry, DescriptorTable, FpuState, LapicState, MsrEntry, SegmentRegister, SpecialRegisters, 12 StandardRegisters, 13 }; 14 use serde::{Deserialize, Serialize}; 15 use std::fmt; 16 17 /// 18 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms 19 /// 20 pub use { 21 mshv_bindings::hv_cpuid_entry, mshv_bindings::mshv_user_mem_region as MemoryRegion, 22 mshv_bindings::msr_entry, mshv_bindings::AllVpStateComponents, mshv_bindings::CpuId, 23 mshv_bindings::DebugRegisters, mshv_bindings::FloatingPointUnit, 24 mshv_bindings::LapicState as MshvLapicState, mshv_bindings::MiscRegs as MiscRegisters, 25 mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, 26 mshv_bindings::SegmentRegister as MshvSegmentRegister, 27 mshv_bindings::SpecialRegisters as MshvSpecialRegisters, 28 mshv_bindings::StandardRegisters as MshvStandardRegisters, mshv_bindings::SuspendRegisters, 29 mshv_bindings::TableRegister, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave, 30 mshv_bindings::Xcrs as ExtendedControlRegisters, 31 }; 32 33 #[derive(Clone, Serialize, Deserialize)] 34 pub struct VcpuMshvState { 35 pub msrs: Vec<MsrEntry>, 36 pub vcpu_events: VcpuEvents, 37 pub regs: MshvStandardRegisters, 38 pub sregs: MshvSpecialRegisters, 39 pub fpu: FpuState, 40 pub xcrs: ExtendedControlRegisters, 41 pub dbg: DebugRegisters, 42 pub misc: MiscRegisters, 43 pub vp_states: AllVpStateComponents, 44 } 45 46 #[derive(Clone, Copy, Debug, Default, Serialize, Deserialize)] 47 pub struct MshvClockData { 48 pub ref_time: u64, 49 } 50 51 impl fmt::Display for VcpuMshvState { 52 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 53 let expected_num_msrs = self.msrs.len(); 54 let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; 55 56 for (i, entry) in self.msrs.iter().enumerate() { 57 msr_entries[i][1] = entry.data; 58 msr_entries[i][0] = entry.index as u64; 59 } 60 write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- DBG: {:?} --- VP States: {:?}", 61 msr_entries.len(), 62 msr_entries, 63 self.vcpu_events, 64 self.regs, 65 self.sregs, 66 self.fpu, 67 self.xcrs, 68 self.dbg, 69 self.vp_states, 70 ) 71 } 72 } 73 74 impl From<StandardRegisters> for MshvStandardRegisters { 75 fn from(regs: StandardRegisters) -> Self { 76 Self { 77 rax: regs.rax, 78 rbx: regs.rbx, 79 rcx: regs.rcx, 80 rdx: regs.rdx, 81 rsi: regs.rsi, 82 rdi: regs.rdi, 83 rsp: regs.rsp, 84 rbp: regs.rbp, 85 r8: regs.r8, 86 r9: regs.r9, 87 r10: regs.r10, 88 r11: regs.r11, 89 r12: regs.r12, 90 r13: regs.r13, 91 r14: regs.r14, 92 r15: regs.r15, 93 rip: regs.rip, 94 rflags: regs.rflags, 95 } 96 } 97 } 98 99 impl From<MshvStandardRegisters> for StandardRegisters { 100 fn from(regs: MshvStandardRegisters) -> Self { 101 Self { 102 rax: regs.rax, 103 rbx: regs.rbx, 104 rcx: regs.rcx, 105 rdx: regs.rdx, 106 rsi: regs.rsi, 107 rdi: regs.rdi, 108 rsp: regs.rsp, 109 rbp: regs.rbp, 110 r8: regs.r8, 111 r9: regs.r9, 112 r10: regs.r10, 113 r11: regs.r11, 114 r12: regs.r12, 115 r13: regs.r13, 116 r14: regs.r14, 117 r15: regs.r15, 118 rip: regs.rip, 119 rflags: regs.rflags, 120 } 121 } 122 } 123 124 impl From<SegmentRegister> for MshvSegmentRegister { 125 fn from(s: SegmentRegister) -> Self { 126 Self { 127 base: s.base, 128 limit: s.limit, 129 selector: s.selector, 130 type_: s.type_, 131 present: s.present, 132 dpl: s.dpl, 133 db: s.db, 134 s: s.s, 135 l: s.l, 136 g: s.g, 137 avl: s.avl, 138 unusable: s.unusable, 139 ..Default::default() 140 } 141 } 142 } 143 144 impl From<MshvSegmentRegister> for SegmentRegister { 145 fn from(s: MshvSegmentRegister) -> Self { 146 Self { 147 base: s.base, 148 limit: s.limit, 149 selector: s.selector, 150 type_: s.type_, 151 present: s.present, 152 dpl: s.dpl, 153 db: s.db, 154 s: s.s, 155 l: s.l, 156 g: s.g, 157 avl: s.avl, 158 unusable: s.unusable, 159 } 160 } 161 } 162 163 impl From<DescriptorTable> for TableRegister { 164 fn from(dt: DescriptorTable) -> Self { 165 Self { 166 base: dt.base, 167 limit: dt.limit, 168 } 169 } 170 } 171 172 impl From<TableRegister> for DescriptorTable { 173 fn from(dt: TableRegister) -> Self { 174 Self { 175 base: dt.base, 176 limit: dt.limit, 177 } 178 } 179 } 180 181 impl From<SpecialRegisters> for MshvSpecialRegisters { 182 fn from(s: SpecialRegisters) -> Self { 183 Self { 184 cs: s.cs.into(), 185 ds: s.ds.into(), 186 es: s.es.into(), 187 fs: s.fs.into(), 188 gs: s.gs.into(), 189 ss: s.ss.into(), 190 tr: s.tr.into(), 191 ldt: s.ldt.into(), 192 gdt: s.gdt.into(), 193 idt: s.idt.into(), 194 cr0: s.cr0, 195 cr2: s.cr2, 196 cr3: s.cr3, 197 cr4: s.cr4, 198 cr8: s.cr8, 199 efer: s.efer, 200 apic_base: s.apic_base, 201 interrupt_bitmap: s.interrupt_bitmap, 202 } 203 } 204 } 205 206 impl From<MshvSpecialRegisters> for SpecialRegisters { 207 fn from(s: MshvSpecialRegisters) -> Self { 208 Self { 209 cs: s.cs.into(), 210 ds: s.ds.into(), 211 es: s.es.into(), 212 fs: s.fs.into(), 213 gs: s.gs.into(), 214 ss: s.ss.into(), 215 tr: s.tr.into(), 216 ldt: s.ldt.into(), 217 gdt: s.gdt.into(), 218 idt: s.idt.into(), 219 cr0: s.cr0, 220 cr2: s.cr2, 221 cr3: s.cr3, 222 cr4: s.cr4, 223 cr8: s.cr8, 224 efer: s.efer, 225 apic_base: s.apic_base, 226 interrupt_bitmap: s.interrupt_bitmap, 227 } 228 } 229 } 230 231 impl From<CpuIdEntry> for hv_cpuid_entry { 232 fn from(e: CpuIdEntry) -> Self { 233 Self { 234 function: e.function, 235 index: e.index, 236 flags: e.flags, 237 eax: e.eax, 238 ebx: e.ebx, 239 ecx: e.ecx, 240 edx: e.edx, 241 ..Default::default() 242 } 243 } 244 } 245 246 impl From<hv_cpuid_entry> for CpuIdEntry { 247 fn from(e: hv_cpuid_entry) -> Self { 248 Self { 249 function: e.function, 250 index: e.index, 251 flags: e.flags, 252 eax: e.eax, 253 ebx: e.ebx, 254 ecx: e.ecx, 255 edx: e.edx, 256 } 257 } 258 } 259 260 impl From<FloatingPointUnit> for FpuState { 261 fn from(s: FloatingPointUnit) -> Self { 262 Self { 263 fpr: s.fpr, 264 fcw: s.fcw, 265 fsw: s.fsw, 266 ftwx: s.ftwx, 267 last_opcode: s.last_opcode, 268 last_ip: s.last_ip, 269 last_dp: s.last_dp, 270 xmm: s.xmm, 271 mxcsr: s.mxcsr, 272 } 273 } 274 } 275 276 impl From<FpuState> for FloatingPointUnit { 277 fn from(s: FpuState) -> Self { 278 Self { 279 fpr: s.fpr, 280 fcw: s.fcw, 281 fsw: s.fsw, 282 ftwx: s.ftwx, 283 last_opcode: s.last_opcode, 284 last_ip: s.last_ip, 285 last_dp: s.last_dp, 286 xmm: s.xmm, 287 mxcsr: s.mxcsr, 288 ..Default::default() 289 } 290 } 291 } 292 293 impl From<LapicState> for MshvLapicState { 294 fn from(s: LapicState) -> Self { 295 Self { regs: s.regs } 296 } 297 } 298 299 impl From<MshvLapicState> for LapicState { 300 fn from(s: MshvLapicState) -> Self { 301 Self { regs: s.regs } 302 } 303 } 304 305 impl From<msr_entry> for MsrEntry { 306 fn from(e: msr_entry) -> Self { 307 Self { 308 index: e.index, 309 data: e.data, 310 } 311 } 312 } 313 314 impl From<MsrEntry> for msr_entry { 315 fn from(e: MsrEntry) -> Self { 316 Self { 317 index: e.index, 318 data: e.data, 319 ..Default::default() 320 } 321 } 322 } 323