1 // Copyright © 2019 Intel Corporation 2 // 3 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 4 // 5 // Copyright © 2020, Microsoft Corporation 6 // 7 // Copyright 2018-2019 CrowdStrike, Inc. 8 // 9 // 10 use crate::arch::x86::{msr_index, SegmentRegisterOps, MTRR_ENABLE, MTRR_MEM_TYPE_WB}; 11 use serde_derive::{Deserialize, Serialize}; 12 use std::fmt; 13 14 /// 15 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms 16 /// 17 pub use { 18 mshv_bindings::mshv_user_mem_region as MemoryRegion, mshv_bindings::msr_entry as MsrEntry, 19 mshv_bindings::CpuId, mshv_bindings::DebugRegisters, 20 mshv_bindings::FloatingPointUnit as FpuState, mshv_bindings::LapicState, 21 mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, 22 mshv_bindings::SegmentRegister, mshv_bindings::SpecialRegisters, 23 mshv_bindings::StandardRegisters, mshv_bindings::SuspendRegisters, mshv_bindings::VcpuEvents, 24 mshv_bindings::XSave as Xsave, mshv_bindings::Xcrs as ExtendedControlRegisters, 25 }; 26 27 #[derive(Clone, Serialize, Deserialize)] 28 pub struct VcpuMshvState { 29 pub msrs: MsrEntries, 30 pub vcpu_events: VcpuEvents, 31 pub regs: StandardRegisters, 32 pub sregs: SpecialRegisters, 33 pub fpu: FpuState, 34 pub xcrs: ExtendedControlRegisters, 35 pub lapic: LapicState, 36 pub dbg: DebugRegisters, 37 pub xsave: Xsave, 38 } 39 40 impl fmt::Display for VcpuMshvState { 41 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 42 let expected_num_msrs = self.msrs.as_fam_struct_ref().nmsrs as usize; 43 let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; 44 45 for (i, entry) in self.msrs.as_slice().iter().enumerate() { 46 msr_entries[i][1] = entry.data; 47 msr_entries[i][0] = entry.index as u64; 48 } 49 write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- Local APIC: {:?} --- DBG: {:?} --- Xsave: {:?}", 50 msr_entries.len(), 51 msr_entries, 52 self.vcpu_events, 53 self.regs, 54 self.sregs, 55 self.fpu, 56 self.xcrs, 57 self.lapic, 58 self.dbg, 59 self.xsave, 60 ) 61 } 62 } 63 64 pub struct CreateDevice {} 65 pub struct DeviceAttr {} 66 pub struct IrqRouting {} 67 pub enum VcpuExit {} 68 pub struct MpState {} 69 70 impl SegmentRegisterOps for SegmentRegister { 71 fn segment_type(&self) -> u8 { 72 self.type_ 73 } 74 fn set_segment_type(&mut self, val: u8) { 75 self.type_ = val; 76 } 77 78 fn dpl(&self) -> u8 { 79 self.dpl 80 } 81 82 fn set_dpl(&mut self, val: u8) { 83 self.dpl = val; 84 } 85 86 fn present(&self) -> u8 { 87 self.present 88 } 89 90 fn set_present(&mut self, val: u8) { 91 self.present = val; 92 } 93 94 fn long(&self) -> u8 { 95 self.l 96 } 97 98 fn set_long(&mut self, val: u8) { 99 self.l = val; 100 } 101 102 fn avl(&self) -> u8 { 103 self.avl 104 } 105 106 fn set_avl(&mut self, val: u8) { 107 self.avl = val; 108 } 109 110 fn desc_type(&self) -> u8 { 111 self.s 112 } 113 114 fn set_desc_type(&mut self, val: u8) { 115 self.s = val; 116 } 117 118 fn granularity(&self) -> u8 { 119 self.g 120 } 121 122 fn set_granularity(&mut self, val: u8) { 123 self.g = val; 124 } 125 126 fn db(&self) -> u8 { 127 self.db 128 } 129 130 fn set_db(&mut self, val: u8) { 131 self.db = val; 132 } 133 } 134 135 pub fn boot_msr_entries() -> MsrEntries { 136 MsrEntries::from_entries(&[ 137 msr!(msr_index::MSR_IA32_SYSENTER_CS), 138 msr!(msr_index::MSR_IA32_SYSENTER_ESP), 139 msr!(msr_index::MSR_IA32_SYSENTER_EIP), 140 msr!(msr_index::MSR_STAR), 141 msr!(msr_index::MSR_CSTAR), 142 msr!(msr_index::MSR_LSTAR), 143 msr!(msr_index::MSR_KERNEL_GS_BASE), 144 msr!(msr_index::MSR_SYSCALL_MASK), 145 msr!(msr_index::MSR_IA32_TSC), 146 msr_data!(msr_index::MSR_MTRRdefType, MTRR_ENABLE | MTRR_MEM_TYPE_WB), 147 ]) 148 .unwrap() 149 } 150