1 // Copyright © 2019 Intel Corporation 2 // 3 // SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause 4 // 5 // Copyright © 2020, Microsoft Corporation 6 // 7 // Copyright 2018-2019 CrowdStrike, Inc. 8 // 9 // 10 use std::fmt; 11 12 use serde::{Deserialize, Serialize}; 13 14 use crate::arch::x86::{ 15 CpuIdEntry, DescriptorTable, FpuState, LapicState, MsrEntry, SegmentRegister, SpecialRegisters, 16 }; 17 18 pub mod emulator; 19 20 /// 21 /// Export generically-named wrappers of mshv_bindings for Unix-based platforms 22 /// 23 pub use { 24 mshv_bindings::hv_cpuid_entry, mshv_bindings::mshv_user_mem_region as MemoryRegion, 25 mshv_bindings::msr_entry, mshv_bindings::AllVpStateComponents, mshv_bindings::CpuId, 26 mshv_bindings::DebugRegisters, mshv_bindings::FloatingPointUnit, 27 mshv_bindings::LapicState as MshvLapicState, mshv_bindings::MiscRegs as MiscRegisters, 28 mshv_bindings::MsrList, mshv_bindings::Msrs as MsrEntries, mshv_bindings::Msrs, 29 mshv_bindings::SegmentRegister as MshvSegmentRegister, 30 mshv_bindings::SpecialRegisters as MshvSpecialRegisters, 31 mshv_bindings::StandardRegisters as MshvStandardRegisters, mshv_bindings::SuspendRegisters, 32 mshv_bindings::TableRegister, mshv_bindings::VcpuEvents, mshv_bindings::XSave as Xsave, 33 mshv_bindings::Xcrs as ExtendedControlRegisters, 34 }; 35 36 #[derive(Clone, Serialize, Deserialize)] 37 pub struct VcpuMshvState { 38 pub msrs: Vec<MsrEntry>, 39 pub vcpu_events: VcpuEvents, 40 pub regs: MshvStandardRegisters, 41 pub sregs: MshvSpecialRegisters, 42 pub fpu: FpuState, 43 pub xcrs: ExtendedControlRegisters, 44 pub dbg: DebugRegisters, 45 pub misc: MiscRegisters, 46 pub vp_states: AllVpStateComponents, 47 } 48 49 #[derive(Clone, Copy, Debug, Default, Serialize, Deserialize)] 50 pub struct MshvClockData { 51 pub ref_time: u64, 52 } 53 54 impl fmt::Display for VcpuMshvState { fmt(&self, f: &mut fmt::Formatter) -> fmt::Result55 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 56 let expected_num_msrs = self.msrs.len(); 57 let mut msr_entries = vec![vec![0; 2]; expected_num_msrs]; 58 59 for (i, entry) in self.msrs.iter().enumerate() { 60 msr_entries[i][1] = entry.data; 61 msr_entries[i][0] = entry.index as u64; 62 } 63 write!(f, "Number of MSRs: {}: MSRs: {:#010X?}, -- VCPU Events: {:?} -- Standard registers: {:?} Special Registers: {:?} ---- Floating Point Unit: {:?} --- Extended Control Register: {:?} --- DBG: {:?} --- VP States: {:?}", 64 msr_entries.len(), 65 msr_entries, 66 self.vcpu_events, 67 self.regs, 68 self.sregs, 69 self.fpu, 70 self.xcrs, 71 self.dbg, 72 self.vp_states, 73 ) 74 } 75 } 76 77 impl From<SegmentRegister> for MshvSegmentRegister { from(s: SegmentRegister) -> Self78 fn from(s: SegmentRegister) -> Self { 79 Self { 80 base: s.base, 81 limit: s.limit, 82 selector: s.selector, 83 type_: s.type_, 84 present: s.present, 85 dpl: s.dpl, 86 db: s.db, 87 s: s.s, 88 l: s.l, 89 g: s.g, 90 avl: s.avl, 91 unusable: s.unusable, 92 ..Default::default() 93 } 94 } 95 } 96 97 impl From<MshvSegmentRegister> for SegmentRegister { from(s: MshvSegmentRegister) -> Self98 fn from(s: MshvSegmentRegister) -> Self { 99 Self { 100 base: s.base, 101 limit: s.limit, 102 selector: s.selector, 103 type_: s.type_, 104 present: s.present, 105 dpl: s.dpl, 106 db: s.db, 107 s: s.s, 108 l: s.l, 109 g: s.g, 110 avl: s.avl, 111 unusable: s.unusable, 112 } 113 } 114 } 115 116 impl From<DescriptorTable> for TableRegister { from(dt: DescriptorTable) -> Self117 fn from(dt: DescriptorTable) -> Self { 118 Self { 119 base: dt.base, 120 limit: dt.limit, 121 } 122 } 123 } 124 125 impl From<TableRegister> for DescriptorTable { from(dt: TableRegister) -> Self126 fn from(dt: TableRegister) -> Self { 127 Self { 128 base: dt.base, 129 limit: dt.limit, 130 } 131 } 132 } 133 134 impl From<SpecialRegisters> for MshvSpecialRegisters { from(s: SpecialRegisters) -> Self135 fn from(s: SpecialRegisters) -> Self { 136 Self { 137 cs: s.cs.into(), 138 ds: s.ds.into(), 139 es: s.es.into(), 140 fs: s.fs.into(), 141 gs: s.gs.into(), 142 ss: s.ss.into(), 143 tr: s.tr.into(), 144 ldt: s.ldt.into(), 145 gdt: s.gdt.into(), 146 idt: s.idt.into(), 147 cr0: s.cr0, 148 cr2: s.cr2, 149 cr3: s.cr3, 150 cr4: s.cr4, 151 cr8: s.cr8, 152 efer: s.efer, 153 apic_base: s.apic_base, 154 interrupt_bitmap: s.interrupt_bitmap, 155 } 156 } 157 } 158 159 impl From<MshvSpecialRegisters> for SpecialRegisters { from(s: MshvSpecialRegisters) -> Self160 fn from(s: MshvSpecialRegisters) -> Self { 161 Self { 162 cs: s.cs.into(), 163 ds: s.ds.into(), 164 es: s.es.into(), 165 fs: s.fs.into(), 166 gs: s.gs.into(), 167 ss: s.ss.into(), 168 tr: s.tr.into(), 169 ldt: s.ldt.into(), 170 gdt: s.gdt.into(), 171 idt: s.idt.into(), 172 cr0: s.cr0, 173 cr2: s.cr2, 174 cr3: s.cr3, 175 cr4: s.cr4, 176 cr8: s.cr8, 177 efer: s.efer, 178 apic_base: s.apic_base, 179 interrupt_bitmap: s.interrupt_bitmap, 180 } 181 } 182 } 183 184 impl From<CpuIdEntry> for hv_cpuid_entry { from(e: CpuIdEntry) -> Self185 fn from(e: CpuIdEntry) -> Self { 186 Self { 187 function: e.function, 188 index: e.index, 189 flags: e.flags, 190 eax: e.eax, 191 ebx: e.ebx, 192 ecx: e.ecx, 193 edx: e.edx, 194 ..Default::default() 195 } 196 } 197 } 198 199 impl From<hv_cpuid_entry> for CpuIdEntry { from(e: hv_cpuid_entry) -> Self200 fn from(e: hv_cpuid_entry) -> Self { 201 Self { 202 function: e.function, 203 index: e.index, 204 flags: e.flags, 205 eax: e.eax, 206 ebx: e.ebx, 207 ecx: e.ecx, 208 edx: e.edx, 209 } 210 } 211 } 212 213 impl From<FloatingPointUnit> for FpuState { from(s: FloatingPointUnit) -> Self214 fn from(s: FloatingPointUnit) -> Self { 215 Self { 216 fpr: s.fpr, 217 fcw: s.fcw, 218 fsw: s.fsw, 219 ftwx: s.ftwx, 220 last_opcode: s.last_opcode, 221 last_ip: s.last_ip, 222 last_dp: s.last_dp, 223 xmm: s.xmm, 224 mxcsr: s.mxcsr, 225 } 226 } 227 } 228 229 impl From<FpuState> for FloatingPointUnit { from(s: FpuState) -> Self230 fn from(s: FpuState) -> Self { 231 Self { 232 fpr: s.fpr, 233 fcw: s.fcw, 234 fsw: s.fsw, 235 ftwx: s.ftwx, 236 last_opcode: s.last_opcode, 237 last_ip: s.last_ip, 238 last_dp: s.last_dp, 239 xmm: s.xmm, 240 mxcsr: s.mxcsr, 241 ..Default::default() 242 } 243 } 244 } 245 246 impl From<LapicState> for MshvLapicState { from(s: LapicState) -> Self247 fn from(s: LapicState) -> Self { 248 Self { regs: s.regs } 249 } 250 } 251 252 impl From<MshvLapicState> for LapicState { from(s: MshvLapicState) -> Self253 fn from(s: MshvLapicState) -> Self { 254 Self { regs: s.regs } 255 } 256 } 257 258 impl From<msr_entry> for MsrEntry { from(e: msr_entry) -> Self259 fn from(e: msr_entry) -> Self { 260 Self { 261 index: e.index, 262 data: e.data, 263 } 264 } 265 } 266 267 impl From<MsrEntry> for msr_entry { from(e: MsrEntry) -> Self268 fn from(e: MsrEntry) -> Self { 269 Self { 270 index: e.index, 271 data: e.data, 272 ..Default::default() 273 } 274 } 275 } 276